enable full 224KB flash for ch32v203 with flash enhanced read mode in SystemInit (better with startup).

add flash with wlink-rs
This commit is contained in:
hathach
2024-07-10 22:48:06 +07:00
parent 8d5dbb9577
commit c1175b7013
13 changed files with 75 additions and 93 deletions

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@@ -1,6 +1,8 @@
set(MCU_VARIANT D6)
set(LD_FLASH_SIZE 64K)
# 64KB zero-wait, 224KB total flash
#set(LD_FLASH_SIZE 64K)
set(LD_FLASH_SIZE 224K)
set(LD_RAM_SIZE 20K)
# set(LD_FILE_GNU ${CMAKE_CURRENT_LIST_DIR}/../../linker/${CH32_FAMILY}_tinyuf2.ld)
@@ -8,6 +10,7 @@ set(LD_RAM_SIZE 20K)
function(update_board TARGET)
target_compile_definitions(${TARGET} PUBLIC
SYSCLK_FREQ_144MHz_HSE=144000000
CH32_FLASH_ENHANCE_READ_MODE=1
CFG_EXAMPLE_MSC_DUAL_READONLY
)
endfunction()

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@@ -2,8 +2,10 @@ MCU_VARIANT = D6
CFLAGS += \
-DSYSCLK_FREQ_144MHz_HSE=144000000 \
-DCH32_FLASH_ENHANCE_READ_MODE=1 \
-DCFG_EXAMPLE_MSC_DUAL_READONLY \
# 64KB zero-wait, 224KB total flash
LDFLAGS += \
-Wl,--defsym=__FLASH_SIZE=64K \
-Wl,--defsym=__FLASH_SIZE=224K \
-Wl,--defsym=__RAM_SIZE=20K \

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@@ -1,11 +1,14 @@
set(MCU_VARIANT D6)
set(LD_FLASH_SIZE 32K)
# 32KB zero-wait, 224KB total flash
#set(LD_FLASH_SIZE 32K)
set(LD_FLASH_SIZE 224K)
set(LD_RAM_SIZE 10K)
function(update_board TARGET)
target_compile_definitions(${TARGET} PUBLIC
SYSCLK_FREQ_144MHz_HSI=144000000
CH32_FLASH_ENHANCE_READ_MODE=1
CFG_EXAMPLE_MSC_DUAL_READONLY
)
endfunction()

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@@ -2,8 +2,10 @@ MCU_VARIANT = D6
CFLAGS += \
-DSYSCLK_FREQ_144MHz_HSI=144000000 \
-DCH32_FLASH_ENHANCE_READ_MODE=1 \
-DCFG_EXAMPLE_MSC_DUAL_READONLY \
# 32KB zero-wait, 224KB total flash
LDFLAGS += \
-Wl,--defsym=__FLASH_SIZE=32K \
-Wl,--defsym=__FLASH_SIZE=224K \
-Wl,--defsym=__RAM_SIZE=10K \

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@@ -1,11 +1,14 @@
set(MCU_VARIANT D6)
set(LD_FLASH_SIZE 64K)
# 64KB zero-wait, 224KB total flash
#set(LD_FLASH_SIZE 64K)
set(LD_FLASH_SIZE 224K)
set(LD_RAM_SIZE 20K)
function(update_board TARGET)
target_compile_definitions(${TARGET} PUBLIC
SYSCLK_FREQ_144MHz_HSE=144000000
CH32_FLASH_ENHANCE_READ_MODE=1
CFG_EXAMPLE_MSC_DUAL_READONLY
)
endfunction()

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@@ -2,8 +2,10 @@ MCU_VARIANT = D6
CFLAGS += \
-DSYSCLK_FREQ_144MHz_HSE=144000000 \
-DCH32_FLASH_ENHANCE_READ_MODE=1 \
-DCFG_EXAMPLE_MSC_DUAL_READONLY \
# 64KB zero-wait , 224KB total flash
LDFLAGS += \
-Wl,--defsym=__FLASH_SIZE=64K \
-Wl,--defsym=__FLASH_SIZE=224K \
-Wl,--defsym=__RAM_SIZE=20K \

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@@ -62,7 +62,6 @@ void USBWakeUp_IRQHandler(void) {
#if CFG_TUSB_OS == OPT_OS_NONE
volatile uint32_t system_ticks = 0;
__attribute__((interrupt))
@@ -84,7 +83,6 @@ uint32_t SysTick_Config(uint32_t ticks) {
uint32_t board_millis(void) {
return system_ticks;
}
#endif
void board_init(void) {
@@ -140,29 +138,29 @@ void board_init(void) {
}
void board_reset_to_bootloader(void) {
board_led_write(true);
__disable_irq();
#if CFG_TUD_ENABLED
tud_deinit(0);
RCC_APB1PeriphResetCmd(RCC_APB1Periph_USB, ENABLE);
RCC_APB1PeriphResetCmd(RCC_APB1Periph_USB, DISABLE);
#endif
SysTick->CTLR = 0;
for (int i = WWDG_IRQn; i< DMA1_Channel8_IRQn; i++) {
NVIC_DisableIRQ(i);
}
__enable_irq();
// define function pointer to BOOT ROM address
void (*bootloader_entry)(void) = (void (*)(void))0x1FFF8000;
bootloader_entry();
board_led_write(false);
// board_led_write(true);
//
// __disable_irq();
//
// #if CFG_TUD_ENABLED
// tud_deinit(0);
// RCC_APB1PeriphResetCmd(RCC_APB1Periph_USB, ENABLE);
// RCC_APB1PeriphResetCmd(RCC_APB1Periph_USB, DISABLE);
// #endif
//
// SysTick->CTLR = 0;
// for (int i = WWDG_IRQn; i< DMA1_Channel8_IRQn; i++) {
// NVIC_DisableIRQ(i);
// }
//
// __enable_irq();
//
// // define function pointer to BOOT ROM address
// void (*bootloader_entry)(void) = (void (*)(void))0x1FFF8000;
//
// bootloader_entry();
//
// board_led_write(false);
// while(1) { }
}

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@@ -131,6 +131,7 @@ function(family_configure_example TARGET RTOS)
# Flashing
family_add_bin_hex(${TARGET})
family_flash_openocd_wch(${TARGET})
family_flash_wlink_rs(${TARGET})
#family_add_uf2(${TARGET} ${UF2_FAMILY_ID})
#family_flash_uf2(${TARGET} ${UF2_FAMILY_ID})

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@@ -60,4 +60,5 @@ INC += \
FREERTOS_PORTABLE_SRC = $(FREERTOS_PORTABLE_PATH)/RISC-V
OPENOCD_WCH_OPTION=-f $(TOP)/$(FAMILY_PATH)/wch-riscv.cfg
flash: flash-openocd-wch
flash: flash-wlink-rs
#flash: flash-openocd-wch

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@@ -19,9 +19,9 @@
* If none of the define below is enabled, the HSI is used as System clock source.
*/
//#define SYSCLK_FREQ_HSE HSE_VALUE
//#define SYSCLK_FREQ_48MHz_HSE 48000000
// #define SYSCLK_FREQ_48MHz_HSE 48000000
//#define SYSCLK_FREQ_56MHz_HSE 56000000
//#define SYSCLK_FREQ_72MHz_HSE 72000000
// #define SYSCLK_FREQ_72MHz_HSE 72000000
// #define SYSCLK_FREQ_96MHz_HSE 96000000
//#define SYSCLK_FREQ_120MHz_HSE 120000000
//#define SYSCLK_FREQ_144MHz_HSE 144000000
@@ -109,6 +109,13 @@ static void SetSysClockTo144_HSI( void );
*/
void SystemInit (void)
{
// Enable Flash enhance read mode for full 224KB
#if defined(CH32_FLASH_ENHANCE_READ_MODE) && CH32_FLASH_ENHANCE_READ_MODE == 1
FLASH_Unlock_Fast();
FLASH->CTLR |= (1 << 24);
FLASH_Lock_Fast();
#endif
RCC->CTLR |= (uint32_t)0x00000001;
RCC->CFGR0 &= (uint32_t)0xF8FF0000;
RCC->CTLR &= (uint32_t)0xFEF6FFFF;

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@@ -455,6 +455,18 @@ function(family_flash_openocd_wch TARGET)
family_flash_openocd(${TARGET})
endfunction()
# Add flash with https://github.com/ch32-rs/wlink
function(family_flash_wlink_rs TARGET)
if (NOT DEFINED WLINK_RS)
set(WLINK_RS wlink)
endif ()
add_custom_target(${TARGET}-wlink-rs
DEPENDS ${TARGET}
COMMAND ${WLINK_RS} flash $<TARGET_FILE:${TARGET}>
)
endfunction()
# Add flash pycod target
function(family_flash_pyocd TARGET)
if (NOT DEFINED PYOC)