diff --git a/demos/host/host_freertos/.cproject b/demos/host/host_freertos/.cproject
index 7f1d3643d..c734c75a4 100644
--- a/demos/host/host_freertos/.cproject
+++ b/demos/host/host_freertos/.cproject
@@ -30,7 +30,7 @@
-
+
-
+
@@ -67,7 +68,7 @@
-
+
@@ -693,7 +694,7 @@
-
+
-
+
@@ -732,7 +733,7 @@
-
+
@@ -2081,6 +2082,7 @@
+
@@ -2089,73 +2091,79 @@
<?xml version="1.0" encoding="UTF-8"?>
<TargetConfig>
-<Properties property_0="" property_3="NXP" property_4="LPC1769" property_count="5" version="1"/>
-<infoList vendor="NXP"><info chip="LPC1769" match_id="0x26113F37" name="LPC1769" package="lpc17_lqfp100.xml"><chip><name>LPC1769</name>
-<family>LPC17xx</family>
+<Properties property_0="" property_3="NXP" property_4="LPC4330" property_count="5" version="1"/>
+<infoList vendor="NXP"><info chip="LPC4330" match_id="0x0" name="LPC4330" resetscript="LPC18LPC43ExternalFLASHBootResetscript.scp" stub="crt_emu_lpc18_43_nxp"><chip><name>LPC4330</name>
+<family>LPC43xx</family>
<vendor>NXP (formerly Philips)</vendor>
<reset board="None" core="Real" sys="Real"/>
<clock changeable="TRUE" freq="20MHz" is_accurate="TRUE"/>
<memory can_program="true" id="Flash" is_ro="true" type="Flash"/>
<memory id="RAM" type="RAM"/>
<memory id="Periph" is_volatile="true" type="Peripheral"/>
-<memoryInstance derived_from="Flash" id="MFlash512" location="0x0" size="0x80000"/>
-<memoryInstance derived_from="RAM" id="RamLoc32" location="0x10000000" size="0x8000"/>
-<memoryInstance derived_from="RAM" id="RamAHB32" location="0x2007c000" size="0x8000"/>
-<prog_flash blocksz="0x1000" location="0" maxprgbuff="0x1000" progwithcode="TRUE" size="0x10000"/>
-<prog_flash blocksz="0x8000" location="0x10000" maxprgbuff="0x1000" progwithcode="TRUE" size="0x70000"/>
-<peripheralInstance derived_from="LPC17_NVIC" id="NVIC" location="0xE000E000"/>
-<peripheralInstance derived_from="TIMER" enable="SYSCTL.PCONP.PCTIM0&0x1" id="TIMER0" location="0x40004000"/>
-<peripheralInstance derived_from="TIMER" enable="SYSCTL.PCONP.PCTIM1&0x1" id="TIMER1" location="0x40008000"/>
-<peripheralInstance derived_from="TIMER" enable="SYSCTL.PCONP.PCTIM2&0x1" id="TIMER2" location="0x40090000"/>
-<peripheralInstance derived_from="TIMER" enable="SYSCTL.PCONP.PCTIM3&0x1" id="TIMER3" location="0x40094000"/>
-<peripheralInstance derived_from="LPC17_RIT" enable="SYSCTL.PCONP.PCRIT&0x1" id="RIT" location="0x400B0000"/>
-<peripheralInstance derived_from="FGPIO" enable="SYSCTL.PCONP.PCGPIO&0x1" id="GPIO0" location="0x2009C000"/>
-<peripheralInstance derived_from="FGPIO" enable="SYSCTL.PCONP.PCGPIO&0x1" id="GPIO1" location="0x2009C020"/>
-<peripheralInstance derived_from="FGPIO" enable="SYSCTL.PCONP.PCGPIO&0x1" id="GPIO2" location="0x2009C040"/>
-<peripheralInstance derived_from="FGPIO" enable="SYSCTL.PCONP.PCGPIO&0x1" id="GPIO3" location="0x2009C060"/>
-<peripheralInstance derived_from="FGPIO" enable="SYSCTL.PCONP.PCGPIO&0x1" id="GPIO4" location="0x2009C080"/>
-<peripheralInstance derived_from="LPC17_I2S" enable="SYSCTL.PCONP&0x08000000" id="I2S" location="0x400A8000"/>
-<peripheralInstance derived_from="LPC17_SYSCTL" id="SYSCTL" location="0x400FC000"/>
-<peripheralInstance derived_from="LPC17_DAC" enable="PCB.PINSEL1.P0_26&0x2=2" id="DAC" location="0x4008C000"/>
-<peripheralInstance derived_from="LPC17xx_UART" enable="SYSCTL.PCONP.PCUART0&0x1" id="UART0" location="0x4000C000"/>
-<peripheralInstance derived_from="LPC17xx_UART_MODEM" enable="SYSCTL.PCONP.PCUART1&0x1" id="UART1" location="0x40010000"/>
-<peripheralInstance derived_from="LPC17xx_UART" enable="SYSCTL.PCONP.PCUART2&0x1" id="UART2" location="0x40098000"/>
-<peripheralInstance derived_from="LPC17xx_UART" enable="SYSCTL.PCONP.PCUART3&0x1" id="UART3" location="0x4009C000"/>
-<peripheralInstance derived_from="SPI" enable="SYSCTL.PCONP.PCSPI&0x1" id="SPI" location="0x40020000"/>
-<peripheralInstance derived_from="LPC17_SSP" enable="SYSCTL.PCONP.PCSSP0&0x1" id="SSP0" location="0x40088000"/>
-<peripheralInstance derived_from="LPC17_SSP" enable="SYSCTL.PCONP.PCSSP1&0x1" id="SSP1" location="0x40030000"/>
-<peripheralInstance derived_from="LPC17_ADC" enable="SYSCTL.PCONP.PCAD&0x1" id="ADC" location="0x40034000"/>
-<peripheralInstance derived_from="LPC17_USBINTST" enable="USBCLKCTL.USBClkCtrl&0x12" id="USBINTSTAT" location="0x400fc1c0"/>
-<peripheralInstance derived_from="LPC17_USB_CLK_CTL" id="USBCLKCTL" location="0x5000cff4"/>
-<peripheralInstance derived_from="LPC17_USBDEV" enable="USBCLKCTL.USBClkSt&0x12=0x12" id="USBDEV" location="0x5000C200"/>
-<peripheralInstance derived_from="LPC17_PWM" enable="SYSCTL.PCONP.PWM1&0x1" id="PWM" location="0x40018000"/>
-<peripheralInstance derived_from="LPC17_I2C" enable="SYSCTL.PCONP.PCI2C0&0x1" id="I2C0" location="0x4001C000"/>
-<peripheralInstance derived_from="LPC17_I2C" enable="SYSCTL.PCONP.PCI2C1&0x1" id="I2C1" location="0x4005C000"/>
-<peripheralInstance derived_from="LPC17_I2C" enable="SYSCTL.PCONP.PCI2C2&0x1" id="I2C2" location="0x400A0000"/>
-<peripheralInstance derived_from="LPC17_DMA" enable="SYSCTL.PCONP.PCGPDMA&0x1" id="DMA" location="0x50004000"/>
-<peripheralInstance derived_from="LPC17_ENET" enable="SYSCTL.PCONP.PCENET&0x1" id="ENET" location="0x50000000"/>
-<peripheralInstance derived_from="CM3_DCR" id="DCR" location="0xE000EDF0"/>
-<peripheralInstance derived_from="LPC17_PCB" id="PCB" location="0x4002c000"/>
-<peripheralInstance derived_from="LPC17_QEI" enable="SYSCTL.PCONP.PCQEI&0x1" id="QEI" location="0x400bc000"/>
-<peripheralInstance derived_from="LPC17_USBHOST" enable="USBCLKCTL.USBClkSt&0x11=0x11" id="USBHOST" location="0x5000C000"/>
-<peripheralInstance derived_from="LPC17_USBOTG" enable="USBCLKCTL.USBClkSt&0x1c=0x1c" id="USBOTG" location="0x5000C000"/>
-<peripheralInstance derived_from="LPC17_RTC" enable="SYSCTL.PCONP.PCRTC&0x1" id="RTC" location="0x40024000"/>
-<peripheralInstance derived_from="MPU" id="MPU" location="0xE000ED90"/>
-<peripheralInstance derived_from="LPC1x_WDT" id="WDT" location="0x40000000"/>
-<peripheralInstance derived_from="LPC17_FLASHCFG" id="FLASHACCEL" location="0x400FC000"/>
-<peripheralInstance derived_from="GPIO_INT" id="GPIOINTMAP" location="0x40028080"/>
-<peripheralInstance derived_from="LPC17_CANAFR" enable="SYSCTL.PCONP.PCCAN1&0x1|SYSCTL.PCONP.PCCAN2&0x1" id="CANAFR" location="0x4003C000"/>
-<peripheralInstance derived_from="LPC17_CANCEN" enable="SYSCTL.PCONP.PCCAN1&0x1|SYSCTL.PCONP.PCCAN2&0x1" id="CANCEN" location="0x40040000"/>
-<peripheralInstance derived_from="LPC17_CANWAKESLEEP" id="CANWAKESLEEP" location="0x400FC110"/>
-<peripheralInstance derived_from="LPC17_CANCON" enable="SYSCTL.PCONP.PCCAN1&0x1" id="CANCON1" location="0x40044000"/>
-<peripheralInstance derived_from="LPC17_CANCON" enable="SYSCTL.PCONP.PCCAN2&0x1" id="CANCON2" location="0x40048000"/>
-<peripheralInstance derived_from="LPC17_MCPWM" enable="SYSCTL.PCONP.PCMCPWM&0x1" id="MCPWM" location="0x400B8000"/>
-<peripheralInstance derived_from="LPC17_FMC" id="FMC" location="0x40084000"/>
+<memoryInstance derived_from="RAM" id="RamLoc128" location="0x10000000" size="0x20000"/>
+<memoryInstance derived_from="RAM" id="RamLoc72" location="0x10080000" size="0x12000"/>
+<memoryInstance derived_from="RAM" id="RamAHB32" location="0x20000000" size="0x8000"/>
+<memoryInstance derived_from="RAM" id="RamAHB16" location="0x20008000" size="0x4000"/>
+<memoryInstance derived_from="RAM" id="RamAHB_ETB16" location="0x2000c000" size="0x4000"/>
+<peripheralInstance derived_from="V7M_MPU" id="MPU" location="0xe000ed90"/>
+<peripheralInstance derived_from="V7M_NVIC" id="NVIC" location="0xe000e000"/>
+<peripheralInstance derived_from="V7M_DCR" id="DCR" location="0xe000edf0"/>
+<peripheralInstance derived_from="V7M_ITM" id="ITM" location="0xe0000000"/>
+<peripheralInstance derived_from="SCT" id="SCT" location="0x40000000"/>
+<peripheralInstance derived_from="GPDMA" id="GPDMA" location="0x40002000"/>
+<peripheralInstance derived_from="SPIFI" id="SPIFI" location="0x40003000"/>
+<peripheralInstance derived_from="SDMMC" id="SDMMC" location="0x40004000"/>
+<peripheralInstance derived_from="EMC" id="EMC" location="0x40005000"/>
+<peripheralInstance derived_from="USB0" id="USB0" location="0x40006000"/>
+<peripheralInstance derived_from="USB1" id="USB1" location="0x40007000"/>
+<peripheralInstance derived_from="EEPROM" id="EEPROM" location="0x4000e000"/>
+<peripheralInstance derived_from="ETHERNET" id="ETHERNET" location="0x40010000"/>
+<peripheralInstance derived_from="ATIMER" id="ATIMER" location="0x40040000"/>
+<peripheralInstance derived_from="REGFILE" id="REGFILE" location="0x40041000"/>
+<peripheralInstance derived_from="PMC" id="PMC" location="0x40042000"/>
+<peripheralInstance derived_from="CREG" id="CREG" location="0x40043000"/>
+<peripheralInstance derived_from="EVENTROUTER" id="EVENTROUTER" location="0x40044000"/>
+<peripheralInstance derived_from="RTC" id="RTC" location="0x40046000"/>
+<peripheralInstance derived_from="CGU" id="CGU" location="0x40050000"/>
+<peripheralInstance derived_from="CCU1" id="CCU1" location="0x40051000"/>
+<peripheralInstance derived_from="CCU2" id="CCU2" location="0x40052000"/>
+<peripheralInstance derived_from="RGU" id="RGU" location="0x40053000"/>
+<peripheralInstance derived_from="WWDT" id="WWDT" location="0x40080000"/>
+<peripheralInstance derived_from="USART0" id="USART0" location="0x40081000"/>
+<peripheralInstance derived_from="USART2" id="USART2" location="0x400c1000"/>
+<peripheralInstance derived_from="USART3" id="USART3" location="0x400c2000"/>
+<peripheralInstance derived_from="UART1" id="UART1" location="0x40082000"/>
+<peripheralInstance derived_from="SSP0" id="SSP0" location="0x40083000"/>
+<peripheralInstance derived_from="SSP1" id="SSP1" location="0x400c5000"/>
+<peripheralInstance derived_from="TIMER0" id="TIMER0" location="0x40084000"/>
+<peripheralInstance derived_from="TIMER1" id="TIMER1" location="0x40085000"/>
+<peripheralInstance derived_from="TIMER2" id="TIMER2" location="0x400c3000"/>
+<peripheralInstance derived_from="TIMER3" id="TIMER3" location="0x400c4000"/>
+<peripheralInstance derived_from="SCU" id="SCU" location="0x40086000"/>
+<peripheralInstance derived_from="GPIO-PIN-INT" id="GPIO-PIN-INT" location="0x40087000"/>
+<peripheralInstance derived_from="GPIO-GROUP-INT0" id="GPIO-GROUP-INT0" location="0x40088000"/>
+<peripheralInstance derived_from="GPIO-GROUP-INT1" id="GPIO-GROUP-INT1" location="0x40089000"/>
+<peripheralInstance derived_from="MCPWM" id="MCPWM" location="0x400a0000"/>
+<peripheralInstance derived_from="I2C0" id="I2C0" location="0x400a1000"/>
+<peripheralInstance derived_from="I2C1" id="I2C1" location="0x400e0000"/>
+<peripheralInstance derived_from="I2S0" id="I2S0" location="0x400a2000"/>
+<peripheralInstance derived_from="I2S1" id="I2S1" location="0x400a3000"/>
+<peripheralInstance derived_from="C-CAN1" id="C-CAN1" location="0x400a4000"/>
+<peripheralInstance derived_from="RITIMER" id="RITIMER" location="0x400c0000"/>
+<peripheralInstance derived_from="QEI" id="QEI" location="0x400c6000"/>
+<peripheralInstance derived_from="GIMA" id="GIMA" location="0x400c7000"/>
+<peripheralInstance derived_from="DAC" id="DAC" location="0x400e1000"/>
+<peripheralInstance derived_from="C-CAN0" id="C-CAN0" location="0x400e2000"/>
+<peripheralInstance derived_from="ADC0" id="ADC0" location="0x400e3000"/>
+<peripheralInstance derived_from="ADC1" id="ADC1" location="0x400e4000"/>
+<peripheralInstance derived_from="GPIO-PORT" id="GPIO-PORT" location="0x400f4000"/>
+<peripheralInstance derived_from="SPI" id="SPI" location="0x40100000"/>
+<peripheralInstance derived_from="SGPIO" id="SGPIO" location="0x40101000"/>
</chip>
-<processor><name gcc_name="cortex-m3">Cortex-M3</name>
+<processor><name gcc_name="cortex-m4">Cortex-M4</name>
<family>Cortex-M</family>
</processor>
-<link href="nxp_lpcxxxx_peripheral.xme" show="embed" type="simple"/>
+<link href="nxp_lpc43xx_peripheral.xme" show="embed" type="simple"/>
</info>
</infoList>
</TargetConfig>
diff --git a/demos/host/host_freertos/lwipopts.h b/demos/host/host_freertos/lwipopts.h
deleted file mode 100644
index 96758296e..000000000
--- a/demos/host/host_freertos/lwipopts.h
+++ /dev/null
@@ -1,158 +0,0 @@
-/*
- * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. The name of the author may not be used to endorse or promote products
- * derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
- * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
- * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
- * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
- * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
- * OF SUCH DAMAGE.
- *
- * This file is part of the lwIP TCP/IP stack.
- *
- * Author: Adam Dunkels
- *
- */
-
-#ifndef __LWIPOPTS_H_
-#define __LWIPOPTS_H_
-
-//--------------------------------------------------------------------+
-// Platform
-//--------------------------------------------------------------------+
-#define NO_SYS 0 // 1 : No RTOS
-
-#define NO_SYS_NO_TIMERS 0
-
-//--------------------------------------------------------------------+
-// Memory
-//--------------------------------------------------------------------+
-#define SYS_LIGHTWEIGHT_PROT 0
-
-#define MEM_ALIGNMENT 4
-
-/* the number of buffers in the pbuf pool. In zero-copy mode, these buffers are
- located in peripheral RAM. In copied mode, they are located in internal IRAM */
-#define PBUF_POOL_SIZE 5
-
-#define ETH_PAD_SIZE 0
-
-#define IP_SOF_BROADCAST 1
-#define IP_SOF_BROADCAST_RECV 1
-
-//--------------------------------------------------------------------+
-// Checksum Options
-// 1 : Checksum is generated in software
-// 0 : Checksum is generated in hardware
-//--------------------------------------------------------------------+
-/* The ethernet FCS is performed in hardware. The IP, TCP, and UDP
- CRCs still need to be done in hardware. */
-#define CHECKSUM_GEN_IP 1
-#define CHECKSUM_GEN_UDP 1
-#define CHECKSUM_GEN_TCP 1
-#define CHECKSUM_CHECK_IP 1
-#define CHECKSUM_CHECK_UDP 1
-#define CHECKSUM_CHECK_TCP 1
-#define LWIP_CHECKSUM_ON_COPY 1
-
-/* Use LWIP version of htonx() to allow generic functionality across
- all platforms. If you are using the Cortex Mx devices, you might
- be able to use the Cortex __rev instruction instead. */
-#define LWIP_PLATFORM_BYTESWAP 0
-
-/* Non-static memory, used with DMA pool */
-#define MEM_SIZE (6 * 1024)
-
-//--------------------------------------------------------------------+
-// Protocols
-//--------------------------------------------------------------------+
-#define LWIP_RAW 0
-#define LWIP_DHCP 0
-#define LWIP_SNMP 0
-#define LWIP_IGMP 0
-#define LWIP_DNS 0
-
-#define LWIP_UDP 0
-#define LWIP_TCP 1
-
-/* Hostname can be used */
-#define LWIP_NETIF_HOSTNAME 1
-
-#define LWIP_BROADCAST_PING 1
-
-//--------------------------------------------------------------------+
-// TCP Options
-//--------------------------------------------------------------------+
-/* MSS should match the hardware packet size */
-#define TCP_MSS 1460
-#define TCP_SND_BUF (2 * TCP_MSS)
-
-//--------------------------------------------------------------------+
-// API
-//--------------------------------------------------------------------+
-#define LWIP_SOCKET 0
-#define LWIP_NETCONN 1
-
-#define MEMP_NUM_SYS_TIMEOUT 100 // FIXME check settings
-
-//--------------------------------------------------------------------+
-// Statistics options
-//--------------------------------------------------------------------+
-#define LWIP_STATS 0
-#define LINK_STATS 0
-#define LWIP_STATS_DISPLAY 0
-
-//--------------------------------------------------------------------+
-// DEBUG options
-//--------------------------------------------------------------------+
-#define LWIP_DEBUG
-
-/* There are more *_DEBUG options that can be selected.
- See opts.h. Make sure that LWIP_DEBUG is defined when
- building the code to use debug. */
-#define TCP_DEBUG LWIP_DBG_TRACE
-#define ETHARP_DEBUG LWIP_DBG_OFF
-#define PBUF_DEBUG LWIP_DBG_OFF
-#define IP_DEBUG LWIP_DBG_TRACE
-#define TCPIP_DEBUG LWIP_DBG_OFF
-#define DHCP_DEBUG LWIP_DBG_OFF
-#define UDP_DEBUG LWIP_DBG_OFF
-
-/* This define is custom for the LPC EMAC driver. Enabled it to
- get debug messages for the driver. */
-#define EMAC_DEBUG LWIP_DBG_TRACE
-#define UDP_LPC_EMAC LWIP_DBG_OFF
-
-//--------------------------------------------------------------------+
-// FreeRTOS
-//--------------------------------------------------------------------+
-
-#define DEFAULT_THREAD_PRIO (tskIDLE_PRIORITY + 1)
-#define DEFAULT_THREAD_STACKSIZE (256)
-#define DEFAULT_ACCEPTMBOX_SIZE 6
-#define DEFAULT_ACCEPTMBOX_SIZE 6
-#define DEFAULT_TCP_RECVMBOX_SIZE 6
-#define DEFAULT_UDP_RECVMBOX_SIZE 6
-
-/* TCPIP thread must run at higher priority than MAC threads! */
-#define TCPIP_THREAD_PRIO (configMAX_PRIORITIES - 1)
-#define TCPIP_THREAD_STACKSIZE (512)
-#define TCPIP_MBOX_SIZE 3
-
-#endif /* __LWIPOPTS_H_ */
diff --git a/demos/host/host_os_none/.cproject b/demos/host/host_os_none/.cproject
index eea415f96..e1977f87d 100644
--- a/demos/host/host_os_none/.cproject
+++ b/demos/host/host_os_none/.cproject
@@ -52,12 +52,14 @@
+
+
@@ -75,6 +77,7 @@
+
@@ -490,7 +493,7 @@
-
+
-
+
@@ -525,7 +528,7 @@
-
+