osal_spin skipping lock/unlock when executed in isr
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@@ -1020,16 +1020,11 @@ void dcd_int_handler(uint8_t rhport) {
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if (gintsts & GINTSTS_USBRST) {
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// USBRST is start of reset.
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#if TUP_MCU_MULTIPLE_CORE
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osal_spin_lock(&_dcd_spinlock, true);
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#endif
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dwc2->gintsts = GINTSTS_USBRST;
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handle_bus_reset(rhport);
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#if TUP_MCU_MULTIPLE_CORE
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osal_spin_lock(&_dcd_spinlock, true);
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handle_bus_reset(rhport);
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osal_spin_unlock(&_dcd_spinlock, true);
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#endif
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}
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if (gintsts & GINTSTS_ENUMDNE) {
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@@ -55,8 +55,8 @@ static const dwc2_controller_t _dwc2_controller[] = {
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// On ESP32 for consistency we associate
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// - Port0 to OTG_FS, and Port1 to OTG_HS
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static const dwc2_controller_t _dwc2_controller[] = {
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{ .reg_base = DWC2_FS_REG_BASE, .irqnum = ETS_USB_OTG11_CH0_INTR_SOURCE, .ep_count = 7, .ep_in_count = 5, .ep_fifo_size = 1024 },
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{ .reg_base = DWC2_HS_REG_BASE, .irqnum = ETS_USB_OTG_INTR_SOURCE, .ep_count = 16, .ep_in_count = 8, .ep_fifo_size = 4096 }
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{ .reg_base = DWC2_FS_REG_BASE, .irqnum = ETS_USB_OTG11_CH0_INTR_SOURCE, .ep_count = 7, .ep_in_count = 5, .ep_fifo_size = 1024 },
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{ .reg_base = DWC2_HS_REG_BASE, .irqnum = ETS_USB_OTG_INTR_SOURCE, .ep_count = 16, .ep_in_count = 8, .ep_fifo_size = 4096 }
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};
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#endif
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