osal_spin skipping lock/unlock when executed in isr

This commit is contained in:
hathach
2025-05-21 11:19:07 +07:00
parent a4875fefea
commit c1d23a0a92
7 changed files with 37 additions and 19 deletions

View File

@@ -1020,16 +1020,11 @@ void dcd_int_handler(uint8_t rhport) {
if (gintsts & GINTSTS_USBRST) {
// USBRST is start of reset.
#if TUP_MCU_MULTIPLE_CORE
osal_spin_lock(&_dcd_spinlock, true);
#endif
dwc2->gintsts = GINTSTS_USBRST;
handle_bus_reset(rhport);
#if TUP_MCU_MULTIPLE_CORE
osal_spin_lock(&_dcd_spinlock, true);
handle_bus_reset(rhport);
osal_spin_unlock(&_dcd_spinlock, true);
#endif
}
if (gintsts & GINTSTS_ENUMDNE) {

View File

@@ -55,8 +55,8 @@ static const dwc2_controller_t _dwc2_controller[] = {
// On ESP32 for consistency we associate
// - Port0 to OTG_FS, and Port1 to OTG_HS
static const dwc2_controller_t _dwc2_controller[] = {
{ .reg_base = DWC2_FS_REG_BASE, .irqnum = ETS_USB_OTG11_CH0_INTR_SOURCE, .ep_count = 7, .ep_in_count = 5, .ep_fifo_size = 1024 },
{ .reg_base = DWC2_HS_REG_BASE, .irqnum = ETS_USB_OTG_INTR_SOURCE, .ep_count = 16, .ep_in_count = 8, .ep_fifo_size = 4096 }
{ .reg_base = DWC2_FS_REG_BASE, .irqnum = ETS_USB_OTG11_CH0_INTR_SOURCE, .ep_count = 7, .ep_in_count = 5, .ep_fifo_size = 1024 },
{ .reg_base = DWC2_HS_REG_BASE, .irqnum = ETS_USB_OTG_INTR_SOURCE, .ep_count = 16, .ep_in_count = 8, .ep_fifo_size = 4096 }
};
#endif