osal_spin skipping lock/unlock when executed in isr

src/osal/osal_freertos.h

@@ -114,12 +114,16 @@ TU_ATTR_ALWAYS_INLINE static inline void osal_spin_init(osal_spinlock_t *ctx) {
 }
 
 TU_ATTR_ALWAYS_INLINE static inline void osal_spin_lock(osal_spinlock_t *ctx, bool in_isr) {
-  (void) in_isr;
+  if (!TUP_MCU_MULTIPLE_CORE && in_isr) {
+    return; // single core MCU does not need to lock in ISR
+  }
   portENTER_CRITICAL(ctx);
 }
 
 TU_ATTR_ALWAYS_INLINE static inline void osal_spin_unlock(osal_spinlock_t *ctx, bool in_isr) {
-  (void) in_isr;
+  if (!TUP_MCU_MULTIPLE_CORE && in_isr) {
+    return; // single core MCU does not need to lock in ISR
+  }
   portEXIT_CRITICAL(ctx);
 }
 
@@ -133,6 +137,10 @@ TU_ATTR_ALWAYS_INLINE static inline void osal_spin_init(osal_spinlock_t *ctx) {
 
 TU_ATTR_ALWAYS_INLINE static inline void osal_spin_lock(osal_spinlock_t *ctx, bool in_isr) {
   if (in_isr) {
+    if (!TUP_MCU_MULTIPLE_CORE) {
+      (void) ctx;
+      return; // single core MCU does not need to lock in ISR
+    }
     *ctx = taskENTER_CRITICAL_FROM_ISR();
   } else {
     taskENTER_CRITICAL();
@@ -140,8 +148,11 @@ TU_ATTR_ALWAYS_INLINE static inline void osal_spin_lock(osal_spinlock_t *ctx, bo
 }
 
 TU_ATTR_ALWAYS_INLINE static inline void osal_spin_unlock(osal_spinlock_t *ctx, bool in_isr) {
-  (void) ctx;
   if (in_isr) {
+    if (!TUP_MCU_MULTIPLE_CORE) {
+      (void) ctx;
+      return; // single core MCU does not need to lock in ISR
+    }
     taskEXIT_CRITICAL_FROM_ISR(*ctx);
   } else {
     taskEXIT_CRITICAL();

src/osal/osal_mynewt.h

@@ -53,12 +53,16 @@ TU_ATTR_ALWAYS_INLINE static inline void osal_spin_init(osal_spinlock_t *ctx) {
 }
 
 TU_ATTR_ALWAYS_INLINE static inline void osal_spin_lock(osal_spinlock_t *ctx, bool in_isr) {
-  (void) in_isr;
+  if (!TUP_MCU_MULTIPLE_CORE && in_isr) {
+    return; // single core MCU does not need to lock in ISR
+  }
   OS_ENTER_CRITICAL(*ctx);
 }
 
 TU_ATTR_ALWAYS_INLINE static inline void osal_spin_unlock(osal_spinlock_t *ctx, bool in_isr) {
-  (void) in_isr;
+  if (!TUP_MCU_MULTIPLE_CORE && in_isr) {
+    return; // single core MCU does not need to lock in ISR
+  }
   OS_ENTER_CRITICAL(*ctx);
 }
 

src/osal/osal_none.h

@@ -47,7 +47,7 @@ typedef struct {
   void (* interrupt_set)(bool);
 } osal_spinlock_t;
 
-// For SMP, spinlock must be locked by hardware, not use interrupt
+// For SMP, spinlock must be locked by hardware, cannot just use interrupt
 #define OSAL_SPINLOCK_DEF(_name, _int_set) \
   osal_spinlock_t _name = { .interrupt_set = _int_set }
 

src/osal/osal_rtthread.h

@@ -55,12 +55,16 @@ TU_ATTR_ALWAYS_INLINE static inline void osal_spin_init(osal_spinlock_t *ctx) {
 }
 
 TU_ATTR_ALWAYS_INLINE static inline void osal_spin_lock(osal_spinlock_t *ctx, bool in_isr) {
-  (void) in_isr;
+  if (!TUP_MCU_MULTIPLE_CORE && in_isr) {
+    return; // single core MCU does not need to lock in ISR
+  }
   rt_spin_lock(ctx);
 }
 
 TU_ATTR_ALWAYS_INLINE static inline void osal_spin_unlock(osal_spinlock_t *ctx, bool in_isr) {
-  (void) in_isr;
+  if (!TUP_MCU_MULTIPLE_CORE && in_isr) {
+    return; // single core MCU does not need to lock in ISR
+  }
   rt_spin_unlock(ctx);
 }
 

src/osal/osal_zephyr.h

@@ -51,12 +51,16 @@ TU_ATTR_ALWAYS_INLINE static inline void osal_spin_init(osal_spinlock_t *ctx) {
 }
 
 TU_ATTR_ALWAYS_INLINE static inline void osal_spin_lock(osal_spinlock_t *ctx, bool in_isr) {
-  (void) in_isr;
+  if (!TUP_MCU_MULTIPLE_CORE && in_isr) {
+    return; // single core MCU does not need to lock in ISR
+  }
   ctx->key = k_spin_lock(&ctx->lock);
 }
 
 TU_ATTR_ALWAYS_INLINE static inline void osal_spin_unlock(osal_spinlock_t *ctx, bool in_isr) {
-  (void) in_isr;
+  if (!TUP_MCU_MULTIPLE_CORE && in_isr) {
+    return; // single core MCU does not need to lock in ISR
+  }
   k_spin_unlock(&ctx->lock, ctx->key);
 }
 

src/portable/synopsys/dwc2/dcd_dwc2.c

@@ -1020,16 +1020,11 @@ void dcd_int_handler(uint8_t rhport) {
 
   if (gintsts & GINTSTS_USBRST) {
     // USBRST is start of reset.
-    #if TUP_MCU_MULTIPLE_CORE
-    osal_spin_lock(&_dcd_spinlock, true);
-    #endif
-
     dwc2->gintsts = GINTSTS_USBRST;
-    handle_bus_reset(rhport);
 
-    #if TUP_MCU_MULTIPLE_CORE
+    osal_spin_lock(&_dcd_spinlock, true);
+    handle_bus_reset(rhport);
     osal_spin_unlock(&_dcd_spinlock, true);
-    #endif
   }
 
   if (gintsts & GINTSTS_ENUMDNE) {

src/portable/synopsys/dwc2/dwc2_esp32.h

@@ -55,8 +55,8 @@ static const dwc2_controller_t _dwc2_controller[] = {
 // On ESP32 for consistency we associate
 // - Port0 to OTG_FS, and Port1 to OTG_HS
 static const dwc2_controller_t _dwc2_controller[] = {
-{ .reg_base = DWC2_FS_REG_BASE, .irqnum = ETS_USB_OTG11_CH0_INTR_SOURCE, .ep_count = 7, .ep_in_count = 5, .ep_fifo_size = 1024 },
+  { .reg_base = DWC2_FS_REG_BASE, .irqnum = ETS_USB_OTG11_CH0_INTR_SOURCE, .ep_count = 7, .ep_in_count = 5, .ep_fifo_size = 1024 },
-{ .reg_base = DWC2_HS_REG_BASE, .irqnum = ETS_USB_OTG_INTR_SOURCE, .ep_count = 16, .ep_in_count = 8, .ep_fifo_size = 4096 }
+  { .reg_base = DWC2_HS_REG_BASE, .irqnum = ETS_USB_OTG_INTR_SOURCE, .ep_count = 16, .ep_in_count = 8, .ep_fifo_size = 4096 }
 };
 #endif