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@@ -2,6 +2,7 @@
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* The MIT License (MIT)
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*
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* Copyright (c) 2019 Ha Thach (tinyusb.org)
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* Copyright (c) 2023 Heiko Kuester (CH34x support)
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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@@ -69,7 +70,16 @@ typedef struct {
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uint8_t rx_ff_buf[CFG_TUH_CDC_TX_BUFSIZE];
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CFG_TUH_MEM_ALIGN uint8_t rx_ep_buf[CFG_TUH_CDC_TX_EPSIZE];
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} stream;
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#if CFG_TUH_CDC_CH34X
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struct {
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uint32_t baud_rate;
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uint8_t mcr;
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uint8_t msr;
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uint8_t lcr;
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uint32_t quirks;
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uint8_t version;
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} ch34x;
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#endif
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} cdch_interface_t;
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CFG_TUH_MEM_SECTION
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@@ -121,6 +131,23 @@ static bool cp210x_set_modem_ctrl(cdch_interface_t* p_cdc, uint16_t line_state,
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static bool cp210x_set_baudrate(cdch_interface_t* p_cdc, uint32_t baudrate, tuh_xfer_cb_t complete_cb, uintptr_t user_data);
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#endif
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//------------- CH34x prototypes -------------//
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#if CFG_TUH_CDC_CH34X
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#include "serial/ch34x.h"
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static uint16_t const ch34x_vids_pids[][2] = { CFG_TUH_CDC_CH34X_VID_PID_LIST };
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enum {
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CH34X_VID_PID_COUNT = sizeof ( ch34x_vids_pids ) / sizeof ( ch34x_vids_pids[0] )
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};
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static bool ch34x_open ( uint8_t daddr, tusb_desc_interface_t const *itf_desc, uint16_t max_len );
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static void ch34x_process_config ( tuh_xfer_t* xfer );
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static bool ch34x_set_modem_ctrl ( cdch_interface_t* p_cdc, uint16_t line_state, tuh_xfer_cb_t complete_cb, uintptr_t user_data );
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static bool ch34x_set_baudrate ( cdch_interface_t* p_cdc, uint32_t baudrate, tuh_xfer_cb_t complete_cb, uintptr_t user_data );
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#endif
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enum {
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SERIAL_DRIVER_ACM = 0,
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@@ -131,6 +158,10 @@ enum {
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#if CFG_TUH_CDC_CP210X
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SERIAL_DRIVER_CP210X,
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#endif
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#if CFG_TUH_CDC_CH34X
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SERIAL_DRIVER_CH34X,
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#endif
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};
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typedef struct {
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@@ -159,6 +190,13 @@ static const cdch_serial_driver_t serial_drivers[] = {
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.set_baudrate = cp210x_set_baudrate
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},
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#endif
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#if CFG_TUH_CDC_CH34X
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{ .process_set_config = ch34x_process_config,
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.set_control_line_state = ch34x_set_modem_ctrl,
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.set_baudrate = ch34x_set_baudrate
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},
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#endif
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};
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enum {
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@@ -426,6 +464,12 @@ static void cdch_internal_control_complete(tuh_xfer_t* xfer)
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break;
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#endif
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#if CFG_TUH_CDC_CH34X
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case SERIAL_DRIVER_CH34X:
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TU_ASSERT(false, ); // see special ch34x_control_complete function
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break;
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#endif
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default: break;
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}
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}
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@@ -641,7 +685,7 @@ bool cdch_open(uint8_t rhport, uint8_t daddr, tusb_desc_interface_t const *itf_d
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{
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return acm_open(daddr, itf_desc, max_len);
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}
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#if CFG_TUH_CDC_FTDI || CFG_TUH_CDC_CP210X
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#if CFG_TUH_CDC_FTDI || CFG_TUH_CDC_CP210X || CFG_TUH_CDC_CH34X
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else if ( 0xff == itf_desc->bInterfaceClass )
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{
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uint16_t vid, pid;
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@@ -666,8 +710,16 @@ bool cdch_open(uint8_t rhport, uint8_t daddr, tusb_desc_interface_t const *itf_d
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}
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}
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#endif
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#if CFG_TUH_CDC_CH34X
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for (size_t i = 0; i < CH34X_VID_PID_COUNT; i++) {
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if ( ch34x_vids_pids[i][0] == vid && ch34x_vids_pids[i][1] == pid ) {
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return ch34x_open(daddr, itf_desc, max_len);
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}
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}
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#endif
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}
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#endif
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#endif // CFG_TUH_CDC_FTDI || CFG_TUH_CDC_CP210X || CFG_TUH_CDC_CH34X
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return false;
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}
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@@ -1176,4 +1228,412 @@ static void cp210x_process_config(tuh_xfer_t* xfer) {
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#endif
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//--------------------------------------------------------------------+
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// CH34x
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//--------------------------------------------------------------------+
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#if CFG_TUH_CDC_CH34X
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enum {
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CONFIG_CH34X_STEP1 = 0,
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CONFIG_CH34X_STEP2,
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CONFIG_CH34X_STEP3,
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CONFIG_CH34X_STEP4,
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CONFIG_CH34X_STEP5,
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CONFIG_CH34X_STEP6,
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CONFIG_CH34X_STEP7,
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CONFIG_CH34X_STEP8,
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CONFIG_CH34X_COMPLETE
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};
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static bool ch34x_open ( uint8_t daddr, tusb_desc_interface_t const *itf_desc, uint16_t max_len )
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{
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// CH34x Interface includes 1 vendor interface + 3 bulk endpoints
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TU_VERIFY ( itf_desc->bNumEndpoints == 3 );
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TU_VERIFY ( sizeof ( tusb_desc_interface_t ) + 2 * sizeof ( tusb_desc_endpoint_t ) <= max_len );
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cdch_interface_t *p_cdc = make_new_itf ( daddr, itf_desc );
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TU_VERIFY ( p_cdc );
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TU_LOG_DRV ( "CH34x opened\r\n" );
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p_cdc->serial_drid = SERIAL_DRIVER_CH34X;
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// endpoint pair
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tusb_desc_endpoint_t const * desc_ep = (tusb_desc_endpoint_t const *) tu_desc_next ( itf_desc );
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// data endpoints expected to be in pairs
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return open_ep_stream_pair ( p_cdc, desc_ep );
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}
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static bool ch34x_set_request ( cdch_interface_t* p_cdc, uint8_t direction, uint8_t request, uint16_t value, uint16_t index, uint8_t* buffer, uint16_t length, tuh_xfer_cb_t complete_cb, uintptr_t user_data )
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{
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tusb_control_request_t const request_setup = {
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.bmRequestType_bit = {
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.recipient = TUSB_REQ_RCPT_DEVICE,
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.type = TUSB_REQ_TYPE_VENDOR,
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.direction = direction
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},
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.bRequest = request,
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.wValue = tu_htole16 ( value ),
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.wIndex = tu_htole16 ( index ),
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.wLength = tu_htole16 ( length )
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};
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// use usbh enum buf since application variable does not live long enough
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uint8_t* enum_buf = NULL;
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if ( buffer && length > 0 ) {
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enum_buf = usbh_get_enum_buf();
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tu_memcpy_s ( enum_buf, CFG_TUH_ENUMERATION_BUFSIZE, buffer, length );
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}
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tuh_xfer_t xfer = {
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.daddr = p_cdc->daddr,
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.ep_addr = 0,
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.setup = &request_setup,
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.buffer = enum_buf,
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.complete_cb = complete_cb,
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// CH34x needs a special handling of bInterfaceNumber, because wIndex is used for other purposes and not for bInterfaceNumber
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.user_data = (uintptr_t)( ( p_cdc->bInterfaceNumber & 0xff ) << 8 ) | ( user_data & 0xff )
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};
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return tuh_control_xfer ( &xfer );
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return false;
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}
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static bool ch341_control_out ( cdch_interface_t* p_cdc, uint8_t request, uint16_t value, uint16_t index, tuh_xfer_cb_t complete_cb, uintptr_t user_data )
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{
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return ch34x_set_request ( p_cdc, TUSB_DIR_OUT, request, value, index, /* buffer */ NULL, /* length */ 0, complete_cb, user_data );
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}
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static bool ch341_control_in ( cdch_interface_t* p_cdc, uint8_t request, uint16_t value, uint16_t index, uint8_t *buffer, uint16_t buffersize, tuh_xfer_cb_t complete_cb, uintptr_t user_data )
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{
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return ch34x_set_request ( p_cdc, TUSB_DIR_IN, request, value, index, buffer, buffersize, complete_cb, user_data );
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}
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static int32_t ch341_write_reg ( cdch_interface_t* p_cdc, uint16_t reg, uint16_t value, tuh_xfer_cb_t complete_cb, uintptr_t user_data )
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{
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return ch341_control_out ( p_cdc, CH341_REQ_WRITE_REG, /* value */ reg, /* index */ value, complete_cb, user_data );
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}
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static int32_t ch341_read_reg_request ( cdch_interface_t* p_cdc, uint16_t reg, uint8_t *buffer, uint16_t buffersize, tuh_xfer_cb_t complete_cb, uintptr_t user_data )
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{
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return ch341_control_in ( p_cdc, CH341_REQ_READ_REG, reg, /* index */ 0, buffer, buffersize, complete_cb, user_data );
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}
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/*
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* The device line speed is given by the following equation:
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*
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* baudrate = 48000000 / (2^(12 - 3 * ps - fact) * div), where
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*
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* 0 <= ps <= 3,
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* 0 <= fact <= 1,
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* 2 <= div <= 256 if fact = 0, or
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* 9 <= div <= 256 if fact = 1
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*/
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// calculate baudrate devisors
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// Parts of this functions have been taken over from Linux driver /drivers/usb/serial/ch341.c
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static int32_t ch341_get_divisor ( cdch_interface_t* p_cdc, uint32_t speed )
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{
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uint32_t fact, div, clk_div;
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bool force_fact0 = false;
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int32_t ps;
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static const uint32_t ch341_min_rates[] = {
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CH341_MIN_RATE(0),
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CH341_MIN_RATE(1),
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CH341_MIN_RATE(2),
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CH341_MIN_RATE(3),
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};
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/*
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* Clamp to supported range, this makes the (ps < 0) and (div < 2)
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* sanity checks below redundant.
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*/
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inline uint32_t max ( uint32_t val, uint32_t maxval ) { return val > maxval ? val : maxval; }
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inline uint32_t min ( uint32_t val, uint32_t minval ) { return val < minval ? val : minval; }
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inline uint32_t clamp_val ( uint32_t val, uint32_t minval, uint32_t maxval ) { return min ( max ( val, minval ), maxval ); }
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speed = clamp_val(speed, CH341_MIN_BPS, CH341_MAX_BPS);
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/*
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* Start with highest possible base clock (fact = 1) that will give a
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* divisor strictly less than 512.
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*/
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fact = 1;
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for (ps = 3; ps >= 0; ps--) {
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if (speed > ch341_min_rates[ps])
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break;
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}
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if (ps < 0)
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return -EINVAL;
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/* Determine corresponding divisor, rounding down. */
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clk_div = CH341_CLK_DIV(ps, fact);
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div = CH341_CLKRATE / (clk_div * speed);
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/* Some devices require a lower base clock if ps < 3. */
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if (ps < 3 && (p_cdc->ch34x.quirks & CH341_QUIRK_LIMITED_PRESCALER))
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force_fact0 = true;
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/* Halve base clock (fact = 0) if required. */
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if (div < 9 || div > 255 || force_fact0) {
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div /= 2;
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clk_div *= 2;
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fact = 0;
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}
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if (div < 2)
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return -EINVAL;
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/*
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* Pick next divisor if resulting rate is closer to the requested one,
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* scale up to avoid rounding errors on low rates.
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*/
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if (16 * CH341_CLKRATE / (clk_div * div) - 16 * speed >=
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16 * speed - 16 * CH341_CLKRATE / (clk_div * (div + 1)))
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div++;
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/*
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* Prefer lower base clock (fact = 0) if even divisor.
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*
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* Note that this makes the receiver more tolerant to errors.
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*/
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if (fact == 1 && div % 2 == 0) {
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div /= 2;
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fact = 0;
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}
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return (0x100 - div) << 8 | fact << 2 | ps;
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}
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// set baudrate (low level)
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// do not confuse with ch34x_set_baudrate
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|
// Parts of this functions have been taken over from Linux driver /drivers/usb/serial/ch341.c
|
|
|
|
|
static int32_t ch341_set_baudrate ( cdch_interface_t* p_cdc, uint32_t baud_rate, tuh_xfer_cb_t complete_cb, uintptr_t user_data )
|
|
|
|
|
{
|
|
|
|
|
int val;
|
|
|
|
|
|
|
|
|
|
if (!baud_rate)
|
|
|
|
|
return -EINVAL;
|
|
|
|
|
|
|
|
|
|
val = ch341_get_divisor(p_cdc, baud_rate);
|
|
|
|
|
if (val < 0)
|
|
|
|
|
return -EINVAL;
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* CH341A buffers data until a full endpoint-size packet (32 bytes)
|
|
|
|
|
* has been received unless bit 7 is set.
|
|
|
|
|
*
|
|
|
|
|
* At least one device with version 0x27 appears to have this bit
|
|
|
|
|
* inverted.
|
|
|
|
|
*/
|
|
|
|
|
if ( p_cdc->ch34x.version > 0x27 )
|
|
|
|
|
val |= BIT(7);
|
|
|
|
|
|
|
|
|
|
return ch341_write_reg ( p_cdc, CH341_REG_DIVISOR << 8 | CH341_REG_PRESCALER, val, complete_cb, user_data );
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
// set lcr register
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|
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|
|
// Parts of this functions have been taken over from Linux driver /drivers/usb/serial/ch341.c
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|
|
static int32_t ch341_set_lcr ( cdch_interface_t* p_cdc, uint8_t lcr, tuh_xfer_cb_t complete_cb, uintptr_t user_data )
|
|
|
|
|
{
|
|
|
|
|
/*
|
|
|
|
|
* Chip versions before version 0x30 as read using
|
|
|
|
|
* CH341_REQ_READ_VERSION used separate registers for line control
|
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|
|
* (stop bits, parity and word length). Version 0x30 and above use
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|
|
|
* CH341_REG_LCR only and CH341_REG_LCR2 is always set to zero.
|
|
|
|
|
*/
|
|
|
|
|
if ( p_cdc->ch34x.version < 0x30 )
|
|
|
|
|
return 0;
|
|
|
|
|
|
|
|
|
|
return ch341_write_reg ( p_cdc, CH341_REG_LCR2 << 8 | CH341_REG_LCR, lcr, complete_cb, user_data );
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
// set handshake (modem controls)
|
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|
|
|
// Parts of this functions have been taken over from Linux driver /drivers/usb/serial/ch341.c
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|
|
|
|
static int32_t ch341_set_handshake ( cdch_interface_t* p_cdc, uint8_t control, tuh_xfer_cb_t complete_cb, uintptr_t user_data )
|
|
|
|
|
{
|
|
|
|
|
return ch341_control_out ( p_cdc, CH341_REQ_MODEM_CTRL, /* value */ ~control, /* index */ 0, complete_cb, user_data );
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
// detect quirks (special versions of CH34x)
|
|
|
|
|
// Parts of this functions have been taken over from Linux driver /drivers/usb/serial/ch341.c
|
|
|
|
|
static int32_t ch341_detect_quirks ( tuh_xfer_t* xfer, cdch_interface_t* p_cdc, uint8_t step, uint8_t *buffer, uint16_t buffersize, tuh_xfer_cb_t complete_cb, uintptr_t user_data )
|
|
|
|
|
{
|
|
|
|
|
/*
|
|
|
|
|
* A subset of CH34x devices does not support all features. The
|
|
|
|
|
* prescaler is limited and there is no support for sending a RS232
|
|
|
|
|
* break condition. A read failure when trying to set up the latter is
|
|
|
|
|
* used to detect these devices.
|
|
|
|
|
*/
|
|
|
|
|
switch ( step )
|
|
|
|
|
{
|
|
|
|
|
case 1:
|
|
|
|
|
p_cdc->ch34x.quirks = 0;
|
|
|
|
|
return ch341_read_reg_request ( p_cdc, CH341_REG_BREAK, buffer, buffersize, complete_cb, user_data );
|
|
|
|
|
break;
|
|
|
|
|
case 2:
|
|
|
|
|
if ( xfer->result != XFER_RESULT_SUCCESS )
|
|
|
|
|
p_cdc->ch34x.quirks |= CH341_QUIRK_LIMITED_PRESCALER | CH341_QUIRK_SIMULATE_BREAK;
|
|
|
|
|
return true;
|
|
|
|
|
break;
|
|
|
|
|
default:
|
|
|
|
|
TU_ASSERT ( false ); // suspicious step
|
|
|
|
|
break;
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
// internal control complete to update state such as line state, encoding
|
|
|
|
|
// CH34x needs a special interface recovery due to abnormal wIndex usage
|
|
|
|
|
static void ch34x_control_complete(tuh_xfer_t* xfer)
|
|
|
|
|
{
|
|
|
|
|
uint8_t const itf_num = (uint8_t)( ( xfer->user_data & 0xff00 ) >> 8 );
|
|
|
|
|
uint8_t const idx = tuh_cdc_itf_get_index ( xfer->daddr, itf_num );
|
|
|
|
|
cdch_interface_t *p_cdc = get_itf ( idx );
|
|
|
|
|
TU_ASSERT ( p_cdc, );
|
|
|
|
|
TU_ASSERT ( p_cdc->serial_drid == SERIAL_DRIVER_CH34X, ); // ch34x_control_complete is only used for CH34x
|
|
|
|
|
|
|
|
|
|
if (xfer->result == XFER_RESULT_SUCCESS) {
|
|
|
|
|
switch (xfer->setup->bRequest) {
|
|
|
|
|
case CH341_REQ_WRITE_REG: { // register write request
|
|
|
|
|
switch ( tu_le16toh ( xfer->setup->wValue ) ) {
|
|
|
|
|
case ( CH341_REG_DIVISOR << 8 | CH341_REG_PRESCALER ): { // baudrate write
|
|
|
|
|
p_cdc->line_coding.bit_rate = p_cdc->ch34x.baud_rate;
|
|
|
|
|
break;
|
|
|
|
|
}
|
|
|
|
|
default: {
|
|
|
|
|
TU_ASSERT(false, ); // unexpected register write
|
|
|
|
|
break;
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
break;
|
|
|
|
|
}
|
|
|
|
|
default: {
|
|
|
|
|
TU_ASSERT(false, ); // unexpected request
|
|
|
|
|
break;
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
xfer->complete_cb = p_cdc->user_control_cb;
|
|
|
|
|
if (xfer->complete_cb)
|
|
|
|
|
xfer->complete_cb(xfer);
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static bool ch34x_set_baudrate ( cdch_interface_t* p_cdc, uint32_t baudrate, tuh_xfer_cb_t complete_cb, uintptr_t user_data ) // do not confuse with ch341_set_baudrate
|
|
|
|
|
{
|
|
|
|
|
TU_LOG_DRV("CDC CH34x Set BaudRate = %lu\r\n", baudrate);
|
|
|
|
|
uint32_t baud_le = tu_htole32(baudrate);
|
|
|
|
|
p_cdc->ch34x.baud_rate = baudrate;
|
|
|
|
|
p_cdc->user_control_cb = complete_cb;
|
|
|
|
|
return ch341_set_baudrate ( p_cdc, baud_le, complete_cb ? ch34x_control_complete : NULL, user_data );
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static bool ch34x_set_modem_ctrl ( cdch_interface_t* p_cdc, uint16_t line_state, tuh_xfer_cb_t complete_cb, uintptr_t user_data )
|
|
|
|
|
{
|
|
|
|
|
TU_LOG_DRV("CDC CH34x Set Control Line State\r\n");
|
|
|
|
|
// todo later
|
|
|
|
|
return false;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static void ch34x_process_config ( tuh_xfer_t* xfer )
|
|
|
|
|
{
|
|
|
|
|
uintptr_t const state = xfer->user_data & 0xff;
|
|
|
|
|
// CH34x needs a special handling of bInterfaceNumber, because wIndex is used for other purposes and not for bInterfaceNumber
|
|
|
|
|
uint8_t const itf_num = (uint8_t)( ( xfer->user_data & 0xff00 ) >> 8 );
|
|
|
|
|
uint8_t const idx = tuh_cdc_itf_get_index ( xfer->daddr, itf_num );
|
|
|
|
|
cdch_interface_t *p_cdc = get_itf ( idx );
|
|
|
|
|
uint8_t buffer [ CH34X_BUFFER_SIZE ];
|
|
|
|
|
cdc_line_coding_t line_coding = CFG_TUH_CDC_LINE_CODING_ON_ENUM;
|
|
|
|
|
TU_ASSERT ( p_cdc, );
|
|
|
|
|
|
|
|
|
|
if ( state == 0 ) {
|
|
|
|
|
// defaults
|
|
|
|
|
p_cdc->ch34x.baud_rate = DEFAULT_BAUD_RATE;
|
|
|
|
|
p_cdc->ch34x.mcr = 0;
|
|
|
|
|
p_cdc->ch34x.msr = 0;
|
|
|
|
|
p_cdc->ch34x.quirks = 0;
|
|
|
|
|
p_cdc->ch34x.version = 0;
|
|
|
|
|
/*
|
|
|
|
|
* Some CH340 devices appear unable to change the initial LCR
|
|
|
|
|
* settings, so set a sane 8N1 default.
|
|
|
|
|
*/
|
|
|
|
|
p_cdc->ch34x.lcr = CH341_LCR_ENABLE_RX | CH341_LCR_ENABLE_TX | CH341_LCR_CS8;
|
|
|
|
|
}
|
|
|
|
|
// This process flow has been taken over from Linux driver /drivers/usb/serial/ch341.c
|
|
|
|
|
switch ( state ) {
|
|
|
|
|
case CONFIG_CH34X_STEP1: // request version read
|
|
|
|
|
TU_ASSERT ( ch341_control_in ( p_cdc, /* request */ CH341_REQ_READ_VERSION, /* value */ 0, /* index */ 0, buffer, CH34X_BUFFER_SIZE, ch34x_process_config, CONFIG_CH34X_STEP2 ), );
|
|
|
|
|
break;
|
|
|
|
|
case CONFIG_CH34X_STEP2: // handle version read data, request to init CH34x
|
|
|
|
|
p_cdc->ch34x.version = xfer->buffer[0];
|
|
|
|
|
TU_LOG_DRV ( "Chip version=%02x\r\n", p_cdc->ch34x.version );
|
|
|
|
|
TU_ASSERT ( ch341_control_out ( p_cdc, /* request */ CH341_REQ_SERIAL_INIT, /* value */ 0, /* index */ 0, ch34x_process_config, CONFIG_CH34X_STEP3 ), );
|
|
|
|
|
break;
|
|
|
|
|
case CONFIG_CH34X_STEP3: // set baudrate with default values (see above)
|
|
|
|
|
TU_ASSERT ( ch341_set_baudrate ( p_cdc, p_cdc->ch34x.baud_rate, ch34x_process_config, CONFIG_CH34X_STEP4 ) > 0, );
|
|
|
|
|
break;
|
|
|
|
|
case CONFIG_CH34X_STEP4: // set line controls with default values (see above)
|
|
|
|
|
TU_ASSERT ( ch341_set_lcr ( p_cdc, p_cdc->ch34x.lcr, ch34x_process_config, CONFIG_CH34X_STEP5 ) > 0, );
|
|
|
|
|
break;
|
|
|
|
|
case CONFIG_CH34X_STEP5: // set handshake RTS/DTR
|
|
|
|
|
TU_ASSERT ( ch341_set_handshake ( p_cdc, p_cdc->ch34x.mcr, ch34x_process_config, CONFIG_CH34X_STEP6 ) > 0, );
|
|
|
|
|
break;
|
|
|
|
|
case CONFIG_CH34X_STEP6: // detect quirks step 1
|
|
|
|
|
TU_ASSERT ( ch341_detect_quirks ( xfer, p_cdc, /* step */ 1, buffer, CH34X_BUFFER_SIZE, ch34x_process_config, CONFIG_CH34X_STEP7 ) > 0, );
|
|
|
|
|
break;
|
|
|
|
|
case CONFIG_CH34X_STEP7: // detect quirks step 2 and set baudrate with configured values
|
|
|
|
|
TU_ASSERT ( ch341_detect_quirks ( xfer, p_cdc, /* step */ 2, NULL, 0, NULL, 0 ) > 0, );
|
|
|
|
|
#ifdef CFG_TUH_CDC_LINE_CODING_ON_ENUM
|
|
|
|
|
TU_ASSERT ( ch34x_set_baudrate ( p_cdc, line_coding.bit_rate, ch34x_process_config, CONFIG_CH34X_STEP8 ), );
|
|
|
|
|
#else
|
|
|
|
|
TU_ATTR_FALLTHROUGH;
|
|
|
|
|
#endif
|
|
|
|
|
break;
|
|
|
|
|
case CONFIG_CH34X_STEP8: // set data/stop bit quantities, parity
|
|
|
|
|
#ifdef CFG_TUH_CDC_LINE_CODING_ON_ENUM
|
|
|
|
|
p_cdc->ch34x.lcr = CH341_LCR_ENABLE_RX | CH341_LCR_ENABLE_TX;
|
|
|
|
|
switch ( line_coding.data_bits ) {
|
|
|
|
|
case 5:
|
|
|
|
|
p_cdc->ch34x.lcr |= CH341_LCR_CS5;
|
|
|
|
|
break;
|
|
|
|
|
case 6:
|
|
|
|
|
p_cdc->ch34x.lcr |= CH341_LCR_CS6;
|
|
|
|
|
break;
|
|
|
|
|
case 7:
|
|
|
|
|
p_cdc->ch34x.lcr |= CH341_LCR_CS7;
|
|
|
|
|
break;
|
|
|
|
|
case 8:
|
|
|
|
|
p_cdc->ch34x.lcr |= CH341_LCR_CS8;
|
|
|
|
|
break;
|
|
|
|
|
default:
|
|
|
|
|
TU_ASSERT ( false, ); // not supported data_bits
|
|
|
|
|
p_cdc->ch34x.lcr |= CH341_LCR_CS8;
|
|
|
|
|
break;
|
|
|
|
|
}
|
|
|
|
|
if ( line_coding.parity != CDC_LINE_CODING_PARITY_NONE ) {
|
|
|
|
|
p_cdc->ch34x.lcr |= CH341_LCR_ENABLE_PAR;
|
|
|
|
|
if ( line_coding.parity == CDC_LINE_CODING_PARITY_EVEN || line_coding.parity == CDC_LINE_CODING_PARITY_SPACE )
|
|
|
|
|
p_cdc->ch34x.lcr |= CH341_LCR_PAR_EVEN;
|
|
|
|
|
if ( line_coding.parity == CDC_LINE_CODING_PARITY_MARK || line_coding.parity == CDC_LINE_CODING_PARITY_SPACE )
|
|
|
|
|
p_cdc->ch34x.lcr |= CH341_LCR_MARK_SPACE;
|
|
|
|
|
}
|
|
|
|
|
TU_ASSERT ( line_coding.stop_bits == CDC_LINE_CODING_STOP_BITS_1 || line_coding.stop_bits == CDC_LINE_CODING_STOP_BITS_2, ); // not supported 1.5 stop bits
|
|
|
|
|
if ( line_coding.stop_bits == CDC_LINE_CODING_STOP_BITS_2 )
|
|
|
|
|
p_cdc->ch34x.lcr |= CH341_LCR_STOP_BITS_2;
|
|
|
|
|
TU_ASSERT ( ch341_set_lcr ( p_cdc, p_cdc->ch34x.lcr, ch34x_process_config, CONFIG_CH34X_COMPLETE ) > 0, );
|
|
|
|
|
#else
|
|
|
|
|
TU_ATTR_FALLTHROUGH;
|
|
|
|
|
#endif
|
|
|
|
|
break;
|
|
|
|
|
case CONFIG_CH34X_COMPLETE:
|
|
|
|
|
set_config_complete ( p_cdc, idx, itf_num );
|
|
|
|
|
break;
|
|
|
|
|
default:
|
|
|
|
|
TU_ASSERT ( false, );
|
|
|
|
|
break;
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
#endif // CFG_TUH_CDC_CH34X
|
|
|
|
|
|
|
|
|
|
#endif // (CFG_TUH_ENABLED && CFG_TUH_CDC)
|
|
|
|
|