fix build with nrfx v3, though max3421e spi does not seem to work well.
This commit is contained in:
@@ -72,7 +72,7 @@ void tuh_cdc_rx_cb(uint8_t idx) {
|
|||||||
uint32_t count = tuh_cdc_read(idx, buf, bufsize);
|
uint32_t count = tuh_cdc_read(idx, buf, bufsize);
|
||||||
buf[count] = 0;
|
buf[count] = 0;
|
||||||
|
|
||||||
printf((char*) buf);
|
printf("%s", (char*) buf);
|
||||||
}
|
}
|
||||||
|
|
||||||
// Invoked when a device with CDC interface is mounted
|
// Invoked when a device with CDC interface is mounted
|
||||||
@@ -89,7 +89,7 @@ void tuh_cdc_mount_cb(uint8_t idx) {
|
|||||||
// while eneumerating new cdc device
|
// while eneumerating new cdc device
|
||||||
cdc_line_coding_t line_coding = {0};
|
cdc_line_coding_t line_coding = {0};
|
||||||
if (tuh_cdc_get_local_line_coding(idx, &line_coding)) {
|
if (tuh_cdc_get_local_line_coding(idx, &line_coding)) {
|
||||||
printf(" Baudrate: %lu, Stop Bits : %u\r\n", line_coding.bit_rate, line_coding.stop_bits);
|
printf(" Baudrate: %" PRIu32 ", Stop Bits : %u\r\n", line_coding.bit_rate, line_coding.stop_bits);
|
||||||
printf(" Parity : %u, Data Width: %u\r\n", line_coding.parity, line_coding.data_bits);
|
printf(" Parity : %u, Data Width: %u\r\n", line_coding.parity, line_coding.data_bits);
|
||||||
}
|
}
|
||||||
#else
|
#else
|
||||||
|
@@ -107,6 +107,11 @@ TU_ATTR_UNUSED static void power_event_handler(nrfx_power_usb_evt_t event) {
|
|||||||
#if CFG_TUH_ENABLED && defined(CFG_TUH_MAX3421) && CFG_TUH_MAX3421
|
#if CFG_TUH_ENABLED && defined(CFG_TUH_MAX3421) && CFG_TUH_MAX3421
|
||||||
static void max3421_init(void);
|
static void max3421_init(void);
|
||||||
static nrfx_spim_t _spi = NRFX_SPIM_INSTANCE(1);
|
static nrfx_spim_t _spi = NRFX_SPIM_INSTANCE(1);
|
||||||
|
|
||||||
|
#if NRFX_VER > 2
|
||||||
|
static nrfx_gpiote_t _gpiote = NRFX_GPIOTE_INSTANCE(0);
|
||||||
|
#endif
|
||||||
|
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
//--------------------------------------------------------------------+
|
//--------------------------------------------------------------------+
|
||||||
@@ -141,7 +146,7 @@ void board_init(void) {
|
|||||||
SysTick_Config(SystemCoreClock / 1000);
|
SysTick_Config(SystemCoreClock / 1000);
|
||||||
|
|
||||||
// UART
|
// UART
|
||||||
#if NRFX_VER == 2
|
#if NRFX_VER <= 2
|
||||||
nrfx_uarte_config_t uart_cfg = {
|
nrfx_uarte_config_t uart_cfg = {
|
||||||
.pseltxd = UART_TX_PIN,
|
.pseltxd = UART_TX_PIN,
|
||||||
.pselrxd = UART_RX_PIN,
|
.pselrxd = UART_RX_PIN,
|
||||||
@@ -155,7 +160,7 @@ void board_init(void) {
|
|||||||
.parity = NRF_UARTE_PARITY_EXCLUDED,
|
.parity = NRF_UARTE_PARITY_EXCLUDED,
|
||||||
}
|
}
|
||||||
};
|
};
|
||||||
#elif NRFX_VER == 3
|
#else
|
||||||
nrfx_uarte_config_t uart_cfg = {
|
nrfx_uarte_config_t uart_cfg = {
|
||||||
.txd_pin = UART_TX_PIN,
|
.txd_pin = UART_TX_PIN,
|
||||||
.rxd_pin = UART_RX_PIN,
|
.rxd_pin = UART_RX_PIN,
|
||||||
@@ -263,7 +268,7 @@ int board_uart_read(uint8_t* buf, int len) {
|
|||||||
|
|
||||||
int board_uart_write(void const* buf, int len) {
|
int board_uart_write(void const* buf, int len) {
|
||||||
nrfx_err_t err = nrfx_uarte_tx(&_uart_id, (uint8_t const*) buf, (size_t) len
|
nrfx_err_t err = nrfx_uarte_tx(&_uart_id, (uint8_t const*) buf, (size_t) len
|
||||||
#if NRFX_VER == 3
|
#if NRFX_VER > 2
|
||||||
,0
|
,0
|
||||||
#endif
|
#endif
|
||||||
);
|
);
|
||||||
@@ -324,8 +329,16 @@ void nrf_error_cb(uint32_t id, uint32_t pc, uint32_t info) {
|
|||||||
//--------------------------------------------------------------------+
|
//--------------------------------------------------------------------+
|
||||||
#if CFG_TUH_ENABLED && defined(CFG_TUH_MAX3421) && CFG_TUH_MAX3421
|
#if CFG_TUH_ENABLED && defined(CFG_TUH_MAX3421) && CFG_TUH_MAX3421
|
||||||
|
|
||||||
void max3421_int_handler(nrfx_gpiote_pin_t pin, nrf_gpiote_polarity_t action) {
|
#if NRFX_VER <= 2
|
||||||
if (!(pin == MAX3421_INTR_PIN && action == NRF_GPIOTE_POLARITY_HITOLO)) return;
|
void max3421_int_handler(nrfx_gpiote_pin_t pin, nrf_gpiote_polarity_t action ) {
|
||||||
|
if (action != NRF_GPIOTE_POLARITY_HITOLO) return;
|
||||||
|
#else
|
||||||
|
void max3421_int_handler(nrfx_gpiote_pin_t pin, nrfx_gpiote_trigger_t action, void* p_context) {
|
||||||
|
(void) p_context;
|
||||||
|
if (action != NRFX_GPIOTE_TRIGGER_HITOLO) return;
|
||||||
|
#endif
|
||||||
|
|
||||||
|
if (pin != MAX3421_INTR_PIN) return;
|
||||||
tuh_int_handler(1, true);
|
tuh_int_handler(1, true);
|
||||||
}
|
}
|
||||||
|
|
||||||
@@ -341,7 +354,11 @@ static void max3421_init(void) {
|
|||||||
.sck_pin = MAX3421_SCK_PIN,
|
.sck_pin = MAX3421_SCK_PIN,
|
||||||
.mosi_pin = MAX3421_MOSI_PIN,
|
.mosi_pin = MAX3421_MOSI_PIN,
|
||||||
.miso_pin = MAX3421_MISO_PIN,
|
.miso_pin = MAX3421_MISO_PIN,
|
||||||
|
#if NRFX_VER <= 2
|
||||||
.ss_pin = NRFX_SPIM_PIN_NOT_USED,
|
.ss_pin = NRFX_SPIM_PIN_NOT_USED,
|
||||||
|
#else
|
||||||
|
.ss_pin = NRF_SPIM_PIN_NOT_CONNECTED,
|
||||||
|
#endif
|
||||||
.ss_active_high = false,
|
.ss_active_high = false,
|
||||||
.irq_priority = 3,
|
.irq_priority = 3,
|
||||||
.orc = 0xFF,
|
.orc = 0xFF,
|
||||||
@@ -355,14 +372,35 @@ static void max3421_init(void) {
|
|||||||
nrfx_spim_init(&_spi, &cfg, NULL, NULL);
|
nrfx_spim_init(&_spi, &cfg, NULL, NULL);
|
||||||
|
|
||||||
// max3421e interrupt pin
|
// max3421e interrupt pin
|
||||||
|
#if NRFX_VER <= 2
|
||||||
nrfx_gpiote_init(1);
|
nrfx_gpiote_init(1);
|
||||||
nrfx_gpiote_in_config_t in_config = NRFX_GPIOTE_CONFIG_IN_SENSE_HITOLO(true);
|
nrfx_gpiote_in_config_t in_config = NRFX_GPIOTE_CONFIG_IN_SENSE_HITOLO(true);
|
||||||
in_config.pull = NRF_GPIO_PIN_PULLUP;
|
in_config.pull = NRF_GPIO_PIN_PULLUP;
|
||||||
|
|
||||||
NVIC_SetPriority(GPIOTE_IRQn, 2);
|
NVIC_SetPriority(GPIOTE_IRQn, 2);
|
||||||
|
|
||||||
nrfx_gpiote_in_init(MAX3421_INTR_PIN, &in_config, max3421_int_handler);
|
nrfx_gpiote_in_init(MAX3421_INTR_PIN, &in_config, max3421_int_handler);
|
||||||
nrfx_gpiote_trigger_enable(MAX3421_INTR_PIN, true);
|
nrfx_gpiote_trigger_enable(MAX3421_INTR_PIN, true);
|
||||||
|
#else
|
||||||
|
nrf_gpio_pin_pull_t intr_pull = NRF_GPIO_PIN_PULLUP;
|
||||||
|
nrfx_gpiote_trigger_config_t intr_trigger = {
|
||||||
|
.trigger = NRFX_GPIOTE_TRIGGER_HITOLO,
|
||||||
|
.p_in_channel = NULL, // sensing mechanism
|
||||||
|
};
|
||||||
|
nrfx_gpiote_handler_config_t intr_handler = {
|
||||||
|
.handler = max3421_int_handler,
|
||||||
|
.p_context = NULL,
|
||||||
|
};
|
||||||
|
nrfx_gpiote_input_pin_config_t intr_config = {
|
||||||
|
.p_pull_config = &intr_pull,
|
||||||
|
.p_trigger_config = &intr_trigger,
|
||||||
|
.p_handler_config = &intr_handler,
|
||||||
|
};
|
||||||
|
|
||||||
|
nrfx_gpiote_init(&_gpiote, 1);
|
||||||
|
NVIC_SetPriority(GPIOTE_IRQn, 2);
|
||||||
|
|
||||||
|
nrfx_gpiote_input_configure(&_gpiote, MAX3421_INTR_PIN, &intr_config);
|
||||||
|
nrfx_gpiote_trigger_enable(&_gpiote, MAX3421_INTR_PIN, true);
|
||||||
|
#endif
|
||||||
}
|
}
|
||||||
|
|
||||||
// API to enable/disable MAX3421 INTR pin interrupt
|
// API to enable/disable MAX3421 INTR pin interrupt
|
||||||
|
@@ -5,7 +5,7 @@ SEARCH_DIR(.)
|
|||||||
|
|
||||||
MEMORY
|
MEMORY
|
||||||
{
|
{
|
||||||
FLASH (rx) : ORIGIN = 0x26000, LENGTH = 0xED000 - 0x26000
|
FLASH (rx) : ORIGIN = 0x26000, LENGTH = 0xED000 - 0x26000
|
||||||
|
|
||||||
/* SRAM required by S132 depend on
|
/* SRAM required by S132 depend on
|
||||||
* - Attribute Table Size
|
* - Attribute Table Size
|
||||||
@@ -14,7 +14,7 @@ MEMORY
|
|||||||
* - Concurrent connection peripheral + central + secure links
|
* - Concurrent connection peripheral + central + secure links
|
||||||
* - Event Len, HVN queue, Write CMD queue
|
* - Event Len, HVN queue, Write CMD queue
|
||||||
*/
|
*/
|
||||||
RAM (rwx) : ORIGIN = 0x20003400, LENGTH = 0x20040000 - 0x20003400
|
RAM (rwx) : ORIGIN = 0x20003400, LENGTH = 0x20040000 - 0x20003400
|
||||||
}
|
}
|
||||||
|
|
||||||
SECTIONS
|
SECTIONS
|
||||||
@@ -36,3 +36,9 @@ SECTIONS
|
|||||||
} INSERT AFTER .data;
|
} INSERT AFTER .data;
|
||||||
|
|
||||||
INCLUDE "nrf_common.ld"
|
INCLUDE "nrf_common.ld"
|
||||||
|
|
||||||
|
/* nrfx v2 linker does not define __tbss_start/end__ __sbss_start/end__*/
|
||||||
|
__tbss_start__ = __tbss_start;
|
||||||
|
__tbss_end__ = __tbss_end;
|
||||||
|
__sbss_start__ = __sbss_start;
|
||||||
|
__sbss_end__ = __sbss_end;
|
||||||
|
@@ -14,7 +14,7 @@ MEMORY
|
|||||||
INCLUDE "nrf_common.ld"
|
INCLUDE "nrf_common.ld"
|
||||||
|
|
||||||
/* nrfx v2 linker does not define __tbss_start/end__ __sbss_start/end__*/
|
/* nrfx v2 linker does not define __tbss_start/end__ __sbss_start/end__*/
|
||||||
/*__tbss_start__ = __tbss_start;*/
|
__tbss_start__ = __tbss_start;
|
||||||
/*__tbss_end__ = __tbss_end;*/
|
__tbss_end__ = __tbss_end;
|
||||||
/*__sbss_start__ = __sbss_start;*/
|
__sbss_start__ = __sbss_start;
|
||||||
/*__sbss_end__ = __sbss_end;*/
|
__sbss_end__ = __sbss_end;
|
||||||
|
@@ -6,6 +6,7 @@
|
|||||||
|
|
||||||
#define NRFX_CLOCK_ENABLED 0
|
#define NRFX_CLOCK_ENABLED 0
|
||||||
#define NRFX_GPIOTE_ENABLED 1
|
#define NRFX_GPIOTE_ENABLED 1
|
||||||
|
#define NRFX_GPIOTE0_ENABLED 1
|
||||||
|
|
||||||
#define NRFX_UARTE_ENABLED 1
|
#define NRFX_UARTE_ENABLED 1
|
||||||
#define NRFX_UARTE0_ENABLED 1
|
#define NRFX_UARTE0_ENABLED 1
|
||||||
|
Reference in New Issue
Block a user