Merge branch 'master' into ZLP_Request2
This commit is contained in:
@@ -74,7 +74,7 @@ bool tud_hid_ready(void)
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{
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uint8_t itf = 0;
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uint8_t const ep_in = _hidd_itf[itf].ep_in;
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return tud_ready() && (ep_in != 0) && !usbd_edpt_busy(TUD_OPT_RHPORT, ep_in);
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return tud_ready() && (ep_in != 0) && usbd_edpt_ready(TUD_OPT_RHPORT, ep_in);
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}
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bool tud_hid_report(uint8_t report_id, void const* report, uint8_t len)
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@@ -86,16 +86,19 @@ bool tud_midi_n_mounted (uint8_t itf)
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//--------------------------------------------------------------------+
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uint32_t tud_midi_n_available(uint8_t itf, uint8_t jack_id)
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{
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(void) jack_id;
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return tu_fifo_count(&_midid_itf[itf].rx_ff);
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}
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uint32_t tud_midi_n_read(uint8_t itf, uint8_t jack_id, void* buffer, uint32_t bufsize)
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{
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(void) jack_id;
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return tu_fifo_read_n(&_midid_itf[itf].rx_ff, buffer, bufsize);
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}
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void tud_midi_n_read_flush (uint8_t itf, uint8_t jack_id)
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{
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(void) jack_id;
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tu_fifo_clear(&_midid_itf[itf].rx_ff);
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}
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@@ -128,6 +131,8 @@ void midi_rx_done_cb(midid_interface_t* midi, uint8_t const* buffer, uint32_t bu
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static bool maybe_transmit(midid_interface_t* midi, uint8_t itf_index)
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{
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(void) itf_index;
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// skip if previous transfer not complete
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TU_VERIFY( !usbd_edpt_busy(TUD_OPT_RHPORT, midi->ep_in) );
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@@ -309,11 +314,15 @@ bool midid_open(uint8_t rhport, tusb_desc_interface_t const * p_interface_desc,
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bool midid_control_complete(uint8_t rhport, tusb_control_request_t const * p_request)
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{
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return false;
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(void) rhport;
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(void) p_request;
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return true;
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}
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bool midid_control_request(uint8_t rhport, tusb_control_request_t const * p_request)
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{
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(void) rhport;
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//------------- Class Specific Request -------------//
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if (p_request->bmRequestType_bit.type != TUSB_REQ_TYPE_CLASS) return false;
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@@ -322,6 +331,8 @@ bool midid_control_request(uint8_t rhport, tusb_control_request_t const * p_requ
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bool midid_xfer_cb(uint8_t rhport, uint8_t ep_addr, xfer_result_t result, uint32_t xferred_bytes)
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{
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(void) result;
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// TODO Support multiple interfaces
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uint8_t const itf = 0;
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midid_interface_t* p_midi = &_midid_itf[itf];
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@@ -52,14 +52,19 @@ typedef struct {
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uint8_t self_powered : 1; // configuration descriptor's attribute
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};
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uint8_t ep_busy_map[2]; // bit mask for busy endpoint
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uint8_t ep_stall_map[2]; // bit map for stalled endpoint
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uint8_t itf2drv[16]; // map interface number to driver (0xff is invalid)
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uint8_t ep2drv[8][2]; // map endpoint to driver ( 0xff is invalid )
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struct TU_ATTR_PACKED
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{
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volatile bool busy : 1;
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volatile bool stalled : 1;
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// TODO merge ep2drv here, 4-bit should be sufficient
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}ep_status[8][2];
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}usbd_device_t;
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static usbd_device_t _usbd_dev = { 0 };
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static usbd_device_t _usbd_dev;
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// Invalid driver ID in itf2drv[] ep2drv[][] mapping
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enum { DRVID_INVALID = 0xFFu };
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@@ -310,7 +315,7 @@ void tud_task (void)
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uint8_t const epnum = tu_edpt_number(ep_addr);
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uint8_t const ep_dir = tu_edpt_dir(ep_addr);
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_usbd_dev.ep_busy_map[ep_dir] = (uint8_t) tu_bit_clear(_usbd_dev.ep_busy_map[ep_dir], epnum);
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_usbd_dev.ep_status[epnum][ep_dir].busy = false;
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if ( 0 == epnum )
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{
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@@ -864,8 +869,7 @@ bool usbd_edpt_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t * buffer, uint16_t
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uint8_t const dir = tu_edpt_dir(ep_addr);
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TU_VERIFY( dcd_edpt_xfer(rhport, ep_addr, buffer, total_bytes) );
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_usbd_dev.ep_busy_map[dir] = (uint8_t) tu_bit_set(_usbd_dev.ep_busy_map[dir], epnum);
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_usbd_dev.ep_status[epnum][dir].busy = true;
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return true;
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}
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@@ -877,18 +881,17 @@ bool usbd_edpt_busy(uint8_t rhport, uint8_t ep_addr)
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uint8_t const epnum = tu_edpt_number(ep_addr);
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uint8_t const dir = tu_edpt_dir(ep_addr);
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return tu_bit_test(_usbd_dev.ep_busy_map[dir], epnum);
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return _usbd_dev.ep_status[epnum][dir].busy;
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}
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void usbd_edpt_stall(uint8_t rhport, uint8_t ep_addr)
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{
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uint8_t const epnum = tu_edpt_number(ep_addr);
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uint8_t const dir = tu_edpt_dir(ep_addr);
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dcd_edpt_stall(rhport, ep_addr);
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_usbd_dev.ep_stall_map[dir] = (uint8_t) tu_bit_set(_usbd_dev.ep_stall_map[dir], epnum);
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_usbd_dev.ep_busy_map[dir] = (uint8_t) tu_bit_set(_usbd_dev.ep_busy_map[dir], epnum);
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_usbd_dev.ep_status[epnum][dir].stalled = true;
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_usbd_dev.ep_status[epnum][dir].busy = true;
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}
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void usbd_edpt_clear_stall(uint8_t rhport, uint8_t ep_addr)
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@@ -897,8 +900,8 @@ void usbd_edpt_clear_stall(uint8_t rhport, uint8_t ep_addr)
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uint8_t const dir = tu_edpt_dir(ep_addr);
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dcd_edpt_clear_stall(rhport, ep_addr);
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_usbd_dev.ep_busy_map[dir] = (uint8_t) tu_bit_clear(_usbd_dev.ep_busy_map[dir], epnum);
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_usbd_dev.ep_stall_map[dir] = (uint8_t) tu_bit_clear(_usbd_dev.ep_stall_map[dir], epnum);
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_usbd_dev.ep_status[epnum][dir].stalled = false;
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_usbd_dev.ep_status[epnum][dir].busy = false;
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}
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bool usbd_edpt_stalled(uint8_t rhport, uint8_t ep_addr)
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@@ -908,7 +911,7 @@ bool usbd_edpt_stalled(uint8_t rhport, uint8_t ep_addr)
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uint8_t const epnum = tu_edpt_number(ep_addr);
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uint8_t const dir = tu_edpt_dir(ep_addr);
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return tu_bit_test(_usbd_dev.ep_stall_map[dir], epnum);
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return _usbd_dev.ep_status[epnum][dir].stalled;
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}
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#endif
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@@ -47,10 +47,21 @@ bool usbd_edpt_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t * buffer, uint16_t
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// Check if endpoint transferring is complete
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bool usbd_edpt_busy(uint8_t rhport, uint8_t ep_addr);
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// Stall endpoint
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void usbd_edpt_stall(uint8_t rhport, uint8_t ep_addr);
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// Clear stalled endpoint
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void usbd_edpt_clear_stall(uint8_t rhport, uint8_t ep_addr);
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// Check if endpoint is stalled
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bool usbd_edpt_stalled(uint8_t rhport, uint8_t ep_addr);
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static inline
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bool usbd_edpt_ready(uint8_t rhport, uint8_t ep_addr)
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{
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return !usbd_edpt_busy(rhport, ep_addr) && !usbd_edpt_stalled(rhport, ep_addr);
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}
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/*------------------------------------------------------------------*/
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/* Helper
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*------------------------------------------------------------------*/
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@@ -145,6 +145,8 @@ typedef osal_queue_def_t* osal_queue_t;
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// lock queue by disable usb isr
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static inline void _osal_q_lock(osal_queue_t qhdl)
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{
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(void) qhdl;
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#if TUSB_OPT_DEVICE_ENABLED
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if (qhdl->role == OPT_MODE_DEVICE) dcd_int_disable(TUD_OPT_RHPORT);
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#endif
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@@ -157,6 +159,8 @@ static inline void _osal_q_lock(osal_queue_t qhdl)
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// unlock queue
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static inline void _osal_q_unlock(osal_queue_t qhdl)
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{
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(void) qhdl;
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#if TUSB_OPT_DEVICE_ENABLED
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if (qhdl->role == OPT_MODE_DEVICE) dcd_int_enable(TUD_OPT_RHPORT);
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#endif
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@@ -103,17 +103,17 @@
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#include "tusb_option.h"
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#define STM32F1_FSDEV ( \
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defined(STM32F102x6) || defined(STM32F102xB) || \
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#if defined(STM32F102x6) || defined(STM32F102xB) || \
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defined(STM32F103x6) || defined(STM32F103xB) || \
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defined(STM32F103xE) || defined(STM32F103xG) \
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)
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defined(STM32F103xE) || defined(STM32F103xG)
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#define STM32F1_FSDEV
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#endif
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#if (TUSB_OPT_DEVICE_ENABLED) && ( \
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(CFG_TUSB_MCU == OPT_MCU_STM32F0 ) || \
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(CFG_TUSB_MCU == OPT_MCU_STM32F1 && STM32F1_FSDEV ) || \
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(CFG_TUSB_MCU == OPT_MCU_STM32F3 ) || \
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(CFG_TUSB_MCU == OPT_MCU_STM32L0 ) \
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(CFG_TUSB_MCU == OPT_MCU_STM32F0 ) || \
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(CFG_TUSB_MCU == OPT_MCU_STM32F1 && defined(STM32F1_FSDEV)) || \
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(CFG_TUSB_MCU == OPT_MCU_STM32F3 ) || \
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(CFG_TUSB_MCU == OPT_MCU_STM32L0 ) \
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)
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// In order to reduce the dependance on HAL, we undefine this.
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@@ -252,7 +252,9 @@ void dcd_init (uint8_t rhport)
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void dcd_int_enable (uint8_t rhport)
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{
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(void)rhport;
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// Member here forces write to RAM before allowing ISR to execute
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__DSB();
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__ISB();
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#if CFG_TUSB_MCU == OPT_MCU_STM32F0 || CFG_TUSB_MCU == OPT_MCU_STM32L0
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NVIC_EnableIRQ(USB_IRQn);
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#elif CFG_TUSB_MCU == OPT_MCU_STM32F3
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@@ -276,10 +278,7 @@ void dcd_int_disable(uint8_t rhport)
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#else
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#error Unknown arch in USB driver
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#endif
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// I'm not convinced that memory synchronization is completely necessary, but
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// it isn't a bad idea.
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__DSB();
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__ISB();
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// CMSIS has a membar after disabling interrupts
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}
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// Receive Set Address request, mcu port must also include status IN response
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@@ -419,10 +418,15 @@ static uint16_t dcd_ep_ctr_handler(void)
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uint8_t userMemBuf[8];
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/* Get SETUP Packet*/
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count = pcd_get_ep_rx_cnt(USB, EPindex);
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//TU_ASSERT_ERR(count == 8);
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dcd_read_packet_memory(userMemBuf, *pcd_ep_rx_address_ptr(USB,EPindex), 8);
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if(count == 8) // Setup packet should always be 8 bytes. If not, ignore it, and try again.
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{
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// Must reset EP to NAK (in case it had been stalling) (though, maybe too late here)
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pcd_set_ep_rx_status(USB,0u,USB_EP_RX_NAK);
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pcd_set_ep_tx_status(USB,0u,USB_EP_TX_NAK);
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dcd_read_packet_memory(userMemBuf, *pcd_ep_rx_address_ptr(USB,EPindex), 8);
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dcd_event_setup_received(0, (uint8_t*)userMemBuf, true);
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}
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/* SETUP bit kept frozen while CTR_RX = 1*/
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dcd_event_setup_received(0, (uint8_t*)userMemBuf, true);
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pcd_clear_rx_ep_ctr(USB, EPindex);
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}
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else if ((wEPVal & USB_EP_CTR_RX) != 0U) // OUT
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@@ -440,10 +444,6 @@ static uint16_t dcd_ep_ctr_handler(void)
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}
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/* Process Control Data OUT status Packet*/
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if(EPindex == 0u && xfer->total_len == 0u)
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{
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pcd_clear_ep_kind(USB,0); // Good, so allow non-zero length packets now.
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}
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dcd_event_xfer_complete(0, EPindex, xfer->total_len, XFER_RESULT_SUCCESS, true);
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pcd_set_ep_rx_cnt(USB, EPindex, CFG_TUD_ENDPOINT0_SIZE);
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@@ -627,7 +627,9 @@ bool dcd_edpt_open (uint8_t rhport, tusb_desc_endpoint_t const * p_endpoint_desc
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}
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pcd_set_ep_address(USB, epnum, epnum);
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pcd_clear_ep_kind(USB,0); // Be normal, for now, instead of only accepting zero-byte packets
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// Be normal, for now, instead of only accepting zero-byte packets (on control endpoint)
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// or being double-buffered (bulk endpoints)
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pcd_clear_ep_kind(USB,0);
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if(dir == TUSB_DIR_IN)
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{
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@@ -688,7 +690,6 @@ bool dcd_edpt_xfer (uint8_t rhport, uint8_t ep_addr, uint8_t * buffer, uint16_t
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if (epnum == 0 && buffer == NULL)
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{
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xfer->buffer = (uint8_t*)_setup_packet;
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pcd_set_ep_kind(USB,0); // Expect a zero-byte INPUT
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}
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if(total_bytes > xfer->max_packet_size)
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{
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@@ -52,7 +52,7 @@
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// 070RB: 2 x 16 bits/word memory LPM Support, BCD Support
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// PMA dedicated to USB (no sharing with CAN)
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#elif STM32F1_FSDEV
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#elif defined(STM32F1_FSDEV)
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#include "stm32f1xx.h"
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#define PMA_LENGTH (512u)
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// NO internal Pull-ups
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@@ -27,19 +27,19 @@
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#include "tusb_option.h"
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#define STM32L4_SYNOPSYS ( \
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defined (STM32L475xx) || defined (STM32L476xx) || \
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#if defined (STM32L475xx) || defined (STM32L476xx) || \
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defined (STM32L485xx) || defined (STM32L486xx) || defined (STM32L496xx) || \
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defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || \
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defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) \
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)
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defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx)
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#define STM32L4_SYNOPSYS
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#endif
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#if TUSB_OPT_DEVICE_ENABLED && \
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( CFG_TUSB_MCU == OPT_MCU_STM32F2 || \
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CFG_TUSB_MCU == OPT_MCU_STM32F4 || \
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CFG_TUSB_MCU == OPT_MCU_STM32F7 || \
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CFG_TUSB_MCU == OPT_MCU_STM32H7 || \
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(CFG_TUSB_MCU == OPT_MCU_STM32L4 && STM32L4_SYNOPSYS) \
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(CFG_TUSB_MCU == OPT_MCU_STM32L4 && defined(STM32L4_SYNOPSYS)) \
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)
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// TODO Support OTG_HS
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