refractoring test code
This commit is contained in:
hathach
@@ -56,7 +56,7 @@ uint8_t dev_addr;
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uint8_t hostid;
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ehci_qhd_t *async_head;
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ehci_qhd_t *period_head;
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ehci_qhd_t *p_control_qhd;
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//--------------------------------------------------------------------+
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// Setup/Teardown + helper declare
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@@ -83,7 +83,7 @@ void setUp(void)
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}
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async_head = get_async_head( hostid );
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period_head = get_period_head( hostid );
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p_control_qhd = &ehci_data.device[dev_addr-1].control.qhd;
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}
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void tearDown(void)
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@@ -115,7 +115,7 @@ void verify_open_qhd(ehci_qhd_t *p_qhd, uint8_t endpoint_addr, uint16_t max_pack
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}
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//--------------------------------------------------------------------+
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// CONTROL PIPE
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// PIPE OPEN
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//--------------------------------------------------------------------+
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void verify_control_open_qhd(ehci_qhd_t *p_qhd)
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{
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@@ -131,238 +131,70 @@ void test_control_open_addr0_qhd_data(void)
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{
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dev_addr = 0;
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ehci_qhd_t * const p_qhd = async_head;
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//------------- Code Under Test -------------//
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hcd_pipe_control_open(dev_addr, control_max_packet_size);
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verify_control_open_qhd(p_qhd);
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TEST_ASSERT(p_qhd->head_list_flag);
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verify_control_open_qhd(async_head);
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TEST_ASSERT(async_head->head_list_flag);
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}
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void test_control_open_qhd_data(void)
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{
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ehci_qhd_t * const p_qhd = &ehci_data.device[dev_addr-1].control.qhd;
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//------------- Code Under TEST -------------//
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hcd_pipe_control_open(dev_addr, control_max_packet_size);
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verify_control_open_qhd(p_qhd);
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TEST_ASSERT_FALSE(p_qhd->head_list_flag);
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verify_control_open_qhd(p_control_qhd);
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TEST_ASSERT_FALSE(p_control_qhd->head_list_flag);
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//------------- async list check -------------//
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TEST_ASSERT_EQUAL_HEX((uint32_t) p_qhd, align32(async_head->next.address));
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TEST_ASSERT_EQUAL_HEX((uint32_t) p_control_qhd, align32(async_head->next.address));
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TEST_ASSERT_FALSE(async_head->next.terminate);
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TEST_ASSERT_EQUAL(EHCI_QUEUE_ELEMENT_QHD, async_head->next.type);
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}
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void test_control_open_highspeed(void)
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{
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ehci_qhd_t * const p_qhd = &ehci_data.device[dev_addr].control.qhd;
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usbh_device_info_pool[dev_addr].speed = TUSB_SPEED_HIGH;
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//------------- Code Under TEST -------------//
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hcd_pipe_control_open(dev_addr, control_max_packet_size);
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TEST_ASSERT_FALSE(p_qhd->non_hs_control_endpoint);
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TEST_ASSERT_FALSE(p_control_qhd->non_hs_control_endpoint);
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}
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void test_control_open_non_highspeed(void)
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{
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ehci_qhd_t * const p_qhd = &ehci_data.device[dev_addr-1].control.qhd;
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usbh_device_info_pool[dev_addr].speed = TUSB_SPEED_FULL;
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//------------- Code Under TEST -------------//
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hcd_pipe_control_open(dev_addr, control_max_packet_size);
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TEST_ASSERT_TRUE(p_qhd->non_hs_control_endpoint);
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TEST_ASSERT_TRUE(p_control_qhd->non_hs_control_endpoint);
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}
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//--------------------------------------------------------------------+
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// PIPE CLOSE
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//--------------------------------------------------------------------+
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void test_control_addr0_close(void)
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{
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ehci_qhd_t * const p_qhd = async_head;
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dev_addr = 0;
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hcd_pipe_control_open(dev_addr, control_max_packet_size);
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//------------- Code Under Test -------------//
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hcd_pipe_control_close(dev_addr);
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TEST_ASSERT(p_qhd->head_list_flag);
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TEST_ASSERT(p_qhd->is_removing);
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TEST_ASSERT(async_head->head_list_flag);
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TEST_ASSERT(async_head->is_removing);
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}
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void test_control_close(void)
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{
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ehci_qhd_t * const p_qhd = &ehci_data.device[dev_addr-1].control.qhd;
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hcd_pipe_control_open(dev_addr, control_max_packet_size);
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//------------- Code Under TEST -------------//
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hcd_pipe_control_close(dev_addr);
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TEST_ASSERT(p_qhd->is_removing);
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TEST_ASSERT(p_qhd->used);
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TEST_ASSERT(p_control_qhd->is_removing);
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TEST_ASSERT(p_control_qhd->used);
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TEST_ASSERT( align32(get_async_head(hostid)->next.address) != (uint32_t) p_qhd );
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TEST_ASSERT_EQUAL( get_async_head(hostid), align32(p_qhd->next.address));
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}
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//--------------------------------------------------------------------+
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// BULK PIPE
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//--------------------------------------------------------------------+
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tusb_descriptor_endpoint_t const desc_ept_bulk_in =
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{
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.bLength = sizeof(tusb_descriptor_endpoint_t),
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.bDescriptorType = TUSB_DESC_ENDPOINT,
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.bEndpointAddress = 0x81,
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.bmAttributes = { .xfer = TUSB_XFER_BULK },
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.wMaxPacketSize = 512,
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.bInterval = 0
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};
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void verify_bulk_open_qhd(ehci_qhd_t *p_qhd, tusb_descriptor_endpoint_t const * desc_endpoint, uint8_t class_code)
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{
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verify_open_qhd(p_qhd, desc_endpoint->bEndpointAddress, desc_endpoint->wMaxPacketSize);
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TEST_ASSERT_FALSE(p_qhd->head_list_flag);
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TEST_ASSERT_EQUAL(0, p_qhd->data_toggle_control);
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TEST_ASSERT_EQUAL(0, p_qhd->interrupt_smask);
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TEST_ASSERT_EQUAL(0, p_qhd->non_hs_interrupt_cmask);
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TEST_ASSERT_FALSE(p_qhd->non_hs_control_endpoint);
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// TEST_ASSERT_EQUAL(desc_endpoint->bInterval); TDD highspeed bulk/control OUT
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TEST_ASSERT_EQUAL(desc_endpoint->bEndpointAddress & 0x80 ? EHCI_PID_IN : EHCI_PID_OUT, p_qhd->pid_non_control);
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TEST_ASSERT_EQUAL(class_code, p_qhd->class_code);
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//------------- async list check -------------//
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TEST_ASSERT_EQUAL_HEX((uint32_t) p_qhd, align32(async_head->next.address));
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TEST_ASSERT_FALSE(async_head->next.terminate);
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TEST_ASSERT_EQUAL(EHCI_QUEUE_ELEMENT_QHD, async_head->next.type);
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}
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void test_open_bulk_qhd_data(void)
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{
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ehci_qhd_t *p_qhd;
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pipe_handle_t pipe_hdl;
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tusb_descriptor_endpoint_t const * desc_endpoint = &desc_ept_bulk_in;
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//------------- Code Under TEST -------------//
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pipe_hdl = hcd_pipe_open(dev_addr, desc_endpoint, TUSB_CLASS_MSC);
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TEST_ASSERT_EQUAL(dev_addr, pipe_hdl.dev_addr);
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TEST_ASSERT_EQUAL(TUSB_XFER_BULK, pipe_hdl.xfer_type);
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p_qhd = &ehci_data.device[ pipe_hdl.dev_addr ].qhd[ pipe_hdl.index ];
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verify_bulk_open_qhd(p_qhd, desc_endpoint, TUSB_CLASS_MSC);
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//------------- async list check -------------//
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TEST_ASSERT_EQUAL_HEX((uint32_t) p_qhd, align32(async_head->next.address));
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TEST_ASSERT_FALSE(async_head->next.terminate);
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TEST_ASSERT_EQUAL(EHCI_QUEUE_ELEMENT_QHD, async_head->next.type);
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}
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void test_bulk_close(void)
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{
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tusb_descriptor_endpoint_t const * desc_endpoint = &desc_ept_bulk_in;
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pipe_handle_t pipe_hdl = hcd_pipe_open(dev_addr, desc_endpoint, TUSB_CLASS_MSC);
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ehci_qhd_t *p_qhd = &ehci_data.device[ pipe_hdl.dev_addr ].qhd[ pipe_hdl.index ];
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//------------- Code Under TEST -------------//
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hcd_pipe_close(pipe_hdl);
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TEST_ASSERT(p_qhd->is_removing);
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TEST_ASSERT( align32(get_async_head(hostid)->next.address) != (uint32_t) p_qhd );
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TEST_ASSERT_EQUAL_HEX( (uint32_t) get_async_head(hostid), align32(p_qhd->next.address ) );
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}
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//--------------------------------------------------------------------+
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// INTERRUPT PIPE
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//--------------------------------------------------------------------+
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tusb_descriptor_endpoint_t const desc_ept_interrupt_out =
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{
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.bLength = sizeof(tusb_descriptor_endpoint_t),
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.bDescriptorType = TUSB_DESC_ENDPOINT,
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.bEndpointAddress = 0x02,
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.bmAttributes = { .xfer = TUSB_XFER_INTERRUPT },
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.wMaxPacketSize = 16,
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.bInterval = 1
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};
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void verify_int_qhd(ehci_qhd_t *p_qhd, tusb_descriptor_endpoint_t const * desc_endpoint, uint8_t class_code)
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{
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verify_open_qhd(p_qhd, desc_endpoint->bEndpointAddress, desc_endpoint->wMaxPacketSize);
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TEST_ASSERT_FALSE(p_qhd->head_list_flag);
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TEST_ASSERT_EQUAL(0, p_qhd->data_toggle_control);
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TEST_ASSERT_FALSE(p_qhd->non_hs_control_endpoint);
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// TEST_ASSERT_EQUAL(desc_endpoint->bInterval); TDD highspeed bulk/control OUT
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TEST_ASSERT_EQUAL(desc_endpoint->bEndpointAddress & 0x80 ? EHCI_PID_IN : EHCI_PID_OUT, p_qhd->pid_non_control);
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//------------- period list check -------------//
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TEST_ASSERT_EQUAL_HEX((uint32_t) p_qhd, align32(period_head->next.address));
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TEST_ASSERT_FALSE(period_head->next.terminate);
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TEST_ASSERT_EQUAL(EHCI_QUEUE_ELEMENT_QHD, period_head->next.type);
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}
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void test_open_interrupt_qhd_hs(void)
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{
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ehci_qhd_t *p_qhd;
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pipe_handle_t pipe_hdl;
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//------------- Code Under TEST -------------//
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pipe_hdl = hcd_pipe_open(dev_addr, &desc_ept_interrupt_out, TUSB_CLASS_HID);
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TEST_ASSERT_EQUAL(dev_addr, pipe_hdl.dev_addr);
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TEST_ASSERT_EQUAL(TUSB_XFER_INTERRUPT, pipe_hdl.xfer_type);
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p_qhd = &ehci_data.device[ pipe_hdl.dev_addr ].qhd[ pipe_hdl.index ];
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verify_int_qhd(p_qhd, &desc_ept_interrupt_out, TUSB_CLASS_HID);
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TEST_ASSERT_EQUAL(0xFF, p_qhd->interrupt_smask);
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//TEST_ASSERT_EQUAL(0, p_qhd->non_hs_interrupt_cmask); cmask in high speed is ignored
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}
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void test_open_interrupt_qhd_non_hs(void)
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{
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ehci_qhd_t *p_qhd;
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pipe_handle_t pipe_hdl;
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usbh_device_info_pool[dev_addr].speed = TUSB_SPEED_FULL;
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//------------- Code Under TEST -------------//
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pipe_hdl = hcd_pipe_open(dev_addr, &desc_ept_interrupt_out, TUSB_CLASS_HID);
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TEST_ASSERT_EQUAL(dev_addr, pipe_hdl.dev_addr);
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TEST_ASSERT_EQUAL(TUSB_XFER_INTERRUPT, pipe_hdl.xfer_type);
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p_qhd = &ehci_data.device[ pipe_hdl.dev_addr ].qhd[ pipe_hdl.index ];
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verify_int_qhd(p_qhd, &desc_ept_interrupt_out, TUSB_CLASS_HID);
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TEST_ASSERT_EQUAL(1, p_qhd->interrupt_smask);
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TEST_ASSERT_EQUAL(0x1c, p_qhd->non_hs_interrupt_cmask);
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}
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//--------------------------------------------------------------------+
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// TODO ISOCRHONOUS PIPE
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//--------------------------------------------------------------------+
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tusb_descriptor_endpoint_t const desc_ept_iso_in =
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{
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.bLength = sizeof(tusb_descriptor_endpoint_t),
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.bDescriptorType = TUSB_DESC_ENDPOINT,
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.bEndpointAddress = 0x83,
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.bmAttributes = { .xfer = TUSB_XFER_ISOCHRONOUS },
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.wMaxPacketSize = 1024,
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.bInterval = 1
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};
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void test_open_isochronous(void)
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{
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pipe_handle_t pipe_hdl = hcd_pipe_open(dev_addr, &desc_ept_iso_in, TUSB_CLASS_AUDIO);
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TEST_ASSERT_EQUAL(0, pipe_hdl.dev_addr);
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TEST_ASSERT( align32(get_async_head(hostid)->next.address) != (uint32_t) p_control_qhd );
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TEST_ASSERT_EQUAL( get_async_head(hostid), align32(p_control_qhd->next.address));
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}
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