channge DWC2_CHANNEL_COUNT/DWC2_EP_COUNT to inline function

hw/bsp/broadcom_32bit/family.cmake

@@ -42,7 +42,7 @@ function(add_board_target BOARD_TARGET)
     -ffreestanding
     -mgeneral-regs-only
     -fno-exceptions
-    -std=gnu17
+    -std=c17
     )
   target_include_directories(${BOARD_TARGET} PUBLIC
     ${SDK_DIR}

hw/bsp/broadcom_32bit/family.mk

@@ -10,7 +10,7 @@ CFLAGS += \
 	-nostartfiles \
 	-mgeneral-regs-only \
 	-fno-exceptions \
-	-std=gnu17
+	-std=c17
 
 CROSS_COMPILE = arm-none-eabi-
 

hw/bsp/broadcom_64bit/family.cmake

@@ -43,7 +43,7 @@ function(add_board_target BOARD_TARGET)
     -ffreestanding
     -mgeneral-regs-only
     -fno-exceptions
-    -std=gnu17
+    -std=c17
     )
   target_compile_definitions(${BOARD_TARGET} PUBLIC
     BCM_VERSION=${BCM_VERSION}

hw/bsp/broadcom_64bit/family.mk

@@ -9,7 +9,7 @@ CFLAGS += \
 	-nostartfiles \
 	--specs=nosys.specs \
 	-mgeneral-regs-only \
-	-std=gnu17
+	-std=c17
 
 CROSS_COMPILE = aarch64-none-elf-
 

src/portable/synopsys/dwc2/dcd_dwc2.c

@@ -41,12 +41,6 @@
 #include "device/dcd.h"
 #include "dwc2_common.h"
 
-#if TU_CHECK_MCU(OPT_MCU_GD32VF103)
-  #define DWC2_EP_COUNT(_dwc2)   DWC2_EP_MAX
-#else
-  #define DWC2_EP_COUNT(_dwc2)  ({const dwc2_ghwcfg2_t ghwcfg2 = {.value = (_dwc2)->ghwcfg2};  ghwcfg2.num_dev_ep + 1;})
-#endif
-
 //--------------------------------------------------------------------+
 // MACRO TYPEDEF CONSTANT ENUM
 //--------------------------------------------------------------------+
@@ -79,6 +73,16 @@ CFG_TUD_MEM_SECTION static struct {
   TUD_EPBUF_DEF(setup_packet, 8);
 } _dcd_usbbuf;
 
+TU_ATTR_ALWAYS_INLINE static inline uint8_t dwc2_ep_count(const dwc2_regs_t* dwc2) {
+  #if TU_CHECK_MCU(OPT_MCU_GD32VF103)
+  return DWC2_EP_MAX;
+  #else
+  const dwc2_ghwcfg2_t ghwcfg2 = {.value = dwc2->ghwcfg2};
+  return ghwcfg2.num_dev_ep + 1;
+  #endif
+}
+
+
 //--------------------------------------------------------------------
 // DMA
 //--------------------------------------------------------------------
@@ -629,7 +633,7 @@ void dcd_edpt_clear_stall(uint8_t rhport, uint8_t ep_addr) {
 // 7.4.1 Initialization on USB Reset
 static void handle_bus_reset(uint8_t rhport) {
   dwc2_regs_t *dwc2 = DWC2_REG(rhport);
-  const uint8_t ep_count =  DWC2_EP_COUNT(dwc2);
+  const uint8_t ep_count =  dwc2_ep_count(dwc2);
 
   tu_memclr(xfer_status, sizeof(xfer_status));
 
@@ -926,7 +930,7 @@ static void handle_epin_dma(uint8_t rhport, uint8_t epnum, dwc2_diepint_t diepin
 static void handle_ep_irq(uint8_t rhport, uint8_t dir) {
   dwc2_regs_t* dwc2 = DWC2_REG(rhport);
   const bool is_dma = dma_device_enabled(dwc2);
-  const uint8_t ep_count = DWC2_EP_COUNT(dwc2);
+  const uint8_t ep_count = dwc2_ep_count(dwc2);
   const uint8_t daint_offset = (dir == TUSB_DIR_IN) ? DAINT_IEPINT_Pos : DAINT_OEPINT_Pos;
   dwc2_dep_t* ep_base = &dwc2->ep[dir == TUSB_DIR_IN ? 0 : 1][0];
 

src/portable/synopsys/dwc2/dwc2_common.c

@@ -173,7 +173,6 @@ static bool check_dwc2(dwc2_regs_t* dwc2) {
 //--------------------------------------------------------------------
 bool dwc2_core_is_highspeed(dwc2_regs_t* dwc2, tusb_role_t role) {
   (void)dwc2;
-  const dwc2_ghwcfg2_t ghwcfg2 = {.value = dwc2->ghwcfg2};
 #if CFG_TUD_ENABLED
   if (role == TUSB_ROLE_DEVICE && !TUD_OPT_HIGH_SPEED) {
     return false;
@@ -185,6 +184,7 @@ bool dwc2_core_is_highspeed(dwc2_regs_t* dwc2, tusb_role_t role) {
   }
 #endif
 
+  const dwc2_ghwcfg2_t ghwcfg2 = {.value = dwc2->ghwcfg2};
   return ghwcfg2.hs_phy_type != GHWCFG2_HSPHY_NOT_SUPPORTED;
 }
 

src/portable/synopsys/dwc2/dwc2_type.h

@@ -413,7 +413,7 @@ TU_VERIFY_STATIC(sizeof(dwc2_hnptxsts_t) == 4, "incorrect size");
 typedef union {
   uint32_t value;
   struct TU_ATTR_PACKED {
-    uint32_t fifo_available      : 16; // 0..15 Number of words available in the Tx FIFO
+    uint32_t fifo_available      :16; // 0..15 Number of words available in the Tx FIFO
     uint32_t req_queue_available : 7; // 16..22 Number of spaces available in the PTX transmit request queue
     uint32_t qtop_terminate      : 1; // 23 Last entry for selected channel
     uint32_t qtop_last_period    : 1; // 24 Last entry for selected channel is a periodic entry
@@ -565,7 +565,7 @@ typedef union {
     uint32_t enum_speed     : 2; // 1..2 Enumerated speed
     uint32_t erratic_err    : 1; // 3 Erratic error
     uint32_t rsv4_7         : 4; // 4..7 Reserved
-    uint32_t frame_number   : 14; // 8..21 Frame/MicroFrame number
+    uint32_t frame_number   :14; // 8..21 Frame/MicroFrame number
     uint32_t line_status    : 2; // 22..23 Line status
     uint32_t rsv24_31       : 8; // 24..31 Reserved
   };
@@ -684,7 +684,7 @@ TU_VERIFY_STATIC(sizeof(dwc2_dep_t) == 0x20, "incorrect size");
 // CSR Register Map
 //--------------------------------------------------------------------
 typedef struct {
-    //------------- Core Global -------------//
+  //------------- Core Global -------------
   volatile uint32_t gotgctl;            // 000 OTG Control and Status
   volatile uint32_t gotgint;            // 004 OTG Interrupt
   volatile uint32_t gahbcfg;            // 008 AHB Configuration
@@ -727,7 +727,7 @@ typedef struct {
   volatile uint32_t dieptxf[15];        // 104..13C Device Periodic Transmit FIFO Size
             uint32_t reserved140[176];  // 140..3FF
 
-  //------------ Host -------------//
+  //------------ Host -------------
   volatile uint32_t hcfg;               // 400 Host Configuration
   volatile uint32_t hfir;               // 404 Host Frame Interval
   volatile uint32_t hfnum;              // 408 Host Frame Number / Frame Remaining
@@ -740,11 +740,11 @@ typedef struct {
   volatile uint32_t hprt;               // 440 Host Port Control and Status
             uint32_t reserved444[47];   // 444..4FF
 
-  //------------- Host Channel -------------//
+  //------------- Host Channel --------
   dwc2_channel_t    channel[16];        // 500..6FF Host Channels 0-15
             uint32_t reserved700[64];   // 700..7FF
 
-  //------------- Device -----------//
+  //------------- Device -----------
   volatile uint32_t dcfg;               // 800 Device Configuration
   volatile uint32_t dctl;               // 804 Device Control
   volatile uint32_t dsts;               // 808 Device Status (RO)
@@ -760,15 +760,15 @@ typedef struct {
   volatile uint32_t dthrctl;            // 830 Device threshold Control
   volatile uint32_t diepempmsk;         // 834 Device IN Endpoint FIFO Empty Interrupt Mask
 
-  // Device Each Endpoint (IN/OUT) Interrupt/Mask for generating dedicated EP interrupt line
+  // Device Each Endpoint (IN/OUT) Interrupt/Mask for generating dedicated EP interrupt line require
-  // require OTG_MULTI_PROC_INTRPT=1
+  // OTG_MULTI_PROC_INTRPT=1
   volatile uint32_t deachint;           // 838 Device Each Endpoint Interrupt
   volatile uint32_t deachmsk;           // 83C Device Each Endpoint Interrupt mask
   volatile uint32_t diepeachmsk[16];    // 840..87C Device Each IN Endpoint mask
   volatile uint32_t doepeachmsk[16];    // 880..8BF Device Each OUT Endpoint mask
             uint32_t reserved8c0[16];   // 8C0..8FF
 
-  //------------- Device Endpoint -------------//
+  //------------- Device Endpoint -----
   union {
     dwc2_dep_t ep[2][16];               // 0: IN, 1 OUT
     struct {
@@ -778,12 +778,12 @@ typedef struct {
   };
   uint32_t reservedd00[64];             // D00..DFF
 
-  //------------- Power Clock -------------//
+  //------------- Power Clock ---------
   volatile uint32_t pcgcctl;            // E00 Power and Clock Gating Characteristic Control
   volatile uint32_t pcgcctl1;           // E04 Power and Clock Gating Characteristic Control 1
             uint32_t reservede08[126];  // E08..FFF
 
-  //------------- FIFOs -------------//
+  //------------- FIFOs -------------
   // Word-accessed only using first pointer since it auto shift
   volatile uint32_t fifo[16][0x400];    // 1000..FFFF Endpoint FIFO
 } dwc2_regs_t;

src/portable/synopsys/dwc2/hcd_dwc2.c

@@ -44,8 +44,6 @@
 #endif
 
 #define DWC2_CHANNEL_COUNT_MAX    16 // absolute max channel count
-#define DWC2_CHANNEL_COUNT(_dwc2) ({const dwc2_ghwcfg2_t ghwcfg2 = {.value = (_dwc2)->ghwcfg2};  tu_min8(ghwcfg2.num_host_ch + 1, DWC2_CHANNEL_COUNT_MAX);})
-
 TU_VERIFY_STATIC(CFG_TUH_DWC2_ENDPOINT_MAX <= 255, "currently only use 8-bit for index");
 
 enum {
@@ -116,6 +114,11 @@ hcd_data_t _hcd_data;
 //--------------------------------------------------------------------
 //
 //--------------------------------------------------------------------
+TU_ATTR_ALWAYS_INLINE static inline uint8_t dwc2_channel_count(const dwc2_regs_t* dwc2) {
+  const dwc2_ghwcfg2_t ghwcfg2 = {.value = dwc2->ghwcfg2};
+  return tu_min8(ghwcfg2.num_host_ch + 1, DWC2_CHANNEL_COUNT_MAX);
+}
+
 TU_ATTR_ALWAYS_INLINE static inline tusb_speed_t hprt_speed_get(dwc2_regs_t* dwc2) {
   tusb_speed_t speed;
   const dwc2_hprt_t hprt = {.value = dwc2->hprt};
@@ -157,7 +160,7 @@ bool hcd_dcache_clean_invalidate(const void* addr, uint32_t data_size) {
 
 // Allocate a channel for new transfer
 TU_ATTR_ALWAYS_INLINE static inline uint8_t channel_alloc(dwc2_regs_t* dwc2) {
-  const uint8_t max_channel = DWC2_CHANNEL_COUNT(dwc2);
+  const uint8_t max_channel = dwc2_channel_count(dwc2);
   for (uint8_t ch_id = 0; ch_id < max_channel; ch_id++) {
     hcd_xfer_t* xfer = &_hcd_data.xfer[ch_id];
     if (!xfer->allocated) {
@@ -208,7 +211,7 @@ TU_ATTR_ALWAYS_INLINE static inline bool channel_send_in_token(const dwc2_regs_t
 
 // Find currently enabled channel. Note: EP0 is bidirectional
 TU_ATTR_ALWAYS_INLINE static inline uint8_t channel_find_enabled(dwc2_regs_t* dwc2, uint8_t dev_addr, uint8_t ep_num, uint8_t ep_dir) {
-  const uint8_t max_channel = DWC2_CHANNEL_COUNT(dwc2);
+  const uint8_t max_channel = dwc2_channel_count(dwc2);
   for (uint8_t ch_id = 0; ch_id < max_channel; ch_id++) {
     if (_hcd_data.xfer[ch_id].allocated) {
       const dwc2_channel_char_t hcchar = {.value = dwc2->channel[ch_id].hcchar};
@@ -813,7 +816,7 @@ static bool handle_txfifo_empty(dwc2_regs_t* dwc2, bool is_periodic) {
   // Use period txsts for both p/np to get request queue space available (1-bit difference, it is small enough)
   const dwc2_hptxsts_t txsts = {.value = (is_periodic ? dwc2->hptxsts : dwc2->hnptxsts)};
 
-  const uint8_t max_channel = DWC2_CHANNEL_COUNT(dwc2);
+  const uint8_t max_channel = dwc2_channel_count(dwc2);
   for (uint8_t ch_id = 0; ch_id < max_channel; ch_id++) {
     dwc2_channel_t* channel = &dwc2->channel[ch_id];
     const dwc2_channel_char_t hcchar = {.value = channel->hcchar};
@@ -1168,7 +1171,7 @@ static bool handle_channel_out_dma(dwc2_regs_t* dwc2, uint8_t ch_id, uint32_t hc
 static void handle_channel_irq(uint8_t rhport, bool in_isr) {
   dwc2_regs_t* dwc2 = DWC2_REG(rhport);
   const bool is_dma = dma_host_enabled(dwc2);
-  const uint8_t max_channel = DWC2_CHANNEL_COUNT(dwc2);
+  const uint8_t max_channel = dwc2_channel_count(dwc2);
 
   for (uint8_t ch_id = 0; ch_id < max_channel; ch_id++) {
     if (tu_bit_test(dwc2->haint, ch_id)) {