rename CFG_TUD_DWC2_DMA to CFG_TUD_DWC2_DMA_ENABLE

src/common/tusb_mcu.h

@@ -538,7 +538,7 @@
   #define TUP_DCD_EDPT_ISO_ALLOC
 #endif
 
-#if defined(TUP_USBIP_DWC2) // && CFG_TUD_DWC2_DMA == 0
+#if defined(TUP_USBIP_DWC2) // && CFG_TUD_DWC2_DMA_ENABLE == 0
   #define TUP_MEM_CONST_ADDR
 #endif
 

src/portable/synopsys/dwc2/dcd_dwc2.c

@@ -71,7 +71,7 @@ static bool _sof_en;
 TU_ATTR_ALWAYS_INLINE static inline bool dma_device_enabled(const dwc2_regs_t* dwc2) {
   (void) dwc2;
   // Internal DMA only
-  return CFG_TUD_DWC2_DMA && dwc2->ghwcfg2_bm.arch == GHWCFG2_ARCH_INTERNAL_DMA;
+  return CFG_TUD_DWC2_DMA_ENABLE && dwc2->ghwcfg2_bm.arch == GHWCFG2_ARCH_INTERNAL_DMA;
 }
 
 static void dma_setup_prepare(uint8_t rhport) {
@@ -897,8 +897,6 @@ static void handle_epin_irq(uint8_t rhport) {
   Note: when OTG_MULTI_PROC_INTRPT = 1, Device Each endpoint interrupt deachint/deachmsk/diepeachmsk/doepeachmsk
   are combined to generate dedicated interrupt line for each endpoint.
  */
-
-
 void dcd_int_handler(uint8_t rhport) {
   dwc2_regs_t* dwc2 = DWC2_REG(rhport);
 

src/tusb_option.h

@@ -252,8 +252,8 @@
 // (defined by CFG_TUSB_MEM_SECTION) must be declared as non-cacheable.
 // For example, on Cortex-M7 the MPU region can be configured as normal
 // non-cacheable, with RASR register value: TEX=1 C=0 B=0 S=0.
-#ifndef CFG_TUD_DWC2_DMA
-  #define CFG_TUD_DWC2_DMA 0
+#ifndef CFG_TUD_DWC2_DMA_ENABLE
+  #define CFG_TUD_DWC2_DMA_ENABLE 0
 #endif
 
 // Enable DWC2 Slave mode for host