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rename CFG_TUD_DWC2_DMA to CFG_TUD_DWC2_DMA_ENABLE

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This commit is contained in:
hathach
2024-11-14 13:26:11 +07:00
parent 0569188aed
commit daef846aa7
4 changed files with 8 additions and 10 deletions
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2
src/common/tusb_mcu.h
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@@ -538,7 +538,7 @@
#define TUP_DCD_EDPT_ISO_ALLOC #define TUP_DCD_EDPT_ISO_ALLOC
#endif #endif
#if defined(TUP_USBIP_DWC2) // && CFG_TUD_DWC2_DMA == 0 #if defined(TUP_USBIP_DWC2) // && CFG_TUD_DWC2_DMA_ENABLE == 0
#define TUP_MEM_CONST_ADDR #define TUP_MEM_CONST_ADDR
#endif #endif

4
src/portable/synopsys/dwc2/dcd_dwc2.c
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@@ -71,7 +71,7 @@ static bool _sof_en;
TU_ATTR_ALWAYS_INLINE static inline bool dma_device_enabled(const dwc2_regs_t* dwc2) { TU_ATTR_ALWAYS_INLINE static inline bool dma_device_enabled(const dwc2_regs_t* dwc2) {
(void) dwc2; (void) dwc2;
// Internal DMA only // Internal DMA only
return CFG_TUD_DWC2_DMA && dwc2->ghwcfg2_bm.arch == GHWCFG2_ARCH_INTERNAL_DMA; return CFG_TUD_DWC2_DMA_ENABLE && dwc2->ghwcfg2_bm.arch == GHWCFG2_ARCH_INTERNAL_DMA;
} }
static void dma_setup_prepare(uint8_t rhport) { static void dma_setup_prepare(uint8_t rhport) {
@@ -897,8 +897,6 @@ static void handle_epin_irq(uint8_t rhport) {
Note: when OTG_MULTI_PROC_INTRPT = 1, Device Each endpoint interrupt deachint/deachmsk/diepeachmsk/doepeachmsk Note: when OTG_MULTI_PROC_INTRPT = 1, Device Each endpoint interrupt deachint/deachmsk/diepeachmsk/doepeachmsk
are combined to generate dedicated interrupt line for each endpoint. are combined to generate dedicated interrupt line for each endpoint.
*/ */
void dcd_int_handler(uint8_t rhport) { void dcd_int_handler(uint8_t rhport) {
dwc2_regs_t* dwc2 = DWC2_REG(rhport); dwc2_regs_t* dwc2 = DWC2_REG(rhport);

4
src/tusb_option.h
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@@ -252,8 +252,8 @@
// (defined by CFG_TUSB_MEM_SECTION) must be declared as non-cacheable. // (defined by CFG_TUSB_MEM_SECTION) must be declared as non-cacheable.
// For example, on Cortex-M7 the MPU region can be configured as normal // For example, on Cortex-M7 the MPU region can be configured as normal
// non-cacheable, with RASR register value: TEX=1 C=0 B=0 S=0. // non-cacheable, with RASR register value: TEX=1 C=0 B=0 S=0.
#ifndef CFG_TUD_DWC2_DMA #ifndef CFG_TUD_DWC2_DMA_ENABLE
#define CFG_TUD_DWC2_DMA 0 #define CFG_TUD_DWC2_DMA_ENABLE 0
#endif #endif
// Enable DWC2 Slave mode for host // Enable DWC2 Slave mode for host

8
test/hil/tinyusb.json
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@@ -17,7 +17,7 @@
"name": "espressif_s3_devkitm", "name": "espressif_s3_devkitm",
"uid": "84F703C084E4", "uid": "84F703C084E4",
"build" : { "build" : {
"flags_on": ["", "CFG_TUD_DWC2_DMA"] "flags_on": ["", "CFG_TUD_DWC2_DMA_ENABLE"]
}, },
"tests": { "tests": {
"only": ["device/cdc_msc_freertos", "device/hid_composite_freertos"] "only": ["device/cdc_msc_freertos", "device/hid_composite_freertos"]
@@ -130,7 +130,7 @@
"name": "stm32f723disco", "name": "stm32f723disco",
"uid": "460029001951373031313335", "uid": "460029001951373031313335",
"build" : { "build" : {
"flags_on": ["", "CFG_TUD_DWC2_DMA"] "flags_on": ["", "CFG_TUD_DWC2_DMA_ENABLE"]
}, },
"tests": { "tests": {
"device": true, "host": true, "dual": false, "device": true, "host": true, "dual": false,
@@ -146,7 +146,7 @@
"name": "stm32h743nucleo", "name": "stm32h743nucleo",
"uid": "110018000951383432343236", "uid": "110018000951383432343236",
"build" : { "build" : {
"flags_on": ["", "CFG_TUD_DWC2_DMA"] "flags_on": ["", "CFG_TUD_DWC2_DMA_ENABLE"]
}, },
"tests": { "tests": {
"device": true, "host": false, "dual": false "device": true, "host": false, "dual": false
@@ -175,7 +175,7 @@
"name": "stm32f769disco", "name": "stm32f769disco",
"uid": "21002F000F51363531383437", "uid": "21002F000F51363531383437",
"build" : { "build" : {
"flags_on": ["", "CFG_TUD_DWC2_DMA"] "flags_on": ["", "CFG_TUD_DWC2_DMA_ENABLE"]
}, },
"tests": { "tests": {
"device": true, "host": false, "dual": false "device": true, "host": false, "dual": false