clean up ehci, support only 1 controller
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		@@ -209,8 +209,8 @@ static bool ehci_init(uint8_t hostid)
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  for(uint32_t i=0; i<4; i++)
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  {
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    ehci_data.period_head_arr[ hostid_to_data_idx(hostid) ][i].interrupt_smask    = 1; // queue head in period list must have smask non-zero
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    ehci_data.period_head_arr[ hostid_to_data_idx(hostid) ][i].qtd_overlay.halted = 1; // dummy node, always inactive
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    ehci_data.period_head_arr[i].interrupt_smask    = 1; // queue head in period list must have smask non-zero
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    ehci_data.period_head_arr[i].qtd_overlay.halted = 1; // dummy node, always inactive
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  }
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  ehci_link_t * const framelist  = get_period_frame_list(hostid);
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@@ -873,27 +873,16 @@ static inline ehci_link_t* get_period_frame_list(uint8_t hostid)
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}
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#endif
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static inline uint8_t hostid_to_data_idx(uint8_t hostid)
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{
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  #if (CONTROLLER_HOST_NUMBER == 1) && (CFG_TUSB_RHPORT1_MODE & OPT_MODE_HOST)
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    (void) hostid;
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    return 0;
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  #else
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    return hostid;
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  #endif
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}
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//------------- queue head helper -------------//
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static inline ehci_qhd_t* get_async_head(uint8_t hostid)
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{
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  return &ehci_data.async_head[ hostid_to_data_idx(hostid) ];
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  return &ehci_data.async_head;
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}
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#if EHCI_PERIODIC_LIST // TODO refractor/group this together
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static inline ehci_link_t* get_period_head(uint8_t hostid, uint8_t interval_ms)
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{
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  return (ehci_link_t*) (&ehci_data.period_head_arr[ hostid_to_data_idx(hostid) ]
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                                                    [ tu_log2( tu_min8(EHCI_FRAMELIST_SIZE, interval_ms) ) ] );
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  return (ehci_link_t*) &ehci_data.period_head_arr[ tu_log2( tu_min8(EHCI_FRAMELIST_SIZE, interval_ms) ) ];
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}
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#endif
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@@ -450,12 +450,12 @@ typedef volatile struct {
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//--------------------------------------------------------------------+
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typedef struct {
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  //------------- Static Async/Period List Head, Each for one controller -------------//
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  ehci_qhd_t async_head[CONTROLLER_HOST_NUMBER]; /// head qhd of async list, also is used as control endpoint for address 0
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  ehci_qhd_t async_head; /// head qhd of async list, also is used as control endpoint for address 0
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#if EHCI_PERIODIC_LIST
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  // for NXP ECHI, only implement 1 ms & 2 ms & 4 ms, 8 ms (framelist)
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  // [0] : 1ms, [1] : 2ms, [2] : 4ms, [3] : 8 ms
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  ehci_qhd_t period_head_arr[CONTROLLER_HOST_NUMBER][4];
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  ehci_qhd_t period_head_arr[4];
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#endif
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  //------------- Data for Address 0 (use async head as its queue head) -------------//
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