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revert board flash latency to 8

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hathach
2023-06-07 00:14:22 +07:00
parent 23f7130ae4
commit e02eee7477
2 changed files with 3 additions and 4 deletions
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2
hw/bsp/stm32g4/boards/b_g474e_dpow1/board.h
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@@ -87,7 +87,7 @@ static inline void board_clock_init(void)
RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4); HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_8);
//------------- HSI48 and CRS for USB -------------// //------------- HSI48 and CRS for USB -------------//
RCC_OscInitTypeDef osc_hsi48 = {0}; RCC_OscInitTypeDef osc_hsi48 = {0};

5
hw/bsp/stm32g4/family.c
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@@ -62,8 +62,7 @@ void usbpd_init(uint8_t port_num, tusb_typec_port_type_t port_type) {
} }
// Enable interrupt // Enable interrupt
//NVIC_SetPriority(UCPD1_IRQn, 0); NVIC_EnableIRQ(UCPD1_IRQn);
// NVIC_EnableIRQ(UCPD1_IRQn);
} }
uint8_t pd_rx_buf[262]; uint8_t pd_rx_buf[262];
@@ -253,7 +252,7 @@ void board_init(void)
board_vbus_sense_init(); board_vbus_sense_init();
#if 0 #if 1
// USB PD // USB PD
/* PWR register access (for disabling dead battery feature) */ /* PWR register access (for disabling dead battery feature) */
LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_PWR); LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_PWR);