rename VERIFY to TU_VERIFY to avoid conflict with application
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		@@ -104,7 +104,7 @@ typedef struct ATTR_PACKED
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  volatile uint16_t active      : 1  ; ///< The buffer is enabled. HW can use the buffer to store received OUT data or to transmit data on the IN endpoint. Software can only set this bit to ‘1’. As long as this bit is set to one, software is not allowed to update any of the values in this 32-bit word. In case software wants to deactivate the buffer, it must write a one to the corresponding “skip” bit in the USB Endpoint skip register. Hardware can only write this bit to zero. It will do this when it receives a short packet or when the NBytes field transitions to zero or when software has written a one to the “skip” bit.
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}dcd_11u_13u_qhd_t;
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VERIFY_STATIC( sizeof(dcd_11u_13u_qhd_t) == 4, "size is not correct" );
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TU_VERIFY_STATIC( sizeof(dcd_11u_13u_qhd_t) == 4, "size is not correct" );
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// NOTE data will be transferred as soon as dcd get request by dcd_pipe(_queue)_xfer using double buffering.
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// If there is another dcd_edpt_xfer request, the new request will be saved and executed when the first is done.
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@@ -384,7 +384,7 @@ bool dcd_control_xfer(uint8_t rhport, tusb_dir_t dir, uint8_t * p_buffer, uint16
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{
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  (void) rhport;
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  VERIFY( !(length != 0 && p_buffer == NULL) );
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  TU_VERIFY( !(length != 0 && p_buffer == NULL) );
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  // determine Endpoint where Data & Status phase occurred (IN or OUT)
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  uint8_t const ep_data   = (dir == TUSB_DIR_IN) ? 1 : 0;
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@@ -399,13 +399,13 @@ bool dcd_control_xfer(uint8_t rhport, tusb_dir_t dir, uint8_t * p_buffer, uint16
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    dcd_data.control_dma.remaining_bytes = length;
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    // lpc17xx already received the first DATA OUT packet by now
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    VERIFY_ERR ( pipe_control_xfer(ep_data, p_buffer, length), false );
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    TU_VERIFY_ERR ( pipe_control_xfer(ep_data, p_buffer, length), false );
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  }
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  //------------- Status Phase (opposite direct to Data) -------------//
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  if (dir == TUSB_DIR_OUT)
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  { // only write for CONTROL OUT, CONTROL IN data will be retrieved in hal_dcd_isr // TODO ????
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    VERIFY_ERR ( pipe_control_write(NULL, 0), false );
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    TU_VERIFY_ERR ( pipe_control_write(NULL, 0), false );
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  }
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  return true;
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@@ -80,7 +80,7 @@ typedef struct ATTR_ALIGNED(4)
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//	uint32_t iso_packet_size_addr;		// iso only, can be omitted for non-iso
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}dcd_dma_descriptor_t;
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VERIFY_STATIC( sizeof(dcd_dma_descriptor_t) == 16, "size is not correct"); // TODO not support ISO for now
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TU_VERIFY_STATIC( sizeof(dcd_dma_descriptor_t) == 16, "size is not correct"); // TODO not support ISO for now
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//--------------------------------------------------------------------+
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@@ -244,7 +244,7 @@ bool dcd_control_xfer(uint8_t rhport, tusb_dir_t dir, uint8_t * p_buffer, uint16
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  // wait until ENDPTSETUPSTAT before priming data/status in response TODO add time out
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  while(lpc_usb->ENDPTSETUPSTAT & BIT_(0)) {}
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  VERIFY( !qhd->qtd_overlay.active );
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  TU_VERIFY( !qhd->qtd_overlay.active );
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  dcd_qtd_t* qtd = &p_dcd->qtd[0];
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  qtd_init(qtd, p_buffer, length);
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@@ -295,7 +295,7 @@ bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const * p_endpoint_desc)
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{
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  // TODO USB1 only has 4 non-control enpoint (USB0 has 5)
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  // TODO not support ISO yet
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  VERIFY ( p_endpoint_desc->bmAttributes.xfer != TUSB_XFER_ISOCHRONOUS);
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  TU_VERIFY ( p_endpoint_desc->bmAttributes.xfer != TUSB_XFER_ISOCHRONOUS);
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  tusb_dir_t dir = (p_endpoint_desc->bEndpointAddress & TUSB_DIR_IN_MASK) ? TUSB_DIR_IN : TUSB_DIR_OUT;
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@@ -313,7 +313,7 @@ bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const * p_endpoint_desc)
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  volatile uint32_t * reg_control = get_reg_control_addr(rhport, ep_idx);
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  // endpoint must not be already enabled
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  VERIFY( !( (*reg_control) &  (ENDPTCTRL_MASK_ENABLE << (dir ? 16 : 0)) ) );
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  TU_VERIFY( !( (*reg_control) &  (ENDPTCTRL_MASK_ENABLE << (dir ? 16 : 0)) ) );
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  (*reg_control) |= ((p_endpoint_desc->bmAttributes.xfer << 2) | ENDPTCTRL_MASK_ENABLE | ENDPTCTRL_MASK_TOGGLE_RESET) << (dir ? 16 : 0);
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@@ -363,7 +363,7 @@ bool  dcd_edpt_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t * buffer, uint16_t
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{
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  uint8_t ep_idx = edpt_addr2phy(ep_addr);
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  VERIFY ( pipe_add_xfer(rhport, ep_idx, buffer, total_bytes, true) );
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  TU_VERIFY ( pipe_add_xfer(rhport, ep_idx, buffer, total_bytes, true) );
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  dcd_qhd_t* p_qhd = &dcd_data_ptr[rhport]->qhd[ ep_idx ];
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  dcd_qtd_t* p_qtd = &dcd_data_ptr[rhport]->qtd[ p_qhd->list_qtd_idx[0] ];
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@@ -122,7 +122,7 @@ typedef struct
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  uint8_t reserved;
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} dcd_qtd_t;
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VERIFY_STATIC( sizeof(dcd_qtd_t) == 32, "size is not correct");
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TU_VERIFY_STATIC( sizeof(dcd_qtd_t) == 32, "size is not correct");
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typedef struct
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{
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@@ -153,7 +153,7 @@ typedef struct
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	uint8_t reserved[16-DCD_QTD_PER_QHD_MAX];
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}  dcd_qhd_t;
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VERIFY_STATIC( sizeof(dcd_qhd_t) == 64, "size is not correct");
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TU_VERIFY_STATIC( sizeof(dcd_qhd_t) == 64, "size is not correct");
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#ifdef __cplusplus
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@@ -86,7 +86,7 @@ bool tusb_hal_init(void)
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  //------------- USB0 -------------//
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#if CFG_TUSB_RHPORT0_MODE
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  CGU_EnableEntity(CGU_CLKSRC_PLL0, DISABLE); /* Disable PLL first */
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  VERIFY( CGU_ERROR_SUCCESS == CGU_SetPLL0()); /* the usb core require output clock = 480MHz */
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  TU_VERIFY( CGU_ERROR_SUCCESS == CGU_SetPLL0()); /* the usb core require output clock = 480MHz */
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  CGU_EntityConnect(CGU_CLKSRC_XTAL_OSC, CGU_CLKSRC_PLL0);
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  CGU_EnableEntity(CGU_CLKSRC_PLL0, ENABLE);   /* Enable PLL after all setting is done */
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