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clean up

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This commit is contained in:
hathach
2025-07-31 23:26:27 +07:00
parent b67e00892c
commit e0f2343954
3 changed files with 117 additions and 139 deletions
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148
src/portable/st/stm32_fsdev/fsdev_at32.h
View File

@@ -35,82 +35,6 @@
#endif
//#include "fsdev_common.h"
//--------------------------------------------------------------------+
//
//--------------------------------------------------------------------+
#if (CFG_TUSB_MCU == OPT_MCU_AT32F403A_407) || (CFG_TUSB_MCU == OPT_MCU_AT32F413)
static const IRQn_Type fsdev_irq[] = {
USBFS_H_CAN1_TX_IRQn,
USBFS_L_CAN1_RX0_IRQn,
USBFSWakeUp_IRQn
};
enum { FSDEV_IRQ_NUM = TU_ARRAY_SIZE(fsdev_irq) };
#else
#error "Unsupported MCU"
#endif
void dcd_int_enable(uint8_t rhport) {
(void)rhport;
#if (CFG_TUSB_MCU == OPT_MCU_AT32F403A_407) || (CFG_TUSB_MCU == OPT_MCU_AT32F413)
// AT32F403A/407 devices allow to remap the USB interrupt vectors from
// shared USB/CAN IRQs to separate CAN and USB IRQs.
// This dynamically checks if this remap is active to enable the right IRQs.
if (CRM->intmap_bit.usbintmap) {
NVIC_DisableIRQ(USBFS_MAPH_IRQn);
NVIC_DisableIRQ(USBFS_MAPL_IRQn);
NVIC_DisableIRQ(USBFSWakeUp_IRQn);
} else
#endif
{
for(uint8_t i=0; i < FSDEV_IRQ_NUM; i++) {
NVIC_EnableIRQ(fsdev_irq[i]);
}
}
}
void dcd_int_disable(uint8_t rhport) {
(void)rhport;
#if (CFG_TUSB_MCU == OPT_MCU_AT32F403A_407) || (CFG_TUSB_MCU == OPT_MCU_AT32F413)
// AT32F403A/407 devices allow to remap the USB interrupt vectors from
// shared USB/CAN IRQs to separate CAN and USB IRQs.
// This dynamically checks if this remap is active to enable the right IRQs.
if (CRM->intmap_bit.usbintmap) {
NVIC_DisableIRQ(USBFS_MAPH_IRQn);
NVIC_DisableIRQ(USBFS_MAPL_IRQn);
NVIC_DisableIRQ(USBFSWakeUp_IRQn);
} else
#endif
{
for(uint8_t i=0; i < FSDEV_IRQ_NUM; i++) {
NVIC_DisableIRQ(fsdev_irq[i]);
}
}
}
void dcd_disconnect(uint8_t rhport) {
(void) rhport;
/* disable usb phy */
//USB->ctrl_bit.disusb = TRUE;
*(int *)(0x40000000+0x5C00+0x40) |= (1<<1);
*(int *)(0x40000000+0x5C00+0x60) |= (1<<1);
/* D+ 1.5k pull-up disable */
//USB->cfg_bit.puo = TRUE;
}
void dcd_connect(uint8_t rhport) {
(void) rhport;
/* enable usb phy */
//USB->ctrl_bit.disusb = 0;
*(int *)(0x40000000+0x5C00+0x40) &= ~(1<<1);
*(int *)(0x40000000+0x5C00+0x60) &= ~(1<<1);
/* Dp 1.5k pull-up enable */
//USB->cfg_bit.puo = 0;
}
#define FSDEV_PMA_SIZE (512u)
#define FSDEV_REG_BASE (APB1PERIPH_BASE + 0x00005C00UL)
#define FSDEV_PMA_BASE (APB1PERIPH_BASE + 0x00006000UL)
@@ -221,4 +145,76 @@ void dcd_connect(uint8_t rhport) {
#define USB_EPRX_DTOG2 ((uint16_t)0x2000U) /*!< EndPoint RX Data TOGgle bit1 */
#define USB_EPRX_DTOGMASK (USB_EPRX_STAT|USB_EPREG_MASK)
#include "fsdev_type.h"
//--------------------------------------------------------------------+
//
//--------------------------------------------------------------------+
#if (CFG_TUSB_MCU == OPT_MCU_AT32F403A_407) || (CFG_TUSB_MCU == OPT_MCU_AT32F413)
static const IRQn_Type fsdev_irq[] = {
USBFS_H_CAN1_TX_IRQn,
USBFS_L_CAN1_RX0_IRQn,
USBFSWakeUp_IRQn
};
enum { FSDEV_IRQ_NUM = TU_ARRAY_SIZE(fsdev_irq) };
#else
#error "Unsupported MCU"
#endif
void dcd_int_enable(uint8_t rhport) {
(void)rhport;
#if (CFG_TUSB_MCU == OPT_MCU_AT32F403A_407) || (CFG_TUSB_MCU == OPT_MCU_AT32F413)
// AT32F403A/407 devices allow to remap the USB interrupt vectors from
// shared USB/CAN IRQs to separate CAN and USB IRQs.
// This dynamically checks if this remap is active to enable the right IRQs.
if (CRM->intmap_bit.usbintmap) {
NVIC_DisableIRQ(USBFS_MAPH_IRQn);
NVIC_DisableIRQ(USBFS_MAPL_IRQn);
NVIC_DisableIRQ(USBFSWakeUp_IRQn);
} else
#endif
{
for(uint8_t i=0; i < FSDEV_IRQ_NUM; i++) {
NVIC_EnableIRQ(fsdev_irq[i]);
}
}
}
void dcd_int_disable(uint8_t rhport) {
(void)rhport;
#if (CFG_TUSB_MCU == OPT_MCU_AT32F403A_407) || (CFG_TUSB_MCU == OPT_MCU_AT32F413)
// AT32F403A/407 devices allow to remap the USB interrupt vectors from
// shared USB/CAN IRQs to separate CAN and USB IRQs.
// This dynamically checks if this remap is active to enable the right IRQs.
if (CRM->intmap_bit.usbintmap) {
NVIC_DisableIRQ(USBFS_MAPH_IRQn);
NVIC_DisableIRQ(USBFS_MAPL_IRQn);
NVIC_DisableIRQ(USBFSWakeUp_IRQn);
} else
#endif
{
for(uint8_t i=0; i < FSDEV_IRQ_NUM; i++) {
NVIC_DisableIRQ(fsdev_irq[i]);
}
}
}
void dcd_disconnect(uint8_t rhport) {
(void) rhport;
/* disable usb phy */
FSDEV_REG->CNTR |= USB_CNTR_PDWN;
/* D+ 1.5k pull-up disable, USB->cfg_bit.puo = TRUE; */
*(uint32_t *)(FSDEV_REG_BASE+0x60) |= (1u<<1);
}
void dcd_connect(uint8_t rhport) {
(void) rhport;
/* enable usb phy */
FSDEV_REG->CNTR &= ~USB_CNTR_PDWN;
/* Dp 1.5k pull-up enable, USB->cfg_bit.puo = 0; */
*(uint32_t *)(FSDEV_REG_BASE+0x60) &= ~(1u<<1);
}
#endif

92
src/portable/synopsys/dwc2/dwc2_at32.h
View File

@@ -67,66 +67,52 @@
extern "C" {
#endif
static const dwc2_controller_t _dwc2_controller[] =
{
{ .reg_base = DWC2_OTG1_REG_BASE, .irqnum = OTG1_IRQn, .ep_count = DWC2_EP_MAX, .ep_fifo_size = OTG1_FIFO_SIZE },
#if defined DWC2_OTG2_REG_BASE
{ .reg_base = DWC2_OTG2_REG_BASE, .irqnum = OTG2_IRQn, .ep_count = DWC2_EP_MAX, .ep_fifo_size = OTG2_FIFO_SIZE }
#endif
};
static const dwc2_controller_t _dwc2_controller[] = {
{.reg_base = DWC2_OTG1_REG_BASE, .irqnum = OTG1_IRQn, .ep_count = DWC2_EP_MAX, .ep_fifo_size = OTG1_FIFO_SIZE},
#if defined DWC2_OTG2_REG_BASE
{.reg_base = DWC2_OTG2_REG_BASE, .irqnum = OTG2_IRQn, .ep_count = DWC2_EP_MAX, .ep_fifo_size = OTG2_FIFO_SIZE}
#endif
};
TU_ATTR_ALWAYS_INLINE static inline void dwc2_int_set(uint8_t rhport, tusb_role_t role, bool enabled) {
(void) role;
const IRQn_Type irqn = (IRQn_Type) _dwc2_controller[rhport].irqnum;
if (enabled) {
NVIC_EnableIRQ(irqn);
} else {
NVIC_DisableIRQ(irqn);
}
}
TU_ATTR_ALWAYS_INLINE static inline void dwc2_int_set(uint8_t rhport, tusb_role_t role, bool enabled) {
(void) role;
const IRQn_Type irqn = (IRQn_Type) _dwc2_controller[rhport].irqnum;
if (enabled) {
NVIC_EnableIRQ(irqn);
} else {
NVIC_DisableIRQ(irqn);
}
}
TU_ATTR_ALWAYS_INLINE
static inline void dwc2_dcd_int_enable(uint8_t rhport)
{
NVIC_EnableIRQ(_dwc2_controller[rhport].irqnum);
}
TU_ATTR_ALWAYS_INLINE static inline void dwc2_dcd_int_enable(uint8_t rhport) { NVIC_EnableIRQ(_dwc2_controller[rhport].irqnum);
}
TU_ATTR_ALWAYS_INLINE
static inline void dwc2_dcd_int_disable (uint8_t rhport)
{
NVIC_DisableIRQ(_dwc2_controller[rhport].irqnum);
}
TU_ATTR_ALWAYS_INLINE static inline void dwc2_dcd_int_disable(uint8_t rhport) {
NVIC_DisableIRQ(_dwc2_controller[rhport].irqnum);
}
static inline void dwc2_remote_wakeup_delay(void)
{
// try to delay for 1 ms
uint32_t count = system_core_clock / 1000;
while ( count-- ) __asm volatile ("nop");
}
TU_ATTR_ALWAYS_INLINE static inline void dwc2_remote_wakeup_delay(void) {
// try to delay for 1 ms
uint32_t count = system_core_clock / 1000;
while (count--) __asm volatile("nop");
}
// MCU specific PHY init, called BEFORE core reset
static inline void dwc2_phy_init(dwc2_regs_t * dwc2, uint8_t hs_phy_type)
{
(void) dwc2;
// Enable on-chip HS PHY
if (hs_phy_type == GHWCFG2_HSPHY_UTMI || hs_phy_type == GHWCFG2_HSPHY_UTMI_ULPI)
{
// MCU specific PHY init, called BEFORE core reset
TU_ATTR_ALWAYS_INLINE static inline void dwc2_phy_init(dwc2_regs_t *dwc2, uint8_t hs_phy_type) {
(void) dwc2;
// Enable on-chip HS PHY
if (hs_phy_type == GHWCFG2_HSPHY_UTMI || hs_phy_type == GHWCFG2_HSPHY_UTMI_ULPI) {
} else if (hs_phy_type == GHWCFG2_HSPHY_NOT_SUPPORTED) {
}
}
}
else if(hs_phy_type == GHWCFG2_HSPHY_NOT_SUPPORTED)
{
// MCU specific PHY update, it is called AFTER init() and core reset
TU_ATTR_ALWAYS_INLINE static inline void dwc2_phy_update(dwc2_regs_t *dwc2, uint8_t hs_phy_type) {
(void) dwc2;
(void) hs_phy_type;
}
}
// MCU specific PHY update, it is called AFTER init() and core reset
static inline void dwc2_phy_update(dwc2_regs_t * dwc2, uint8_t hs_phy_type)
{
(void) dwc2;
(void) hs_phy_type;
dwc2->stm32_gccfg |= STM32_GCCFG_PWRDWN | STM32_GCCFG_DCDEN | STM32_GCCFG_PDEN;
}
dwc2->stm32_gccfg |= STM32_GCCFG_PWRDWN | STM32_GCCFG_DCDEN | STM32_GCCFG_PDEN;
}
#ifdef __cplusplus
}

16
src/portable/synopsys/dwc2/dwc2_common.c
View File

@@ -120,13 +120,9 @@ static void phy_hs_init(dwc2_regs_t* dwc2) {
// Set 16-bit interface if supported
if (ghwcfg4.phy_data_width) {
#if CFG_TUSB_MCU != OPT_MCU_AT32F402_405 // at32f402_405 does not actually support 16-bit
gusbcfg |= GUSBCFG_PHYIF16; // 16 bit
/* at32f402_405 does not actually support 16-bit */
#if CFG_TUSB_MCU == OPT_MCU_AT32F402_405
gusbcfg &= ~GUSBCFG_PHYIF16; // 8 bit
#endif
} else {
gusbcfg &= ~GUSBCFG_PHYIF16; // 8 bit
}
@@ -145,12 +141,12 @@ static void phy_hs_init(dwc2_regs_t* dwc2) {
// - 9 if using 8-bit PHY interface
// - 5 if using 16-bit PHY interface
gusbcfg &= ~GUSBCFG_TRDT_Msk;
gusbcfg |= (dwc2->ghwcfg4_bm.phy_data_width ? 5u : 9u) << GUSBCFG_TRDT_Pos;
/* at32f402_405 does not actually support 16-bit */
#if CFG_TUSB_MCU == OPT_MCU_AT32F402_405
gusbcfg |= (dwc2->ghwcfg4_bm.phy_data_width ? 9u : 9u) << GUSBCFG_TRDT_Pos;
#endif
#if CFG_TUSB_MCU == OPT_MCU_AT32F402_405 // at32f402_405 does not actually support 16-bit
gusbcfg |= 9u << GUSBCFG_TRDT_Pos;
#else
gusbcfg |= (dwc2->ghwcfg4_bm.phy_data_width ? 5u : 9u) << GUSBCFG_TRDT_Pos;
#endif
dwc2->gusbcfg = gusbcfg;