clean up
This commit is contained in:
@@ -35,82 +35,6 @@
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#endif
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#endif
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//#include "fsdev_common.h"
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//--------------------------------------------------------------------+
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//
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//--------------------------------------------------------------------+
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#if (CFG_TUSB_MCU == OPT_MCU_AT32F403A_407) || (CFG_TUSB_MCU == OPT_MCU_AT32F413)
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static const IRQn_Type fsdev_irq[] = {
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USBFS_H_CAN1_TX_IRQn,
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USBFS_L_CAN1_RX0_IRQn,
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USBFSWakeUp_IRQn
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};
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enum { FSDEV_IRQ_NUM = TU_ARRAY_SIZE(fsdev_irq) };
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#else
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#error "Unsupported MCU"
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#endif
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void dcd_int_enable(uint8_t rhport) {
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(void)rhport;
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#if (CFG_TUSB_MCU == OPT_MCU_AT32F403A_407) || (CFG_TUSB_MCU == OPT_MCU_AT32F413)
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// AT32F403A/407 devices allow to remap the USB interrupt vectors from
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// shared USB/CAN IRQs to separate CAN and USB IRQs.
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// This dynamically checks if this remap is active to enable the right IRQs.
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if (CRM->intmap_bit.usbintmap) {
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NVIC_DisableIRQ(USBFS_MAPH_IRQn);
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NVIC_DisableIRQ(USBFS_MAPL_IRQn);
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NVIC_DisableIRQ(USBFSWakeUp_IRQn);
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} else
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#endif
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{
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for(uint8_t i=0; i < FSDEV_IRQ_NUM; i++) {
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NVIC_EnableIRQ(fsdev_irq[i]);
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}
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}
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}
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void dcd_int_disable(uint8_t rhport) {
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(void)rhport;
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#if (CFG_TUSB_MCU == OPT_MCU_AT32F403A_407) || (CFG_TUSB_MCU == OPT_MCU_AT32F413)
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// AT32F403A/407 devices allow to remap the USB interrupt vectors from
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// shared USB/CAN IRQs to separate CAN and USB IRQs.
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// This dynamically checks if this remap is active to enable the right IRQs.
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if (CRM->intmap_bit.usbintmap) {
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NVIC_DisableIRQ(USBFS_MAPH_IRQn);
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NVIC_DisableIRQ(USBFS_MAPL_IRQn);
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NVIC_DisableIRQ(USBFSWakeUp_IRQn);
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} else
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#endif
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{
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for(uint8_t i=0; i < FSDEV_IRQ_NUM; i++) {
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NVIC_DisableIRQ(fsdev_irq[i]);
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}
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}
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}
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void dcd_disconnect(uint8_t rhport) {
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(void) rhport;
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/* disable usb phy */
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//USB->ctrl_bit.disusb = TRUE;
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*(int *)(0x40000000+0x5C00+0x40) |= (1<<1);
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*(int *)(0x40000000+0x5C00+0x60) |= (1<<1);
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/* D+ 1.5k pull-up disable */
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//USB->cfg_bit.puo = TRUE;
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}
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void dcd_connect(uint8_t rhport) {
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(void) rhport;
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/* enable usb phy */
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//USB->ctrl_bit.disusb = 0;
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*(int *)(0x40000000+0x5C00+0x40) &= ~(1<<1);
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*(int *)(0x40000000+0x5C00+0x60) &= ~(1<<1);
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/* Dp 1.5k pull-up enable */
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//USB->cfg_bit.puo = 0;
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}
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#define FSDEV_PMA_SIZE (512u)
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#define FSDEV_PMA_SIZE (512u)
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#define FSDEV_REG_BASE (APB1PERIPH_BASE + 0x00005C00UL)
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#define FSDEV_REG_BASE (APB1PERIPH_BASE + 0x00005C00UL)
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#define FSDEV_PMA_BASE (APB1PERIPH_BASE + 0x00006000UL)
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#define FSDEV_PMA_BASE (APB1PERIPH_BASE + 0x00006000UL)
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@@ -221,4 +145,76 @@ void dcd_connect(uint8_t rhport) {
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#define USB_EPRX_DTOG2 ((uint16_t)0x2000U) /*!< EndPoint RX Data TOGgle bit1 */
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#define USB_EPRX_DTOG2 ((uint16_t)0x2000U) /*!< EndPoint RX Data TOGgle bit1 */
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#define USB_EPRX_DTOGMASK (USB_EPRX_STAT|USB_EPREG_MASK)
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#define USB_EPRX_DTOGMASK (USB_EPRX_STAT|USB_EPREG_MASK)
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#include "fsdev_type.h"
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//--------------------------------------------------------------------+
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//
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//--------------------------------------------------------------------+
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#if (CFG_TUSB_MCU == OPT_MCU_AT32F403A_407) || (CFG_TUSB_MCU == OPT_MCU_AT32F413)
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static const IRQn_Type fsdev_irq[] = {
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USBFS_H_CAN1_TX_IRQn,
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USBFS_L_CAN1_RX0_IRQn,
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USBFSWakeUp_IRQn
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};
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enum { FSDEV_IRQ_NUM = TU_ARRAY_SIZE(fsdev_irq) };
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#else
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#error "Unsupported MCU"
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#endif
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void dcd_int_enable(uint8_t rhport) {
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(void)rhport;
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#if (CFG_TUSB_MCU == OPT_MCU_AT32F403A_407) || (CFG_TUSB_MCU == OPT_MCU_AT32F413)
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// AT32F403A/407 devices allow to remap the USB interrupt vectors from
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// shared USB/CAN IRQs to separate CAN and USB IRQs.
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// This dynamically checks if this remap is active to enable the right IRQs.
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if (CRM->intmap_bit.usbintmap) {
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NVIC_DisableIRQ(USBFS_MAPH_IRQn);
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NVIC_DisableIRQ(USBFS_MAPL_IRQn);
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NVIC_DisableIRQ(USBFSWakeUp_IRQn);
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} else
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#endif
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{
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for(uint8_t i=0; i < FSDEV_IRQ_NUM; i++) {
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NVIC_EnableIRQ(fsdev_irq[i]);
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}
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}
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}
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void dcd_int_disable(uint8_t rhport) {
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(void)rhport;
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#if (CFG_TUSB_MCU == OPT_MCU_AT32F403A_407) || (CFG_TUSB_MCU == OPT_MCU_AT32F413)
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// AT32F403A/407 devices allow to remap the USB interrupt vectors from
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// shared USB/CAN IRQs to separate CAN and USB IRQs.
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// This dynamically checks if this remap is active to enable the right IRQs.
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if (CRM->intmap_bit.usbintmap) {
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NVIC_DisableIRQ(USBFS_MAPH_IRQn);
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NVIC_DisableIRQ(USBFS_MAPL_IRQn);
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NVIC_DisableIRQ(USBFSWakeUp_IRQn);
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} else
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#endif
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{
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for(uint8_t i=0; i < FSDEV_IRQ_NUM; i++) {
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NVIC_DisableIRQ(fsdev_irq[i]);
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}
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}
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}
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void dcd_disconnect(uint8_t rhport) {
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(void) rhport;
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/* disable usb phy */
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FSDEV_REG->CNTR |= USB_CNTR_PDWN;
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/* D+ 1.5k pull-up disable, USB->cfg_bit.puo = TRUE; */
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*(uint32_t *)(FSDEV_REG_BASE+0x60) |= (1u<<1);
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}
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void dcd_connect(uint8_t rhport) {
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(void) rhport;
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/* enable usb phy */
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FSDEV_REG->CNTR &= ~USB_CNTR_PDWN;
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/* Dp 1.5k pull-up enable, USB->cfg_bit.puo = 0; */
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*(uint32_t *)(FSDEV_REG_BASE+0x60) &= ~(1u<<1);
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}
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#endif
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#endif
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@@ -67,15 +67,14 @@
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extern "C" {
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extern "C" {
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#endif
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#endif
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static const dwc2_controller_t _dwc2_controller[] =
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static const dwc2_controller_t _dwc2_controller[] = {
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{
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{.reg_base = DWC2_OTG1_REG_BASE, .irqnum = OTG1_IRQn, .ep_count = DWC2_EP_MAX, .ep_fifo_size = OTG1_FIFO_SIZE},
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{ .reg_base = DWC2_OTG1_REG_BASE, .irqnum = OTG1_IRQn, .ep_count = DWC2_EP_MAX, .ep_fifo_size = OTG1_FIFO_SIZE },
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#if defined DWC2_OTG2_REG_BASE
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#if defined DWC2_OTG2_REG_BASE
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{.reg_base = DWC2_OTG2_REG_BASE, .irqnum = OTG2_IRQn, .ep_count = DWC2_EP_MAX, .ep_fifo_size = OTG2_FIFO_SIZE}
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{ .reg_base = DWC2_OTG2_REG_BASE, .irqnum = OTG2_IRQn, .ep_count = DWC2_EP_MAX, .ep_fifo_size = OTG2_FIFO_SIZE }
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#endif
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#endif
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};
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};
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TU_ATTR_ALWAYS_INLINE static inline void dwc2_int_set(uint8_t rhport, tusb_role_t role, bool enabled) {
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TU_ATTR_ALWAYS_INLINE static inline void dwc2_int_set(uint8_t rhport, tusb_role_t role, bool enabled) {
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(void) role;
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(void) role;
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const IRQn_Type irqn = (IRQn_Type) _dwc2_controller[rhport].irqnum;
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const IRQn_Type irqn = (IRQn_Type) _dwc2_controller[rhport].irqnum;
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if (enabled) {
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if (enabled) {
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@@ -83,50 +82,37 @@ TU_ATTR_ALWAYS_INLINE static inline void dwc2_int_set(uint8_t rhport, tusb_role_
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} else {
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} else {
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NVIC_DisableIRQ(irqn);
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NVIC_DisableIRQ(irqn);
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}
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}
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}
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}
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TU_ATTR_ALWAYS_INLINE
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TU_ATTR_ALWAYS_INLINE static inline void dwc2_dcd_int_enable(uint8_t rhport) { NVIC_EnableIRQ(_dwc2_controller[rhport].irqnum);
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static inline void dwc2_dcd_int_enable(uint8_t rhport)
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}
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{
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NVIC_EnableIRQ(_dwc2_controller[rhport].irqnum);
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}
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TU_ATTR_ALWAYS_INLINE
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TU_ATTR_ALWAYS_INLINE static inline void dwc2_dcd_int_disable(uint8_t rhport) {
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static inline void dwc2_dcd_int_disable (uint8_t rhport)
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{
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NVIC_DisableIRQ(_dwc2_controller[rhport].irqnum);
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NVIC_DisableIRQ(_dwc2_controller[rhport].irqnum);
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}
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}
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static inline void dwc2_remote_wakeup_delay(void)
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TU_ATTR_ALWAYS_INLINE static inline void dwc2_remote_wakeup_delay(void) {
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{
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// try to delay for 1 ms
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// try to delay for 1 ms
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uint32_t count = system_core_clock / 1000;
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uint32_t count = system_core_clock / 1000;
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while ( count-- ) __asm volatile ("nop");
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while (count--) __asm volatile("nop");
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}
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}
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// MCU specific PHY init, called BEFORE core reset
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// MCU specific PHY init, called BEFORE core reset
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static inline void dwc2_phy_init(dwc2_regs_t * dwc2, uint8_t hs_phy_type)
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TU_ATTR_ALWAYS_INLINE static inline void dwc2_phy_init(dwc2_regs_t *dwc2, uint8_t hs_phy_type) {
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{
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(void) dwc2;
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(void) dwc2;
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// Enable on-chip HS PHY
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// Enable on-chip HS PHY
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if (hs_phy_type == GHWCFG2_HSPHY_UTMI || hs_phy_type == GHWCFG2_HSPHY_UTMI_ULPI)
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if (hs_phy_type == GHWCFG2_HSPHY_UTMI || hs_phy_type == GHWCFG2_HSPHY_UTMI_ULPI) {
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{
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} else if (hs_phy_type == GHWCFG2_HSPHY_NOT_SUPPORTED) {
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}
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}
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else if(hs_phy_type == GHWCFG2_HSPHY_NOT_SUPPORTED)
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{
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}
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}
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}
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// MCU specific PHY update, it is called AFTER init() and core reset
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// MCU specific PHY update, it is called AFTER init() and core reset
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static inline void dwc2_phy_update(dwc2_regs_t * dwc2, uint8_t hs_phy_type)
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TU_ATTR_ALWAYS_INLINE static inline void dwc2_phy_update(dwc2_regs_t *dwc2, uint8_t hs_phy_type) {
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{
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(void) dwc2;
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(void) dwc2;
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(void) hs_phy_type;
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(void) hs_phy_type;
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dwc2->stm32_gccfg |= STM32_GCCFG_PWRDWN | STM32_GCCFG_DCDEN | STM32_GCCFG_PDEN;
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dwc2->stm32_gccfg |= STM32_GCCFG_PWRDWN | STM32_GCCFG_DCDEN | STM32_GCCFG_PDEN;
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}
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}
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#ifdef __cplusplus
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#ifdef __cplusplus
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}
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}
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@@ -120,13 +120,9 @@ static void phy_hs_init(dwc2_regs_t* dwc2) {
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// Set 16-bit interface if supported
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// Set 16-bit interface if supported
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if (ghwcfg4.phy_data_width) {
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if (ghwcfg4.phy_data_width) {
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#if CFG_TUSB_MCU != OPT_MCU_AT32F402_405 // at32f402_405 does not actually support 16-bit
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gusbcfg |= GUSBCFG_PHYIF16; // 16 bit
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gusbcfg |= GUSBCFG_PHYIF16; // 16 bit
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/* at32f402_405 does not actually support 16-bit */
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#if CFG_TUSB_MCU == OPT_MCU_AT32F402_405
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gusbcfg &= ~GUSBCFG_PHYIF16; // 8 bit
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#endif
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#endif
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} else {
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} else {
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gusbcfg &= ~GUSBCFG_PHYIF16; // 8 bit
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gusbcfg &= ~GUSBCFG_PHYIF16; // 8 bit
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}
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}
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@@ -145,12 +141,12 @@ static void phy_hs_init(dwc2_regs_t* dwc2) {
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// - 9 if using 8-bit PHY interface
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// - 9 if using 8-bit PHY interface
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// - 5 if using 16-bit PHY interface
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// - 5 if using 16-bit PHY interface
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gusbcfg &= ~GUSBCFG_TRDT_Msk;
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gusbcfg &= ~GUSBCFG_TRDT_Msk;
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gusbcfg |= (dwc2->ghwcfg4_bm.phy_data_width ? 5u : 9u) << GUSBCFG_TRDT_Pos;
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/* at32f402_405 does not actually support 16-bit */
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#if CFG_TUSB_MCU == OPT_MCU_AT32F402_405 // at32f402_405 does not actually support 16-bit
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#if CFG_TUSB_MCU == OPT_MCU_AT32F402_405
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gusbcfg |= 9u << GUSBCFG_TRDT_Pos;
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gusbcfg |= (dwc2->ghwcfg4_bm.phy_data_width ? 9u : 9u) << GUSBCFG_TRDT_Pos;
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#else
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#endif
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gusbcfg |= (dwc2->ghwcfg4_bm.phy_data_width ? 5u : 9u) << GUSBCFG_TRDT_Pos;
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#endif
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dwc2->gusbcfg = gusbcfg;
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dwc2->gusbcfg = gusbcfg;
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Block a user