From e339702a2a7977e4e62c2f3fea9aca55f71190ee Mon Sep 17 00:00:00 2001 From: hathach Date: Thu, 15 Aug 2024 16:41:20 +0700 Subject: [PATCH] adding universal register structs for musb --- src/portable/mentor/musb/dcd_musb.c | 99 ++++++++-------- src/portable/mentor/musb/musb_max32.h | 47 +++----- src/portable/mentor/musb/musb_ti.h | 8 +- src/portable/mentor/musb/musb_type.h | 156 +++++++++++++++++++++++--- 4 files changed, 216 insertions(+), 94 deletions(-) diff --git a/src/portable/mentor/musb/dcd_musb.c b/src/portable/mentor/musb/dcd_musb.c index 80dfb9235..78fc3d616 100644 --- a/src/portable/mentor/musb/dcd_musb.c +++ b/src/portable/mentor/musb/dcd_musb.c @@ -54,6 +54,8 @@ _Pragma("GCC diagnostic ignored \"-Waddress-of-packed-member\""); #error "Unsupported MCU" #endif +#define MUSB_REGS(rhport) ((musb_regs_t*) MUSB_BASES[rhport]) + /*------------------------------------------------------------------ * MACRO TYPEDEF CONSTANT ENUM DECLARATION *------------------------------------------------------------------*/ @@ -381,7 +383,7 @@ static void process_ep0(uint8_t rhport) return; } - volatile musb_ctl_regs_t *ctrl_regs = musb_dcd_ctl_regs(rhport); + musb_regs_t* musb_regs = MUSB_REGS(rhport); /* When CSRL0 is zero, it means that completion of sending a any length packet * or receiving a zero length packet. */ @@ -389,7 +391,7 @@ static void process_ep0(uint8_t rhport) /* STATUS IN */ if (*(const uint16_t*)(uintptr_t)&_dcd.setup_packet == 0x0500) { /* The address must be changed on completion of the control transfer. */ - ctrl_regs->FADDR = (uint8_t)_dcd.setup_packet.wValue; + musb_regs->faddr = (uint8_t)_dcd.setup_packet.wValue; } _dcd.setup_packet.bmRequestType = REQUEST_TYPE_INVALID; dcd_event_xfer_complete(rhport, @@ -442,7 +444,7 @@ static void process_edpt_n(uint8_t rhport, uint_fast8_t ep_addr) static void process_bus_reset(uint8_t rhport) { - volatile musb_ctl_regs_t *ctrl_regs = musb_dcd_ctl_regs(rhport); + musb_regs_t* musb_regs = MUSB_REGS(rhport); /* When bmRequestType is REQUEST_TYPE_INVALID(0xFF), * a control transfer state is SETUP or STATUS stage. */ _dcd.setup_packet.bmRequestType = REQUEST_TYPE_INVALID; @@ -450,15 +452,15 @@ static void process_bus_reset(uint8_t rhport) /* When pipe0.buf has not NULL, DATA stage works in progress. */ _dcd.pipe0.buf = NULL; - ctrl_regs->TXIE = 1; /* Enable only EP0 */ - ctrl_regs->RXIE = 0; + musb_regs->intr_txen = 1; /* Enable only EP0 */ + musb_regs->intr_rxen = 0; /* Clear FIFO settings */ for (unsigned i = 1; i < TUP_DCD_ENDPOINT_MAX; ++i) { musb_dcd_reset_fifo(rhport, i, 0); musb_dcd_reset_fifo(rhport, i, 1); } - dcd_event_bus_reset(rhport, (ctrl_regs->POWER & USB_POWER_HSMODE) ? TUSB_SPEED_HIGH : TUSB_SPEED_FULL, true); + dcd_event_bus_reset(rhport, (musb_regs->power & USB_POWER_HSMODE) ? TUSB_SPEED_HIGH : TUSB_SPEED_FULL, true); } /*------------------------------------------------------------------ @@ -467,8 +469,8 @@ static void process_bus_reset(uint8_t rhport) void dcd_init(uint8_t rhport) { - volatile musb_ctl_regs_t *ctrl_regs = musb_dcd_ctl_regs(rhport); - ctrl_regs->IE |= USB_IE_SUSPND; + musb_regs_t* musb_regs = MUSB_REGS(rhport); + musb_regs->intrusben |= USB_IE_SUSPND; musb_dcd_int_clear(rhport); musb_dcd_phy_init(rhport); dcd_connect(rhport); @@ -497,30 +499,29 @@ void dcd_set_address(uint8_t rhport, uint8_t dev_addr) } // Wake up host -void dcd_remote_wakeup(uint8_t rhport) -{ - volatile musb_ctl_regs_t *ctrl_regs = musb_dcd_ctl_regs(rhport); - ctrl_regs->POWER |= USB_POWER_RESUME; +void dcd_remote_wakeup(uint8_t rhport) { + musb_regs_t* musb_regs = MUSB_REGS(rhport); + musb_regs->power |= USB_POWER_RESUME; unsigned cnt = SystemCoreClock / 1000; while (cnt--) __NOP(); - ctrl_regs->POWER &= ~USB_POWER_RESUME; + musb_regs->power &= ~USB_POWER_RESUME; } // Connect by enabling internal pull-up resistor on D+/D- void dcd_connect(uint8_t rhport) { - volatile musb_ctl_regs_t *ctrl_regs = musb_dcd_ctl_regs(rhport); - ctrl_regs->POWER |= TUD_OPT_HIGH_SPEED ? USB_POWER_HSENAB : 0; - ctrl_regs->POWER |= USB_POWER_SOFTCONN; + musb_regs_t* musb_regs = MUSB_REGS(rhport); + musb_regs->power |= TUD_OPT_HIGH_SPEED ? USB_POWER_HSENAB : 0; + musb_regs->power |= USB_POWER_SOFTCONN; } // Disconnect by disabling internal pull-up resistor on D+/D- void dcd_disconnect(uint8_t rhport) { - volatile musb_ctl_regs_t *ctrl_regs = musb_dcd_ctl_regs(rhport); - ctrl_regs->POWER &= ~USB_POWER_SOFTCONN; + musb_regs_t* musb_regs = MUSB_REGS(rhport); + musb_regs->power &= ~USB_POWER_SOFTCONN; } void dcd_sof_enable(uint8_t rhport, bool en) @@ -552,23 +553,25 @@ bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const * ep_desc) pipe->remaining = 0; volatile musb_epn_regs_t *regs = musb_dcd_epn_regs(rhport, epn); - volatile musb_ctl_regs_t *ctrl_regs = musb_dcd_ctl_regs(rhport); + musb_regs_t* musb_regs = MUSB_REGS(rhport); if (dir_in) { regs->TXMAXP = mps; regs->TXCSRH = (xfer == TUSB_XFER_ISOCHRONOUS) ? USB_TXCSRH1_ISO : 0; - if (regs->TXCSRL & USB_TXCSRL1_TXRDY) + if (regs->TXCSRL & USB_TXCSRL1_TXRDY) { regs->TXCSRL = USB_TXCSRL1_CLRDT | USB_TXCSRL1_FLUSH; - else + } else { regs->TXCSRL = USB_TXCSRL1_CLRDT; - ctrl_regs->TXIE |= TU_BIT(epn); + } + musb_regs->intr_txen |= TU_BIT(epn); } else { regs->RXMAXP = mps; regs->RXCSRH = (xfer == TUSB_XFER_ISOCHRONOUS) ? USB_RXCSRH1_ISO : 0; - if (regs->RXCSRL & USB_RXCSRL1_RXRDY) + if (regs->RXCSRL & USB_RXCSRL1_RXRDY) { regs->RXCSRL = USB_RXCSRL1_CLRDT | USB_RXCSRL1_FLUSH; - else + } else { regs->RXCSRL = USB_RXCSRL1_CLRDT; - ctrl_regs->RXIE |= TU_BIT(epn); + } + musb_regs->intr_rxen |= TU_BIT(epn); } /* Setup FIFO */ @@ -580,11 +583,11 @@ bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const * ep_desc) void dcd_edpt_close_all(uint8_t rhport) { volatile musb_epn_regs_t *regs; - volatile musb_ctl_regs_t *ctrl_regs = musb_dcd_ctl_regs(rhport); + musb_regs_t* musb_regs = MUSB_REGS(rhport); unsigned const ie = musb_dcd_get_int_enable(rhport); musb_dcd_int_disable(rhport); - ctrl_regs->TXIE = 1; /* Enable only EP0 */ - ctrl_regs->RXIE = 0; + musb_regs->intr_txen = 1; /* Enable only EP0 */ + musb_regs->intr_rxen = 0; for (unsigned i = 1; i < TUP_DCD_ENDPOINT_MAX; ++i) { regs = musb_dcd_epn_regs(rhport, i); regs->TXMAXP = 0; @@ -596,10 +599,11 @@ void dcd_edpt_close_all(uint8_t rhport) regs->RXMAXP = 0; regs->RXCSRH = 0; - if (regs->RXCSRL & USB_RXCSRL1_RXRDY) + if (regs->RXCSRL & USB_RXCSRL1_RXRDY) { regs->RXCSRL = USB_RXCSRL1_CLRDT | USB_RXCSRL1_FLUSH; - else + } else { regs->RXCSRL = USB_RXCSRL1_CLRDT; + } musb_dcd_reset_fifo(rhport, i, 0); musb_dcd_reset_fifo(rhport, i, 1); @@ -614,25 +618,27 @@ void dcd_edpt_close(uint8_t rhport, uint8_t ep_addr) unsigned const dir_in = tu_edpt_dir(ep_addr); volatile musb_epn_regs_t *regs = musb_dcd_epn_regs(rhport, epn); - volatile musb_ctl_regs_t *ctrl_regs = musb_dcd_ctl_regs(rhport); + musb_regs_t* musb_regs = MUSB_REGS(rhport); unsigned const ie = musb_dcd_get_int_enable(rhport); musb_dcd_int_disable(rhport); if (dir_in) { - ctrl_regs->TXIE &= ~TU_BIT(epn); + musb_regs->intr_txen &= ~TU_BIT(epn); regs->TXMAXP = 0; regs->TXCSRH = 0; - if (regs->TXCSRL & USB_TXCSRL1_TXRDY) + if (regs->TXCSRL & USB_TXCSRL1_TXRDY) { regs->TXCSRL = USB_TXCSRL1_CLRDT | USB_TXCSRL1_FLUSH; - else + } else { regs->TXCSRL = USB_TXCSRL1_CLRDT; + } } else { - ctrl_regs->RXIE &= ~TU_BIT(epn); + musb_regs->intr_rxen &= ~TU_BIT(epn); regs->RXMAXP = 0; regs->RXCSRH = 0; - if (regs->RXCSRL & USB_RXCSRL1_RXRDY) + if (regs->RXCSRL & USB_RXCSRL1_RXRDY) { regs->RXCSRL = USB_RXCSRL1_CLRDT | USB_RXCSRL1_FLUSH; - else + } else { regs->RXCSRL = USB_RXCSRL1_CLRDT; + } } musb_dcd_reset_fifo(rhport, epn, dir_in); if (ie) musb_dcd_int_enable(rhport); @@ -650,8 +656,9 @@ bool dcd_edpt_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t * buffer, uint16_t t if (epnum) { _dcd.pipe_buf_is_fifo[tu_edpt_dir(ep_addr)] &= ~TU_BIT(epnum - 1); ret = edpt_n_xfer(rhport, ep_addr, buffer, total_bytes); - } else + } else { ret = edpt0_xfer(rhport, ep_addr, buffer, total_bytes); + } if (ie) musb_dcd_int_enable(rhport); return ret; } @@ -719,18 +726,18 @@ void dcd_edpt_clear_stall(uint8_t rhport, uint8_t ep_addr) void dcd_int_handler(uint8_t rhport) { uint_fast8_t is, txis, rxis; - volatile musb_ctl_regs_t *ctrl_regs; //Part specific ISR setup/entry musb_dcd_int_handler_enter(rhport); - ctrl_regs = musb_dcd_ctl_regs(rhport); - is = ctrl_regs->IS; /* read and clear interrupt status */ - txis = ctrl_regs->TXIS; /* read and clear interrupt status */ - rxis = ctrl_regs->RXIS; /* read and clear interrupt status */ + musb_regs_t* musb_regs = MUSB_REGS(rhport); + + is = musb_regs->intrusb; /* read and clear interrupt status */ + txis = musb_regs->intr_tx; /* read and clear interrupt status */ + rxis = musb_regs->intr_rx; /* read and clear interrupt status */ // TU_LOG1("D%2x T%2x R%2x\r\n", is, txis, rxis); - is &= ctrl_regs->IE; /* Clear disabled interrupts */ + is &= musb_regs->intrusben; /* Clear disabled interrupts */ if (is & USB_IS_DISCON) { } if (is & USB_IS_SOF) { @@ -746,7 +753,7 @@ void dcd_int_handler(uint8_t rhport) dcd_event_bus_signal(rhport, DCD_EVENT_SUSPEND, true); } - txis &= ctrl_regs->TXIE; /* Clear disabled interrupts */ + txis &= musb_regs->intr_txen; /* Clear disabled interrupts */ if (txis & USB_TXIE_EP0) { process_ep0(rhport); txis &= ~TU_BIT(0); @@ -756,7 +763,7 @@ void dcd_int_handler(uint8_t rhport) process_edpt_n(rhport, tu_edpt_addr(num, TUSB_DIR_IN)); txis &= ~TU_BIT(num); } - rxis &= ctrl_regs->RXIE; /* Clear disabled interrupts */ + rxis &= musb_regs->intr_rxen; /* Clear disabled interrupts */ while (rxis) { unsigned const num = __builtin_ctz(rxis); process_edpt_n(rhport, tu_edpt_addr(num, TUSB_DIR_OUT)); diff --git a/src/portable/mentor/musb/musb_max32.h b/src/portable/mentor/musb/musb_max32.h index 0712aeda4..9c048513c 100644 --- a/src/portable/mentor/musb/musb_max32.h +++ b/src/portable/mentor/musb/musb_max32.h @@ -28,12 +28,14 @@ #define TUSB_MUSB_MAX32_H_ #ifdef __cplusplus - extern "C" { +extern "C" { #endif #include "mxc_device.h" #include "usbhs_regs.h" +const uintptr_t MUSB_BASES[] = { MXC_BASE_USBHS }; + #if CFG_TUD_ENABLED #define USBHS_M31_CLOCK_RECOVERY @@ -92,14 +94,12 @@ static inline void musb_dcd_int_handler_enter(uint8_t rhport) { } } -static inline void musb_dcd_int_handler_exit(uint8_t rhport) -{ +static inline void musb_dcd_int_handler_exit(uint8_t rhport) { //restore register index musb_periph_inst[rhport]->index = isr_saved_index; } -static inline void musb_dcd_phy_init(uint8_t rhport) -{ +static inline void musb_dcd_phy_init(uint8_t rhport) { //Interrupt for VBUS disconnect musb_periph_inst[rhport]->mxm_int_en |= MXC_F_USBHS_MXM_INT_EN_NOVBUS; @@ -136,42 +136,32 @@ static inline void musb_dcd_phy_init(uint8_t rhport) musb_periph_inst[rhport]->m31_phy_ponrst = 1; } -static inline volatile musb_ctl_regs_t* musb_dcd_ctl_regs(uint8_t rhport) -{ - volatile musb_ctl_regs_t *regs = (volatile musb_ctl_regs_t*)((uintptr_t)&(musb_periph_inst[rhport]->faddr)); - return regs; -} - -static inline volatile musb_epn_regs_t* musb_dcd_epn_regs(uint8_t rhport, unsigned epnum) -{ +static inline volatile musb_epn_regs_t* musb_dcd_epn_regs(uint8_t rhport, unsigned epnum) { //Need to set index to map EP registers musb_periph_inst[rhport]->index = epnum; - volatile musb_epn_regs_t *regs = (volatile musb_epn_regs_t*)((uintptr_t)&(musb_periph_inst[rhport]->inmaxp)); + volatile musb_epn_regs_t* regs = (volatile musb_epn_regs_t*) ((uintptr_t) &(musb_periph_inst[rhport]->inmaxp)); return regs; } -static inline volatile musb_ep0_regs_t* musb_dcd_ep0_regs(uint8_t rhport) -{ +static inline volatile musb_ep0_regs_t* musb_dcd_ep0_regs(uint8_t rhport) { //Need to set index to map EP0 registers musb_periph_inst[rhport]->index = 0; - volatile musb_ep0_regs_t *regs = (volatile musb_ep0_regs_t*)((uintptr_t)&(musb_periph_inst[rhport]->csr0)); + volatile musb_ep0_regs_t* regs = (volatile musb_ep0_regs_t*) ((uintptr_t) &(musb_periph_inst[rhport]->csr0)); return regs; } -static volatile void *musb_dcd_ep_get_fifo_ptr(uint8_t rhport, unsigned epnum) -{ - volatile uint32_t *ptr; +static volatile void* musb_dcd_ep_get_fifo_ptr(uint8_t rhport, unsigned epnum) { + volatile uint32_t* ptr; ptr = &(musb_periph_inst[rhport]->fifo0); ptr += epnum; - return (volatile void *) ptr; + return (volatile void*) ptr; } -static inline void musb_dcd_setup_fifo(uint8_t rhport, unsigned epnum, unsigned dir_in, unsigned mps) -{ - (void)mps; +static inline void musb_dcd_setup_fifo(uint8_t rhport, unsigned epnum, unsigned dir_in, unsigned mps) { + (void) mps; //Most likely the caller has already grabbed the right register block. But //as a precaution save and restore the register bank anyways @@ -180,7 +170,7 @@ static inline void musb_dcd_setup_fifo(uint8_t rhport, unsigned epnum, unsigned musb_periph_inst[rhport]->index = epnum; //Disable double buffering - if(dir_in) { + if (dir_in) { musb_periph_inst[rhport]->incsru |= (MXC_F_USBHS_INCSRU_DPKTBUFDIS | MXC_F_USBHS_INCSRU_MODE); } else { musb_periph_inst[rhport]->outcsru |= (MXC_F_USBHS_OUTCSRU_DPKTBUFDIS); @@ -189,8 +179,7 @@ static inline void musb_dcd_setup_fifo(uint8_t rhport, unsigned epnum, unsigned musb_periph_inst[rhport]->index = saved_index; } -static inline void musb_dcd_reset_fifo(uint8_t rhport, unsigned epnum, unsigned dir_in) -{ +static inline void musb_dcd_reset_fifo(uint8_t rhport, unsigned epnum, unsigned dir_in) { //Most likely the caller has already grabbed the right register block. But //as a precaution save and restore the register bank anyways unsigned saved_index = musb_periph_inst[rhport]->index; @@ -198,7 +187,7 @@ static inline void musb_dcd_reset_fifo(uint8_t rhport, unsigned epnum, unsigned musb_periph_inst[rhport]->index = epnum; //Disable double buffering - if(dir_in) { + if (dir_in) { musb_periph_inst[rhport]->incsru |= (MXC_F_USBHS_INCSRU_DPKTBUFDIS); } else { musb_periph_inst[rhport]->outcsru |= (MXC_F_USBHS_OUTCSRU_DPKTBUFDIS); @@ -210,7 +199,7 @@ static inline void musb_dcd_reset_fifo(uint8_t rhport, unsigned epnum, unsigned #endif // CFG_TUD_ENABLED #ifdef __cplusplus - } +} #endif #endif // TUSB_MUSB_MAX32_H_ diff --git a/src/portable/mentor/musb/musb_ti.h b/src/portable/mentor/musb/musb_ti.h index ec0a267b1..df77303a0 100644 --- a/src/portable/mentor/musb/musb_ti.h +++ b/src/portable/mentor/musb/musb_ti.h @@ -42,6 +42,8 @@ #error "Unsupported MCUs" #endif +const uintptr_t MUSB_BASES[] = { USB0_BASE }; + // Header supports both device and host modes. Only include what's necessary #if CFG_TUD_ENABLED @@ -95,12 +97,6 @@ static inline void musb_dcd_int_handler_exit(uint8_t rhport){ //Nothing to do for this part } -static inline volatile musb_ctl_regs_t* musb_dcd_ctl_regs(uint8_t rhport) -{ - volatile musb_ctl_regs_t *regs = (volatile musb_ctl_regs_t*)((uintptr_t)&(musb_periph_inst[rhport]->FADDR)); - return regs; -} - static inline volatile musb_epn_regs_t* musb_dcd_epn_regs(uint8_t rhport, unsigned epnum) { uintptr_t baseptr = (uintptr_t)&(musb_periph_inst[rhport]->TXMAXP1); diff --git a/src/portable/mentor/musb/musb_type.h b/src/portable/mentor/musb/musb_type.h index d21dcd6da..9986a30e0 100644 --- a/src/portable/mentor/musb/musb_type.h +++ b/src/portable/mentor/musb/musb_type.h @@ -32,8 +32,8 @@ * *******************************************************************************/ -#ifndef _TUSB_MUSB_TYPE_H_ -#define _TUSB_MUSB_TYPE_H_ +#ifndef TUSB_MUSB_TYPE_H_ +#define TUSB_MUSB_TYPE_H_ #include "stdint.h" @@ -41,6 +41,22 @@ extern "C" { #endif +#ifndef __IO + #define __IO volatile +#endif + +#ifndef __I + #define __I volatile const +#endif + +#ifndef __O + #define __O volatile +#endif + +#ifndef __R + #define __R volatile const +#endif + // Endpoint register mapping. Non-zero end points. typedef struct TU_ATTR_PACKED { uint16_t TXMAXP; @@ -60,17 +76,131 @@ typedef struct TU_ATTR_PACKED { uint8_t COUNT0; } musb_ep0_regs_t; -// Control register mapping -typedef struct TU_ATTR_PACKED { - uint8_t FADDR; - uint8_t POWER; - uint16_t TXIS; - uint16_t RXIS; - uint16_t TXIE; - uint16_t RXIE; - uint8_t IS; - uint8_t IE; -} musb_ctl_regs_t; +typedef struct { + //------------- Common -------------// + __IO uint8_t faddr; // 0x00: FADDR + __IO uint8_t power; // 0x01: POWER + + __IO uint16_t intr_tx; // 0x02: INTR_TX + __IO uint16_t intr_rx; // 0x04: INTR_RX + + __IO uint16_t intr_txen; // 0x06: INTR_TXEN + __IO uint16_t intr_rxen; // 0x08: INTR_RXEN + + __IO uint8_t intrusb; // 0x0A: INTRUSB + __IO uint8_t intrusben; // 0x0B: INTRUSBEN + + __IO uint16_t frame; // 0x0C: FRAME + __IO uint8_t index; // 0x0E: INDEX + __IO uint8_t testmode; // 0x0F: TESTMODE + __IO uint16_t inmaxp; // 0x10: INMAXP + union { + __IO uint8_t csr0; // 0x12: CSR0 + __IO uint8_t incsrl; // 0x12: INCSRL + }; + __IO uint8_t incsru; // 0x13: INCSRU + __IO uint16_t outmaxp; // 0x14: OUTMAXP + __IO uint8_t outcsrl; // 0x16: OUTCSRL + __IO uint8_t outcsru; // 0x17: OUTCSRU + union { + __IO uint16_t count0; // 0x18: COUNT0 + __IO uint16_t outcount; // 0x18: OUTCOUNT + }; + __R uint16_t rsv_0x1a_0x1f[3]; + __IO uint32_t fifo0; // 0x20: FIFO0 + __IO uint32_t fifo1; // 0x24: FIFO1 + __IO uint32_t fifo2; // 0x28: FIFO2 + __IO uint32_t fifo3; // 0x2c: FIFO3 + __IO uint32_t fifo4; // 0x30: FIFO4 + __IO uint32_t fifo5; // 0x34: FIFO5 + __IO uint32_t fifo6; // 0x38: FIFO6 + __IO uint32_t fifo7; // 0x3c: FIFO7 + __IO uint32_t fifo8; // 0x40: FIFO8 + __IO uint32_t fifo9; // 0x44: FIFO9 + __IO uint32_t fifo10; // 0x48: FIFO10 + __IO uint32_t fifo11; // 0x4c: FIFO11 + __IO uint32_t fifo12; // 0x50: FIFO12 + __IO uint32_t fifo13; // 0x54: FIFO13 + __IO uint32_t fifo14; // 0x58: FIFO14 + __IO uint32_t fifo15; // 0x5c: FIFO15 + __IO uint8_t devctl; // 0x60: DEVCTL + __IO uint8_t misc; // 0x61: MISC + + //------------- Dynammic FIFO -------------// + __IO uint8_t txfifo_sz; // 0x62: TXFIFO_SZ + __IO uint8_t rxfifo_sz; // 0x63: RXFIFO_SZ + __IO uint16_t txfifo_addr; // 0x64: TXFIFO_ADDR + __IO uint16_t rxfifo_addr; // 0x66: RXFIFO_ADDR + + //------------- Additional Control/Status -------------// + union { + __O uint32_t vcontrol; // 0x68: VCONTROL + __IO uint32_t vstatus; // 0x68: VSTATUS + }; + __IO uint16_t hwvers; // 0x6c: HWVERS + __R uint16_t rsv_0x6e_0x77[5]; + + //------------- Additional Configuration -------------// + __IO uint8_t epinfo; // 0x78: EPINFO + __IO uint8_t raminfo; // 0x79: RAMINFO + __IO uint8_t softreset; // 0x7A: SOFTRESET (Analog), Link info + __IO uint8_t vplen; // 0x7B: VPLEN + __IO uint8_t hs_eof1; // 0x7C: HS_EOF1 + __IO uint8_t fs_eof1; // 0x7D: FS_EOF1 + __IO uint8_t ls_eof1; // 0x7E: LS_EOF1 + __IO uint8_t soft_rst; // 0x7F: SOFT_RST + + //------------- Extended -------------// + __IO uint16_t ctuch; // 0x80: CTUCH + __IO uint16_t cthsrtn; // 0x82: CTHSRTN + __R uint32_t rsv_0x84_0x3ff[223]; + + //------------- Analog PHY -------------// + __IO uint32_t mxm_usb_reg_00; // 0x400: MXM_USB_REG_00 + __IO uint32_t m31_phy_utmi_reset; // 0x404: M31_PHY_UTMI_RESET + __IO uint32_t m31_phy_utmi_vcontrol; // 0x408: M31_PHY_UTMI_VCONTROL + __IO uint32_t m31_phy_clk_en; // 0x40C: M31_PHY_CLK_EN + __IO uint32_t m31_phy_ponrst; // 0x410: M31_PHY_PONRST + __IO uint32_t m31_phy_noncry_rstb; // 0x414: M31_PHY_NONCRY_RSTB + __IO uint32_t m31_phy_noncry_en; // 0x418: M31_PHY_NONCRY_EN + __R uint32_t rsv_0x41c; + __IO uint32_t m31_phy_u2_compliance_en; // 0x420: M31_PHY_U2_COMPLIANCE_EN + __IO uint32_t m31_phy_u2_compliance_dac_adj; // 0x424: M31_PHY_U2_COMPLIANCE_DAC_ADJ + __IO uint32_t m31_phy_u2_compliance_dac_adj_en; // 0x428: M31_PHY_U2_COMPLIANCE_DAC_ADJ_EN + __IO uint32_t m31_phy_clk_rdy; // 0x42C: M31_PHY_CLK_RDY + __IO uint32_t m31_phy_pll_en; // 0x430: M31_PHY_PLL_EN + __IO uint32_t m31_phy_bist_ok; // 0x434: M31_PHY_BIST_OK + __IO uint32_t m31_phy_data_oe; // 0x438: M31_PHY_DATA_OE + __IO uint32_t m31_phy_oscouten; // 0x43C: M31_PHY_OSCOUTEN + __IO uint32_t m31_phy_lpm_alive; // 0x440: M31_PHY_LPM_ALIVE + __IO uint32_t m31_phy_hs_bist_mode; // 0x444: M31_PHY_HS_BIST_MODE + __IO uint32_t m31_phy_coreclkin; // 0x448: M31_PHY_CORECLKIN + __IO uint32_t m31_phy_xtlsel; // 0x44C: M31_PHY_XTLSEL + __IO uint32_t m31_phy_ls_en; // 0x450: M31_PHY_LS_EN + __IO uint32_t m31_phy_debug_sel; // 0x454: M31_PHY_DEBUG_SEL + __IO uint32_t m31_phy_debug_out; // 0x458: M31_PHY_DEBUG_OUT + __IO uint32_t m31_phy_outclksel; // 0x45C: M31_PHY_OUTCLKSEL + __IO uint32_t m31_phy_xcfgi_31_0; // 0x460: M31_PHY_XCFGI_31_0 + __IO uint32_t m31_phy_xcfgi_63_32; // 0x464: M31_PHY_XCFGI_63_32 + __IO uint32_t m31_phy_xcfgi_95_64; // 0x468: M31_PHY_XCFGI_95_64 + __IO uint32_t m31_phy_xcfgi_127_96; // 0x46C: M31_PHY_XCFGI_127_96 + __IO uint32_t m31_phy_xcfgi_137_128; // 0x470: M31_PHY_XCFGI_137_128 + __IO uint32_t m31_phy_xcfg_hs_coarse_tune_num; // 0x474: M31_PHY_XCFG_HS_COARSE_TUNE_NUM + __IO uint32_t m31_phy_xcfg_hs_fine_tune_num; // 0x478: M31_PHY_XCFG_HS_FINE_TUNE_NUM + __IO uint32_t m31_phy_xcfg_fs_coarse_tune_num; // 0x47C: M31_PHY_XCFG_FS_COARSE_TUNE_NUM + __IO uint32_t m31_phy_xcfg_fs_fine_tune_num; // 0x480: M31_PHY_XCFG_FS_FINE_TUNE_NUM + __IO uint32_t m31_phy_xcfg_lock_range_max; // 0x484: M31_PHY_XCFG_LOCK_RANGE_MAX + __IO uint32_t m31_phy_xcfgi_lock_range_min; // 0x488: M31_PHY_XCFGI_LOCK_RANGE_MIN + __IO uint32_t m31_phy_xcfg_ob_rsel; // 0x48C: M31_PHY_XCFG_OB_RSEL + __IO uint32_t m31_phy_xcfg_oc_rsel; // 0x490: M31_PHY_XCFG_OC_RSEL + __IO uint32_t m31_phy_xcfgo; // 0x494: M31_PHY_XCFGO + __IO uint32_t mxm_int; // 0x498: MXM_INT + __IO uint32_t mxm_int_en; // 0x49C: MXM_INT_EN + __IO uint32_t mxm_suspend; // 0x4A0: MXM_SUSPEND + __IO uint32_t mxm_reg_a4; // 0x4A4: MXM_REG_A4 +} musb_regs_t; + +TU_VERIFY_STATIC(sizeof(musb_regs_t) == 0x4A8, "size is not correct"); //***************************************************************************** //