rename rx63n to simply rx
This commit is contained in:
24
hw/bsp/rx/boards/gr_citrus/board.mk
Normal file
24
hw/bsp/rx/boards/gr_citrus/board.mk
Normal file
@@ -0,0 +1,24 @@
|
||||
DEPS_SUBMODULES += hw/mcu/renesas/rx
|
||||
|
||||
CFLAGS += \
|
||||
-mcpu=rx610 \
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||||
-misa=v1 \
|
||||
-DCFG_TUSB_MCU=OPT_MCU_RX63X
|
||||
|
||||
MCU_DIR = hw/mcu/renesas/rx/rx63n
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||||
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||||
# All source paths should be relative to the top level.
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||||
LD_FILE = $(BOARD_PATH)/r5f5631fd.ld
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||||
|
||||
# For freeRTOS port source
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||||
FREERTOS_PORT = RX600
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||||
|
||||
# For flash-jlink target
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||||
JLINK_DEVICE = R5F5631F
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||||
JLINK_IF = JTAG
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||||
|
||||
# For flash-pyocd target
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||||
PYOCD_TARGET =
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|
||||
# flash using jlink
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||||
flash: flash-jlink
|
255
hw/bsp/rx/boards/gr_citrus/gr_citrus.c
Normal file
255
hw/bsp/rx/boards/gr_citrus/gr_citrus.c
Normal file
@@ -0,0 +1,255 @@
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||||
/*
|
||||
* The MIT License (MIT)
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||||
*
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||||
* Copyright (c) 2021, Koji Kitayama
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||||
*
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||||
* Permission is hereby granted, free of charge, to any person obtaining a copy
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||||
* of this software and associated documentation files (the "Software"), to deal
|
||||
* in the Software without restriction, including without limitation the rights
|
||||
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
||||
* copies of the Software, and to permit persons to whom the Software is
|
||||
* furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in
|
||||
* all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
|
||||
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
|
||||
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
|
||||
* THE SOFTWARE.
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||||
*
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||||
* This file is part of the TinyUSB stack.
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||||
*/
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/* How to connect JLink and GR-CITRUS
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*
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* GR-CITRUS needs to solder some pads to enable JTAG interface.
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* - Short the following pads individually with solder.
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* - J4
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* - J5
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* - Short EMLE pad and 3.3V(GR-CITRUS pin name) with a wire.
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*
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* The pads are [the back side of GR-CITRUS](https://www.slideshare.net/MinaoYamamoto/grcitrusrx631/2).
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*
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* Connet the pins between GR-CITRUS and JLink as follows.
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*
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* | JTAG Function | GR-CITRUS pin name| JLink pin No.| note |
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* |:-------------:|:-----------------:|:------------:|:--------:|
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* | VTref | 3.3V | 1 | |
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||||
* | TRST | 5 | 3 | |
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* | GND | GND | 4 | |
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* | TDI | 3 | 5 | |
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* | TMS | 2 | 7 | |
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* | TCK | 14 | 9 | short J4 |
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* | TDO | 9 | 13 | short J5 |
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* | nRES | RST | 15 | |
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*
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* JLink firmware needs to update to V6.96 or newer version to avoid
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* [a bug](https://forum.segger.com/index.php/Thread/7758-SOLVED-Bug-in-JLink-from-V6-88b-regarding-RX65N)
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* regarding downloading.
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*
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* When using SEGGER RTT, `RX_NEWLIB=0` should be added to make command arguments.
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* The option is used to change the C runtime library to `optlib` from `newlib`.
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* RTT may not work with `newlib`.
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*/
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#include "../board.h"
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#include "iodefine.h"
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#include "interrupt_handlers.h"
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#define IRQ_PRIORITY_CMT0 5
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#define IRQ_PRIORITY_USBI0 6
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#define IRQ_PRIORITY_SCI0 5
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#define SYSTEM_PRCR_PRC1 (1<<1)
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#define SYSTEM_PRCR_PRKEY (0xA5u<<8)
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#define CMT_PCLK 48000000
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#define CMT_CMCR_CKS_DIV_128 2
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#define CMT_CMCR_CMIE (1<<6)
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#define MPC_PFS_ISEL (1<<6)
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#define SCI_PCLK 48000000
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#define SCI_SSR_FER (1<<4)
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#define SCI_SSR_ORER (1<<5)
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#define SCI_SCR_TEIE (1u<<2)
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#define SCI_SCR_RE (1u<<4)
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#define SCI_SCR_TE (1u<<5)
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#define SCI_SCR_RIE (1u<<6)
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#define SCI_SCR_TIE (1u<<7)
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//--------------------------------------------------------------------+
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// SCI0 handling
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//--------------------------------------------------------------------+
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typedef struct {
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uint8_t *buf;
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uint32_t cnt;
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} sci_buf_t;
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static volatile sci_buf_t sci0_buf[2];
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void INT_Excep_SCI0_TXI0(void)
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{
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uint8_t *buf = sci0_buf[0].buf;
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uint32_t cnt = sci0_buf[0].cnt;
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if (!buf || !cnt) {
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SCI0.SCR.BYTE &= ~(SCI_SCR_TEIE | SCI_SCR_TE | SCI_SCR_TIE);
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return;
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}
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SCI0.TDR = *buf;
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if (--cnt) {
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++buf;
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} else {
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buf = NULL;
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SCI0.SCR.BIT.TIE = 0;
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SCI0.SCR.BIT.TEIE = 1;
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}
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sci0_buf[0].buf = buf;
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sci0_buf[0].cnt = cnt;
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}
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void INT_Excep_SCI0_TEI0(void)
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{
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SCI0.SCR.BYTE &= ~(SCI_SCR_TEIE | SCI_SCR_TE | SCI_SCR_TIE);
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}
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void INT_Excep_SCI0_RXI0(void)
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{
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uint8_t *buf = sci0_buf[1].buf;
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uint32_t cnt = sci0_buf[1].cnt;
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if (!buf || !cnt ||
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(SCI0.SSR.BYTE & (SCI_SSR_FER | SCI_SSR_ORER))) {
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sci0_buf[1].buf = NULL;
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||||
SCI0.SSR.BYTE = 0;
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||||
SCI0.SCR.BYTE &= ~(SCI_SCR_RE | SCI_SCR_RIE);
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||||
return;
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||||
}
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||||
*buf = SCI0.RDR;
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||||
if (--cnt) {
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||||
++buf;
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||||
} else {
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||||
buf = NULL;
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||||
SCI0.SCR.BYTE &= ~(SCI_SCR_RE | SCI_SCR_RIE);
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||||
}
|
||||
sci0_buf[1].buf = buf;
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||||
sci0_buf[1].cnt = cnt;
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||||
}
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||||
|
||||
//--------------------------------------------------------------------+
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||||
// Forward USB interrupt events to TinyUSB IRQ Handler
|
||||
//--------------------------------------------------------------------+
|
||||
void INT_Excep_USB0_USBI0(void)
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||||
{
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||||
tud_int_handler(0);
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||||
}
|
||||
|
||||
void board_init(void)
|
||||
{
|
||||
#if CFG_TUSB_OS == OPT_OS_NONE
|
||||
/* Enable CMT0 */
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||||
SYSTEM.PRCR.WORD = SYSTEM_PRCR_PRKEY | SYSTEM_PRCR_PRC1;
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||||
MSTP(CMT0) = 0;
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||||
SYSTEM.PRCR.WORD = SYSTEM_PRCR_PRKEY;
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||||
/* Setup 1ms tick timer */
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||||
CMT0.CMCNT = 0;
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CMT0.CMCOR = CMT_PCLK / 1000 / 128;
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CMT0.CMCR.WORD = CMT_CMCR_CMIE | CMT_CMCR_CKS_DIV_128;
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||||
IR(CMT0, CMI0) = 0;
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||||
IPR(CMT0, CMI0) = IRQ_PRIORITY_CMT0;
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||||
IEN(CMT0, CMI0) = 1;
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||||
CMT.CMSTR0.BIT.STR0 = 1;
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||||
#endif
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||||
|
||||
/* Unlock MPC registers */
|
||||
MPC.PWPR.BIT.B0WI = 0;
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||||
MPC.PWPR.BIT.PFSWE = 1;
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||||
/* LED PA0 */
|
||||
PORTA.PMR.BIT.B0 = 0U;
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||||
PORTA.PODR.BIT.B0 = 0U;
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PORTA.PDR.BIT.B0 = 1U;
|
||||
/* UART TXD0 => P20, RXD0 => P21 */
|
||||
PORT2.PMR.BIT.B0 = 1U;
|
||||
PORT2.PCR.BIT.B0 = 1U;
|
||||
MPC.P20PFS.BYTE = 0b01010;
|
||||
PORT2.PMR.BIT.B1 = 1U;
|
||||
MPC.P21PFS.BYTE = 0b01010;
|
||||
/* USB VBUS -> P16 DPUPE -> P14 */
|
||||
PORT1.PMR.BIT.B4 = 1U;
|
||||
PORT1.PMR.BIT.B6 = 1U;
|
||||
MPC.P14PFS.BYTE = 0b10001;
|
||||
MPC.P16PFS.BYTE = MPC_PFS_ISEL | 0b10001;
|
||||
MPC.PFUSB0.BIT.PUPHZS = 1;
|
||||
/* Lock MPC registers */
|
||||
MPC.PWPR.BIT.PFSWE = 0;
|
||||
MPC.PWPR.BIT.B0WI = 1;
|
||||
|
||||
IR(USB0, USBI0) = 0;
|
||||
IPR(USB0, USBI0) = IRQ_PRIORITY_USBI0;
|
||||
|
||||
/* Enable SCI0 */
|
||||
SYSTEM.PRCR.WORD = SYSTEM_PRCR_PRKEY | SYSTEM_PRCR_PRC1;
|
||||
MSTP(SCI0) = 0;
|
||||
SYSTEM.PRCR.WORD = SYSTEM_PRCR_PRKEY;
|
||||
SCI0.BRR = (SCI_PCLK / (32 * 115200)) - 1;
|
||||
IR(SCI0, RXI0) = 0;
|
||||
IR(SCI0, TXI0) = 0;
|
||||
IR(SCI0, TEI0) = 0;
|
||||
IPR(SCI0, RXI0) = IRQ_PRIORITY_SCI0;
|
||||
IPR(SCI0, TXI0) = IRQ_PRIORITY_SCI0;
|
||||
IPR(SCI0, TEI0) = IRQ_PRIORITY_SCI0;
|
||||
IEN(SCI0, RXI0) = 1;
|
||||
IEN(SCI0, TXI0) = 1;
|
||||
IEN(SCI0, TEI0) = 1;
|
||||
}
|
||||
|
||||
//--------------------------------------------------------------------+
|
||||
// Board porting API
|
||||
//--------------------------------------------------------------------+
|
||||
|
||||
void board_led_write(bool state)
|
||||
{
|
||||
PORTA.PODR.BIT.B0 = state ? 1 : 0;
|
||||
}
|
||||
|
||||
uint32_t board_button_read(void)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
int board_uart_read(uint8_t* buf, int len)
|
||||
{
|
||||
sci0_buf[1].buf = buf;
|
||||
sci0_buf[1].cnt = len;
|
||||
SCI0.SCR.BYTE |= SCI_SCR_RE | SCI_SCR_RIE;
|
||||
while (SCI0.SCR.BIT.RE) ;
|
||||
return len - sci0_buf[1].cnt;
|
||||
}
|
||||
|
||||
int board_uart_write(void const *buf, int len)
|
||||
{
|
||||
sci0_buf[0].buf = (uint8_t*)buf;
|
||||
sci0_buf[0].cnt = len;
|
||||
SCI0.SCR.BYTE |= SCI_SCR_TE | SCI_SCR_TIE;
|
||||
while (SCI0.SCR.BIT.TE) ;
|
||||
return len;
|
||||
}
|
||||
|
||||
#if CFG_TUSB_OS == OPT_OS_NONE
|
||||
volatile uint32_t system_ticks = 0;
|
||||
void INT_Excep_CMT0_CMI0(void)
|
||||
{
|
||||
++system_ticks;
|
||||
}
|
||||
|
||||
uint32_t board_millis(void)
|
||||
{
|
||||
return system_ticks;
|
||||
}
|
||||
#else
|
||||
uint32_t SystemCoreClock = 96000000;
|
||||
#endif
|
31
hw/bsp/rx/boards/gr_citrus/hwinit.c
Normal file
31
hw/bsp/rx/boards/gr_citrus/hwinit.c
Normal file
@@ -0,0 +1,31 @@
|
||||
/************************************************************************/
|
||||
/* File Version: V1.00 */
|
||||
/* Date Generated: 08/07/2013 */
|
||||
/************************************************************************/
|
||||
|
||||
#include "iodefine.h"
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
extern void HardwareSetup(void);
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
void HardwareSetup(void)
|
||||
{
|
||||
SYSTEM.PRCR.WORD = 0xA503u;
|
||||
SYSTEM.SOSCCR.BYTE = 0x01u;
|
||||
SYSTEM.MOSCWTCR.BYTE = 0x0Du;
|
||||
SYSTEM.PLLWTCR.BYTE = 0x0Eu;
|
||||
SYSTEM.PLLCR.WORD = 0x0F00u;
|
||||
SYSTEM.MOSCCR.BYTE = 0x00u;
|
||||
SYSTEM.PLLCR2.BYTE = 0x00u;
|
||||
for (unsigned i = 0; i < 2075u; ++i) __asm("nop");
|
||||
SYSTEM.SCKCR.LONG = 0x21021211u;
|
||||
SYSTEM.SCKCR2.WORD = 0x0033u;
|
||||
SYSTEM.SCKCR3.WORD = 0x0400u;
|
||||
SYSTEM.SYSCR0.WORD = 0x5A01;
|
||||
SYSTEM.MSTPCRB.BIT.MSTPB15 = 0;
|
||||
SYSTEM.PRCR.WORD = 0xA500u;
|
||||
}
|
127
hw/bsp/rx/boards/gr_citrus/r5f5631fd.ld
Normal file
127
hw/bsp/rx/boards/gr_citrus/r5f5631fd.ld
Normal file
@@ -0,0 +1,127 @@
|
||||
__USTACK_SIZE = 0x00000200;
|
||||
__ISTACK_SIZE = 0x00000200;
|
||||
|
||||
MEMORY
|
||||
{
|
||||
RAM : ORIGIN = 0x4, LENGTH = 0x3fffc
|
||||
ROM : ORIGIN = 0xFFE00000, LENGTH = 0x200000
|
||||
}
|
||||
SECTIONS
|
||||
{
|
||||
.fvectors 0xFFFFFF80: AT(0xFFFFFF80)
|
||||
{
|
||||
KEEP(*(.fvectors))
|
||||
} > ROM
|
||||
.text 0xFFE00000: AT(0xFFE00000)
|
||||
{
|
||||
*(.text)
|
||||
*(.text.*)
|
||||
*(P)
|
||||
etext = .;
|
||||
} > ROM
|
||||
.rvectors ALIGN(4):
|
||||
{
|
||||
_rvectors_start = .;
|
||||
KEEP(*(.rvectors))
|
||||
_rvectors_end = .;
|
||||
} > ROM
|
||||
.init :
|
||||
{
|
||||
KEEP(*(.init))
|
||||
__preinit_array_start = .;
|
||||
KEEP(*(.preinit_array))
|
||||
__preinit_array_end = .;
|
||||
__init_array_start = (. + 3) & ~ 3;
|
||||
KEEP(*(.init_array))
|
||||
KEEP(*(SORT(.init_array.*)))
|
||||
__init_array_end = .;
|
||||
__fini_array_start = .;
|
||||
KEEP(*(.fini_array))
|
||||
KEEP(*(SORT(.fini_array.*)))
|
||||
__fini_array_end = .;
|
||||
} > ROM
|
||||
.fini :
|
||||
{
|
||||
KEEP(*(.fini))
|
||||
} > ROM
|
||||
.got :
|
||||
{
|
||||
*(.got)
|
||||
*(.got.plt)
|
||||
} > ROM
|
||||
.rodata :
|
||||
{
|
||||
*(.rodata)
|
||||
*(.rodata.*)
|
||||
*(C_1)
|
||||
*(C_2)
|
||||
*(C)
|
||||
_erodata = .;
|
||||
} > ROM
|
||||
.eh_frame_hdr :
|
||||
{
|
||||
*(.eh_frame_hdr)
|
||||
} > ROM
|
||||
.eh_frame :
|
||||
{
|
||||
*(.eh_frame)
|
||||
} > ROM
|
||||
.jcr :
|
||||
{
|
||||
*(.jcr)
|
||||
} > ROM
|
||||
.tors :
|
||||
{
|
||||
__CTOR_LIST__ = .;
|
||||
. = ALIGN(2);
|
||||
___ctors = .;
|
||||
*(.ctors)
|
||||
___ctors_end = .;
|
||||
__CTOR_END__ = .;
|
||||
__DTOR_LIST__ = .;
|
||||
___dtors = .;
|
||||
*(.dtors)
|
||||
___dtors_end = .;
|
||||
__DTOR_END__ = .;
|
||||
. = ALIGN(2);
|
||||
_mdata = .;
|
||||
} > ROM
|
||||
.data : AT(_mdata)
|
||||
{
|
||||
_data = .;
|
||||
*(.data)
|
||||
*(.data.*)
|
||||
*(D)
|
||||
*(D_1)
|
||||
*(D_2)
|
||||
_edata = .;
|
||||
} > RAM
|
||||
.gcc_exc :
|
||||
{
|
||||
*(.gcc_exc)
|
||||
} > RAM
|
||||
.bss :
|
||||
{
|
||||
_bss = .;
|
||||
*(.bss)
|
||||
*(.bss.**)
|
||||
*(COMMON)
|
||||
*(B)
|
||||
*(B_1)
|
||||
*(B_2)
|
||||
_ebss = .;
|
||||
_end = .;
|
||||
} > RAM
|
||||
.ustack :
|
||||
{
|
||||
. = ALIGN(8);
|
||||
. = . + __USTACK_SIZE;
|
||||
PROVIDE(_ustack = .);
|
||||
} > RAM
|
||||
.istack :
|
||||
{
|
||||
. = ALIGN(8);
|
||||
. = . + __ISTACK_SIZE;
|
||||
PROVIDE(_istack = .);
|
||||
} > RAM
|
||||
}
|
26
hw/bsp/rx/boards/rx65n_cloud_kit/board.mk
Normal file
26
hw/bsp/rx/boards/rx65n_cloud_kit/board.mk
Normal file
@@ -0,0 +1,26 @@
|
||||
CFLAGS += \
|
||||
-mcpu=rx64m \
|
||||
-misa=v2 \
|
||||
-DCFG_TUSB_MCU=OPT_MCU_RX65X \
|
||||
-DIR_USB0_USBI0=IR_PERIB_INTB185 \
|
||||
-DIER_USB0_USBI0=IER_PERIB_INTB185 \
|
||||
-DIEN_USB0_USBI0=IEN_PERIB_INTB185
|
||||
|
||||
MCU_DIR = hw/mcu/renesas/rx/rx65n
|
||||
|
||||
# All source paths should be relative to the top level.
|
||||
LD_FILE = $(BOARD_PATH)/r5f565ne.ld
|
||||
|
||||
# For freeRTOS port source
|
||||
FREERTOS_PORT = RX600
|
||||
|
||||
# For flash-jlink target
|
||||
JLINK_DEVICE = R5F565NE
|
||||
JLINK_IF = JTAG
|
||||
|
||||
# For flash-pyocd target
|
||||
PYOCD_TARGET =
|
||||
|
||||
# flash using rfp-cli
|
||||
flash: $(BUILD)/$(PROJECT).mot
|
||||
rfp-cli -device rx65x -tool e2l -if fine -fo id FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF -auth id FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF -auto $^
|
168
hw/bsp/rx/boards/rx65n_cloud_kit/r5f565ne.ld
Normal file
168
hw/bsp/rx/boards/rx65n_cloud_kit/r5f565ne.ld
Normal file
@@ -0,0 +1,168 @@
|
||||
__USTACK_SIZE = 0x00000200;
|
||||
__ISTACK_SIZE = 0x00000200;
|
||||
|
||||
MEMORY
|
||||
{
|
||||
RAM : ORIGIN = 0x4, LENGTH = 0x3fffc
|
||||
RAM2 : ORIGIN = 0x00800000, LENGTH = 0x60000
|
||||
OFS : ORIGIN = 0xFE7F5D00, LENGTH = 128
|
||||
ROM : ORIGIN = 0xFFE00000, LENGTH = 0x200000
|
||||
}
|
||||
SECTIONS
|
||||
{
|
||||
.exvectors 0xFFFFFF80: AT(0xFFFFFF80)
|
||||
{
|
||||
"_exvectors_start" = .;
|
||||
KEEP(*(.exvectors))
|
||||
"_exvectors_end" = .;
|
||||
} >ROM
|
||||
.fvectors 0xFFFFFFFC: AT(0xFFFFFFFC)
|
||||
{
|
||||
KEEP(*(.fvectors))
|
||||
} > ROM
|
||||
.text 0xFFE00000: AT(0xFFE00000)
|
||||
{
|
||||
*(.text)
|
||||
*(.text.*)
|
||||
*(P)
|
||||
KEEP(*(.text.*_isr))
|
||||
etext = .;
|
||||
} > ROM
|
||||
.rvectors ALIGN(4):
|
||||
{
|
||||
_rvectors_start = .;
|
||||
KEEP(*(.rvectors))
|
||||
_rvectors_end = .;
|
||||
} > ROM
|
||||
.init :
|
||||
{
|
||||
KEEP(*(.init))
|
||||
__preinit_array_start = .;
|
||||
KEEP(*(.preinit_array))
|
||||
__preinit_array_end = .;
|
||||
__init_array_start = (. + 3) & ~ 3;
|
||||
KEEP(*(.init_array))
|
||||
KEEP(*(SORT(.init_array.*)))
|
||||
__init_array_end = .;
|
||||
__fini_array_start = .;
|
||||
KEEP(*(.fini_array))
|
||||
KEEP(*(SORT(.fini_array.*)))
|
||||
__fini_array_end = .;
|
||||
} > ROM
|
||||
.fini :
|
||||
{
|
||||
KEEP(*(.fini))
|
||||
} > ROM
|
||||
.got :
|
||||
{
|
||||
*(.got)
|
||||
*(.got.plt)
|
||||
} > ROM
|
||||
.rodata :
|
||||
{
|
||||
*(.rodata)
|
||||
*(.rodata.*)
|
||||
*(C_1)
|
||||
*(C_2)
|
||||
*(C)
|
||||
_erodata = .;
|
||||
} > ROM
|
||||
.eh_frame_hdr :
|
||||
{
|
||||
*(.eh_frame_hdr)
|
||||
} > ROM
|
||||
.eh_frame :
|
||||
{
|
||||
*(.eh_frame)
|
||||
} > ROM
|
||||
.jcr :
|
||||
{
|
||||
*(.jcr)
|
||||
} > ROM
|
||||
.tors :
|
||||
{
|
||||
__CTOR_LIST__ = .;
|
||||
. = ALIGN(2);
|
||||
___ctors = .;
|
||||
*(.ctors)
|
||||
___ctors_end = .;
|
||||
__CTOR_END__ = .;
|
||||
__DTOR_LIST__ = .;
|
||||
___dtors = .;
|
||||
*(.dtors)
|
||||
___dtors_end = .;
|
||||
__DTOR_END__ = .;
|
||||
. = ALIGN(2);
|
||||
_mdata = .;
|
||||
} > ROM
|
||||
.data : AT(_mdata)
|
||||
{
|
||||
_data = .;
|
||||
*(.data)
|
||||
*(.data.*)
|
||||
*(D)
|
||||
*(D_1)
|
||||
*(D_2)
|
||||
_edata = .;
|
||||
} > RAM
|
||||
.gcc_exc :
|
||||
{
|
||||
*(.gcc_exc)
|
||||
} > RAM
|
||||
.bss :
|
||||
{
|
||||
_bss = .;
|
||||
*(.bss)
|
||||
*(.bss.**)
|
||||
*(COMMON)
|
||||
*(B)
|
||||
*(B_1)
|
||||
*(B_2)
|
||||
_ebss = .;
|
||||
_end = .;
|
||||
} > RAM
|
||||
.ustack :
|
||||
{
|
||||
. = ALIGN(8);
|
||||
. = . + __USTACK_SIZE;
|
||||
PROVIDE(_ustack = .);
|
||||
} > RAM
|
||||
.istack :
|
||||
{
|
||||
. = ALIGN(8);
|
||||
. = . + __ISTACK_SIZE;
|
||||
PROVIDE(_istack = .);
|
||||
} > RAM
|
||||
.ofs1 0xFE7F5D00: AT(0xFE7F5D00)
|
||||
{
|
||||
KEEP(*(.ofs1))
|
||||
} > OFS
|
||||
.ofs2 0xFE7F5D10: AT(0xFE7F5D10)
|
||||
{
|
||||
KEEP(*(.ofs2))
|
||||
} > OFS
|
||||
.ofs3 0xFE7F5D20: AT(0xFE7F5D20)
|
||||
{
|
||||
KEEP(*(.ofs3))
|
||||
} > OFS
|
||||
.ofs4 0xFE7F5D40: AT(0xFE7F5D40)
|
||||
{
|
||||
KEEP(*(.ofs4))
|
||||
} > OFS
|
||||
.ofs5 0xFE7F5D48: AT(0xFE7F5D48)
|
||||
{
|
||||
KEEP(*(.ofs5))
|
||||
} > OFS
|
||||
.ofs6 0xFE7F5D50: AT(0xFE7F5D50)
|
||||
{
|
||||
KEEP(*(.ofs6))
|
||||
} > OFS
|
||||
.ofs7 0xFE7F5D64: AT(0xFE7F5D64)
|
||||
{
|
||||
KEEP(*(.ofs7))
|
||||
} > OFS
|
||||
.ofs8 0xFE7F5D70: AT(0xFE7F5D70)
|
||||
{
|
||||
KEEP(*(.ofs8))
|
||||
} > OFS
|
||||
}
|
270
hw/bsp/rx/boards/rx65n_cloud_kit/rx65n_cloud_kit.c
Normal file
270
hw/bsp/rx/boards/rx65n_cloud_kit/rx65n_cloud_kit.c
Normal file
@@ -0,0 +1,270 @@
|
||||
/*
|
||||
* The MIT License (MIT)
|
||||
*
|
||||
* Copyright (c) 2021, Koji Kitayama
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||
* of this software and associated documentation files (the "Software"), to deal
|
||||
* in the Software without restriction, including without limitation the rights
|
||||
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
||||
* copies of the Software, and to permit persons to whom the Software is
|
||||
* furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in
|
||||
* all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
|
||||
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
|
||||
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
|
||||
* THE SOFTWARE.
|
||||
*
|
||||
* This file is part of the TinyUSB stack.
|
||||
*/
|
||||
|
||||
#include "bsp/board.h"
|
||||
#include "iodefine.h"
|
||||
#include "interrupt_handlers.h"
|
||||
|
||||
#define IRQ_PRIORITY_CMT0 5
|
||||
#define IRQ_PRIORITY_USBI0 6
|
||||
#define IRQ_PRIORITY_SCI5 5
|
||||
|
||||
#define SYSTEM_PRCR_PRC1 (1<<1)
|
||||
#define SYSTEM_PRCR_PRKEY (0xA5u<<8)
|
||||
|
||||
#define CMT_PCLK 60000000
|
||||
#define CMT_CMCR_CKS_DIV_128 2
|
||||
#define CMT_CMCR_CMIE (1<<6)
|
||||
#define MPC_PFS_ISEL (1<<6)
|
||||
|
||||
#define SCI_PCLK 60000000
|
||||
#define SCI_SSR_FER (1<<4)
|
||||
#define SCI_SSR_ORER (1<<5)
|
||||
|
||||
#define SCI_SCR_TEIE (1u<<2)
|
||||
#define SCI_SCR_RE (1u<<4)
|
||||
#define SCI_SCR_TE (1u<<5)
|
||||
#define SCI_SCR_RIE (1u<<6)
|
||||
#define SCI_SCR_TIE (1u<<7)
|
||||
#define INT_Excep_SCI5_TEI5 INT_Excep_ICU_GROUPBL0
|
||||
|
||||
#define IRQ_USB0_USBI0 62
|
||||
#define SLIBR_USBI0 SLIBR185
|
||||
#define IPR_USB0_USBI0 IPR_PERIB_INTB185
|
||||
#define INT_Excep_USB0_USBI0 INT_Excep_PERIB_INTB185
|
||||
|
||||
void HardwareSetup(void)
|
||||
{
|
||||
FLASH.ROMCIV.WORD = 1;
|
||||
while (FLASH.ROMCIV.WORD) ;
|
||||
FLASH.ROMCE.WORD = 1;
|
||||
while (!FLASH.ROMCE.WORD) ;
|
||||
|
||||
SYSTEM.PRCR.WORD = 0xA503u;
|
||||
if (!SYSTEM.RSTSR1.BYTE) {
|
||||
RTC.RCR4.BYTE = 0;
|
||||
RTC.RCR3.BYTE = 12;
|
||||
while (12 != RTC.RCR3.BYTE) ;
|
||||
}
|
||||
SYSTEM.SOSCCR.BYTE = 1;
|
||||
|
||||
if (SYSTEM.HOCOCR.BYTE) {
|
||||
SYSTEM.HOCOCR.BYTE = 0;
|
||||
while (!SYSTEM.OSCOVFSR.BIT.HCOVF) ;
|
||||
}
|
||||
SYSTEM.PLLCR.WORD = 0x1D10u; /* HOCO x 15 */
|
||||
SYSTEM.PLLCR2.BYTE = 0;
|
||||
while (!SYSTEM.OSCOVFSR.BIT.PLOVF) ;
|
||||
|
||||
SYSTEM.SCKCR.LONG = 0x21C11222u;
|
||||
SYSTEM.SCKCR2.WORD = 0x0041u;
|
||||
SYSTEM.ROMWT.BYTE = 0x02u;
|
||||
while (0x02u != SYSTEM.ROMWT.BYTE) ;
|
||||
SYSTEM.SCKCR3.WORD = 0x400u;
|
||||
SYSTEM.PRCR.WORD = 0xA500u;
|
||||
}
|
||||
|
||||
//--------------------------------------------------------------------+
|
||||
// SCI handling
|
||||
//--------------------------------------------------------------------+
|
||||
typedef struct {
|
||||
uint8_t *buf;
|
||||
uint32_t cnt;
|
||||
} sci_buf_t;
|
||||
static volatile sci_buf_t sci_buf[2];
|
||||
|
||||
void INT_Excep_SCI5_TXI5(void)
|
||||
{
|
||||
uint8_t *buf = sci_buf[0].buf;
|
||||
uint32_t cnt = sci_buf[0].cnt;
|
||||
|
||||
if (!buf || !cnt) {
|
||||
SCI5.SCR.BYTE &= ~(SCI_SCR_TEIE | SCI_SCR_TE | SCI_SCR_TIE);
|
||||
return;
|
||||
}
|
||||
SCI5.TDR = *buf;
|
||||
if (--cnt) {
|
||||
++buf;
|
||||
} else {
|
||||
buf = NULL;
|
||||
SCI5.SCR.BIT.TIE = 0;
|
||||
SCI5.SCR.BIT.TEIE = 1;
|
||||
}
|
||||
sci_buf[0].buf = buf;
|
||||
sci_buf[0].cnt = cnt;
|
||||
}
|
||||
|
||||
void INT_Excep_SCI5_TEI5(void)
|
||||
{
|
||||
SCI5.SCR.BYTE &= ~(SCI_SCR_TEIE | SCI_SCR_TE | SCI_SCR_TIE);
|
||||
}
|
||||
|
||||
void INT_Excep_SCI5_RXI5(void)
|
||||
{
|
||||
uint8_t *buf = sci_buf[1].buf;
|
||||
uint32_t cnt = sci_buf[1].cnt;
|
||||
|
||||
if (!buf || !cnt ||
|
||||
(SCI5.SSR.BYTE & (SCI_SSR_FER | SCI_SSR_ORER))) {
|
||||
sci_buf[1].buf = NULL;
|
||||
SCI5.SSR.BYTE = 0;
|
||||
SCI5.SCR.BYTE &= ~(SCI_SCR_RE | SCI_SCR_RIE);
|
||||
return;
|
||||
}
|
||||
*buf = SCI5.RDR;
|
||||
if (--cnt) {
|
||||
++buf;
|
||||
} else {
|
||||
buf = NULL;
|
||||
SCI5.SCR.BYTE &= ~(SCI_SCR_RE | SCI_SCR_RIE);
|
||||
}
|
||||
sci_buf[1].buf = buf;
|
||||
sci_buf[1].cnt = cnt;
|
||||
}
|
||||
|
||||
//--------------------------------------------------------------------+
|
||||
// Forward USB interrupt events to TinyUSB IRQ Handler
|
||||
//--------------------------------------------------------------------+
|
||||
void INT_Excep_USB0_USBI0(void)
|
||||
{
|
||||
tud_int_handler(0);
|
||||
}
|
||||
|
||||
void board_init(void)
|
||||
{
|
||||
/* setup software configurable interrupts */
|
||||
ICU.SLIBR_USBI0.BYTE = IRQ_USB0_USBI0;
|
||||
ICU.SLIPRCR.BYTE = 1;
|
||||
|
||||
#if CFG_TUSB_OS == OPT_OS_NONE
|
||||
/* Enable CMT0 */
|
||||
SYSTEM.PRCR.WORD = SYSTEM_PRCR_PRKEY | SYSTEM_PRCR_PRC1;
|
||||
MSTP(CMT0) = 0;
|
||||
SYSTEM.PRCR.WORD = SYSTEM_PRCR_PRKEY;
|
||||
/* Setup 1ms tick timer */
|
||||
CMT0.CMCNT = 0;
|
||||
CMT0.CMCOR = CMT_PCLK / 1000 / 128;
|
||||
CMT0.CMCR.WORD = CMT_CMCR_CMIE | CMT_CMCR_CKS_DIV_128;
|
||||
IR(CMT0, CMI0) = 0;
|
||||
IPR(CMT0, CMI0) = IRQ_PRIORITY_CMT0;
|
||||
IEN(CMT0, CMI0) = 1;
|
||||
CMT.CMSTR0.BIT.STR0 = 1;
|
||||
#endif
|
||||
|
||||
/* Unlock MPC registers */
|
||||
MPC.PWPR.BIT.B0WI = 0;
|
||||
MPC.PWPR.BIT.PFSWE = 1;
|
||||
// SW PB1
|
||||
PORTB.PMR.BIT.B1 = 0U;
|
||||
PORTB.PDR.BIT.B1 = 0U;
|
||||
// LED PD6
|
||||
PORTD.PODR.BIT.B6 = 1U;
|
||||
PORTD.ODR1.BIT.B4 = 1U;
|
||||
PORTD.PMR.BIT.B6 = 0U;
|
||||
PORTD.PDR.BIT.B6 = 1U;
|
||||
/* UART TXD5 => PA4, RXD5 => PA3 */
|
||||
PORTA.PMR.BIT.B4 = 1U;
|
||||
PORTA.PCR.BIT.B4 = 1U;
|
||||
MPC.PA4PFS.BYTE = 0b01010;
|
||||
PORTA.PMR.BIT.B3 = 1U;
|
||||
MPC.PA5PFS.BYTE = 0b01010;
|
||||
/* USB VBUS -> P16 */
|
||||
PORT1.PMR.BIT.B6 = 1U;
|
||||
MPC.P16PFS.BYTE = MPC_PFS_ISEL | 0b10001;
|
||||
/* Lock MPC registers */
|
||||
MPC.PWPR.BIT.PFSWE = 0;
|
||||
MPC.PWPR.BIT.B0WI = 1;
|
||||
|
||||
/* Enable SCI5 */
|
||||
SYSTEM.PRCR.WORD = SYSTEM_PRCR_PRKEY | SYSTEM_PRCR_PRC1;
|
||||
MSTP(SCI5) = 0;
|
||||
SYSTEM.PRCR.WORD = SYSTEM_PRCR_PRKEY;
|
||||
SCI5.SEMR.BIT.ABCS = 1;
|
||||
SCI5.SEMR.BIT.BGDM = 1;
|
||||
SCI5.BRR = (SCI_PCLK / (8 * 115200)) - 1;
|
||||
IR(SCI5, RXI5) = 0;
|
||||
IR(SCI5, TXI5) = 0;
|
||||
IS(SCI5, TEI5) = 0;
|
||||
IR(ICU, GROUPBL0) = 0;
|
||||
IPR(SCI5, RXI5) = IRQ_PRIORITY_SCI5;
|
||||
IPR(SCI5, TXI5) = IRQ_PRIORITY_SCI5;
|
||||
IPR(ICU,GROUPBL0) = IRQ_PRIORITY_SCI5;
|
||||
IEN(SCI5, RXI5) = 1;
|
||||
IEN(SCI5, TXI5) = 1;
|
||||
IEN(ICU,GROUPBL0) = 1;
|
||||
EN(SCI5, TEI5) = 1;
|
||||
|
||||
/* setup USBI0 interrupt. */
|
||||
IR(USB0, USBI0) = 0;
|
||||
IPR(USB0, USBI0) = IRQ_PRIORITY_USBI0;
|
||||
}
|
||||
|
||||
//--------------------------------------------------------------------+
|
||||
// Board porting API
|
||||
//--------------------------------------------------------------------+
|
||||
|
||||
void board_led_write(bool state)
|
||||
{
|
||||
PORTD.PODR.BIT.B6 = state ? 0 : 1;
|
||||
}
|
||||
|
||||
uint32_t board_button_read(void)
|
||||
{
|
||||
return PORTB.PIDR.BIT.B1 ? 0 : 1;
|
||||
}
|
||||
|
||||
int board_uart_read(uint8_t* buf, int len)
|
||||
{
|
||||
sci_buf[1].buf = buf;
|
||||
sci_buf[1].cnt = len;
|
||||
SCI5.SCR.BYTE |= SCI_SCR_RE | SCI_SCR_RIE;
|
||||
while (SCI5.SCR.BIT.RE) ;
|
||||
return len - sci_buf[1].cnt;
|
||||
}
|
||||
|
||||
int board_uart_write(void const *buf, int len)
|
||||
{
|
||||
sci_buf[0].buf = (uint8_t*)buf;
|
||||
sci_buf[0].cnt = len;
|
||||
SCI5.SCR.BYTE |= SCI_SCR_TE | SCI_SCR_TIE;
|
||||
while (SCI5.SCR.BIT.TE) ;
|
||||
return len;
|
||||
}
|
||||
|
||||
#if CFG_TUSB_OS == OPT_OS_NONE
|
||||
volatile uint32_t system_ticks = 0;
|
||||
void INT_Excep_CMT0_CMI0(void)
|
||||
{
|
||||
++system_ticks;
|
||||
}
|
||||
|
||||
uint32_t board_millis(void)
|
||||
{
|
||||
return system_ticks;
|
||||
}
|
||||
#else
|
||||
uint32_t SystemCoreClock = 120000000;
|
||||
#endif
|
46
hw/bsp/rx/family.mk
Normal file
46
hw/bsp/rx/family.mk
Normal file
@@ -0,0 +1,46 @@
|
||||
DEPS_SUBMODULES += hw/mcu/renesas/rx
|
||||
|
||||
# Cross Compiler for RX
|
||||
CROSS_COMPILE = rx-elf-
|
||||
|
||||
include $(TOP)/$(BOARD_PATH)/board.mk
|
||||
|
||||
CFLAGS += \
|
||||
-nostartfiles \
|
||||
-ffunction-sections \
|
||||
-fdata-sections \
|
||||
-fshort-enums \
|
||||
-mlittle-endian-data \
|
||||
|
||||
RX_NEWLIB ?= 1
|
||||
|
||||
ifeq ($(CMDEXE),1)
|
||||
OPTLIBINC="$(shell for /F "usebackq delims=" %%i in (`where rx-elf-gcc`) do echo %%~dpi..\rx-elf\optlibinc)"
|
||||
else
|
||||
OPTLIBINC=$(shell dirname `which rx-elf-gcc`)../rx-elf/optlibinc
|
||||
endif
|
||||
|
||||
ifeq ($(RX_NEWLIB),1)
|
||||
CFLAGS += -DSSIZE_MAX=__INT_MAX__
|
||||
else
|
||||
# setup for optlib
|
||||
CFLAGS += -nostdinc \
|
||||
-isystem $(OPTLIBINC) \
|
||||
-DLWIP_NO_INTTYPES_H
|
||||
|
||||
LIBS += -loptc -loptm
|
||||
endif
|
||||
|
||||
SRC_C += \
|
||||
src/portable/renesas/usba/dcd_usba.c \
|
||||
$(MCU_DIR)/vects.c
|
||||
|
||||
INC += \
|
||||
$(TOP)/$(BOARD_PATH) \
|
||||
$(TOP)/$(MCU_DIR)
|
||||
|
||||
SRC_S += $(MCU_DIR)/start.S
|
||||
|
||||
$(BUILD)/$(PROJECT).mot: $(BUILD)/$(PROJECT).elf
|
||||
@echo CREATE $@
|
||||
$(OBJCOPY) -O srec -I elf32-rx-be-ns $^ $@
|
Reference in New Issue
Block a user