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Add a note about data cache.

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HiFiPhile
2024-09-24 21:30:16 +02:00
parent 6a15e7875c
commit e483c6a2ad
1 changed files with 4 additions and 0 deletions
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4
src/tusb_option.h
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@@ -243,6 +243,10 @@
//--------------------------------------------------------------------+ //--------------------------------------------------------------------+
// DWC2 controller: use DMA for data transfer // DWC2 controller: use DMA for data transfer
// For processors with data cache enabled, USB endpoint buffer region
// (defined by CFG_TUSB_MEM_SECTION) must be declared as non-cacheable.
// For example, on Cortex-M7 the MPU region can be configured as normal
// non-cacheable, with RASR register value: TEX=1 C=0 B=0 S=0.
#ifndef CFG_TUD_DWC2_DMA #ifndef CFG_TUD_DWC2_DMA
#define CFG_TUD_DWC2_DMA 0 #define CFG_TUD_DWC2_DMA 0
#endif #endif