rename to hal_dcd_pipe_clear_stall()
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@@ -378,15 +378,13 @@ void hal_dcd_pipe_stall(endpoint_handle_t edpt_hdl)
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(*reg_control) |= ENDPTCTRL_MASK_STALL << (edpt_hdl.index & 0x01 ? 16 : 0);
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}
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tusb_error_t dcd_pipe_clear_stall(uint8_t coreid, uint8_t edpt_addr)
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void hal_dcd_pipe_clear_stall(uint8_t coreid, uint8_t edpt_addr)
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{
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volatile uint32_t * reg_control = get_reg_control_addr(coreid, edpt_addr2phy(edpt_addr));
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// data toggle also need to be reset
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(*reg_control) |= ENDPTCTRL_MASK_TOGGLE_RESET << ((edpt_addr & TUSB_DIR_DEV_TO_HOST_MASK) ? 16 : 0);
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(*reg_control) &= ~(ENDPTCTRL_MASK_STALL << ((edpt_addr & TUSB_DIR_DEV_TO_HOST_MASK) ? 16 : 0));
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return TUSB_ERROR_NONE;
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}
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bool hal_dcd_pipe_open(uint8_t coreid, tusb_descriptor_endpoint_t const * p_endpoint_desc, endpoint_handle_t* eh)
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