add buffer note for host msc api
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@@ -54,13 +54,12 @@ typedef struct {
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uint8_t itf_num;
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uint8_t ep_in;
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uint8_t ep_out;
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uint8_t max_lun;
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volatile bool configured; // Receive SET_CONFIGURE
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volatile bool mounted; // Enumeration is complete
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//------------- SCSI -------------//
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// SCSI command data
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uint8_t stage;
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void* buffer;
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tuh_msc_complete_cb_t complete_cb;
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@@ -82,7 +81,7 @@ CFG_TUH_MEM_SECTION static msch_epbuf_t _msch_epbuf[CFG_TUH_DEVICE_MAX];
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// Epbuf for enumeration, shared for all devices
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CFG_TUH_MEM_SECTION static struct {
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TUH_EPBUF_DEF(buf, 32); // TODO make this configurable
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TUH_EPBUF_DEF(buf, 32);
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} _msch_enum_buf;
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TU_ATTR_ALWAYS_INLINE static inline msch_interface_t* get_itf(uint8_t daddr) {
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@@ -141,10 +140,10 @@ bool tuh_msc_scsi_command(uint8_t daddr, msc_cbw_t const* cbw, void* data,
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msch_epbuf_t* epbuf = get_epbuf(daddr);
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epbuf->cbw = *cbw;
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p_msc->stage = MSC_STAGE_CMD;
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p_msc->buffer = data;
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p_msc->complete_cb = complete_cb;
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p_msc->complete_arg = arg;
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p_msc->stage = MSC_STAGE_CMD;
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if (!usbh_edpt_xfer(daddr, p_msc->ep_out, (uint8_t*) &epbuf->cbw, sizeof(msc_cbw_t))) {
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usbh_edpt_release(daddr, p_msc->ep_out);
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@@ -292,6 +291,7 @@ bool tuh_msc_reset(uint8_t dev_addr) {
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//--------------------------------------------------------------------+
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bool msch_init(void) {
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TU_LOG_DRV("sizeof(msch_interface_t) = %u\r\n", sizeof(msch_interface_t));
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TU_LOG_DRV("sizeof(msch_epbuf_t) = %u\r\n", sizeof(msch_epbuf_t));
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tu_memclr(_msch_itf, sizeof(_msch_itf));
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return true;
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}
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@@ -325,18 +325,15 @@ bool msch_xfer_cb(uint8_t dev_addr, uint8_t ep_addr, xfer_result_t event, uint32
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case MSC_STAGE_CMD:
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// Must be Command Block
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TU_ASSERT(ep_addr == p_msc->ep_out && event == XFER_RESULT_SUCCESS && xferred_bytes == sizeof(msc_cbw_t));
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if (cbw->total_bytes && p_msc->buffer) {
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// Data stage if any
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p_msc->stage = MSC_STAGE_DATA;
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uint8_t const ep_data = (cbw->dir & TUSB_DIR_IN_MASK) ? p_msc->ep_in : p_msc->ep_out;
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TU_ASSERT(usbh_edpt_xfer(dev_addr, ep_data, p_msc->buffer, (uint16_t) cbw->total_bytes));
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} else {
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// Status stage
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p_msc->stage = MSC_STAGE_STATUS;
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TU_ASSERT(usbh_edpt_xfer(dev_addr, p_msc->ep_in, (uint8_t*) csw, (uint16_t) sizeof(msc_csw_t)));
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break;
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}
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break;
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TU_ATTR_FALLTHROUGH; // fallthrough to status stage
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case MSC_STAGE_DATA:
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// Status stage
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@@ -73,10 +73,12 @@ uint32_t tuh_msc_get_block_size(uint8_t dev_addr, uint8_t lun);
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// Perform a full SCSI command (cbw, data, csw) in non-blocking manner.
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// Complete callback is invoked when SCSI op is complete.
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// return true if success, false if there is already pending operation.
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// NOTE: buffer must be accessible by USB/DMA controller, aligned correctly and multiple of cache line if enabled
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bool tuh_msc_scsi_command(uint8_t daddr, msc_cbw_t const* cbw, void* data, tuh_msc_complete_cb_t complete_cb, uintptr_t arg);
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// Perform SCSI Inquiry command
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// Complete callback is invoked when SCSI op is complete.
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// NOTE: response must be accessible by USB/DMA controller, aligned correctly and multiple of cache line if enabled
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bool tuh_msc_inquiry(uint8_t dev_addr, uint8_t lun, scsi_inquiry_resp_t* response, tuh_msc_complete_cb_t complete_cb, uintptr_t arg);
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// Perform SCSI Test Unit Ready command
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@@ -85,14 +87,17 @@ bool tuh_msc_test_unit_ready(uint8_t dev_addr, uint8_t lun, tuh_msc_complete_cb_
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// Perform SCSI Request Sense 10 command
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// Complete callback is invoked when SCSI op is complete.
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// NOTE: response must be accessible by USB/DMA controller, aligned correctly and multiple of cache line if enabled
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bool tuh_msc_request_sense(uint8_t dev_addr, uint8_t lun, void *response, tuh_msc_complete_cb_t complete_cb, uintptr_t arg);
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// Perform SCSI Read 10 command. Read n blocks starting from LBA to buffer
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// Complete callback is invoked when SCSI op is complete.
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// NOTE: buffer must be accessible by USB/DMA controller, aligned correctly and multiple of cache line if enabled
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bool tuh_msc_read10(uint8_t dev_addr, uint8_t lun, void * buffer, uint32_t lba, uint16_t block_count, tuh_msc_complete_cb_t complete_cb, uintptr_t arg);
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// Perform SCSI Write 10 command. Write n blocks starting from LBA to device
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// Complete callback is invoked when SCSI op is complete.
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// NOTE: buffer must be accessible by USB/DMA controller, aligned correctly and multiple of cache line if enabled
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bool tuh_msc_write10(uint8_t dev_addr, uint8_t lun, void const * buffer, uint32_t lba, uint16_t block_count, tuh_msc_complete_cb_t complete_cb, uintptr_t arg);
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// Perform SCSI Read Capacity 10 command
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