From eaf9cc1beb6f5e34683debe531c7fa4d012c47b2 Mon Sep 17 00:00:00 2001 From: hathach Date: Sat, 17 Aug 2024 13:31:31 +0700 Subject: [PATCH] more refactor to simplify musb driver --- src/common/tusb_mcu.h | 2 + src/portable/mentor/musb/dcd_musb.c | 176 +- src/portable/mentor/musb/musb_max32.h | 66 +- src/portable/mentor/musb/musb_ti.h | 47 +- src/portable/mentor/musb/musb_type.h | 2389 ++++++++++--------------- 5 files changed, 1091 insertions(+), 1589 deletions(-) diff --git a/src/common/tusb_mcu.h b/src/common/tusb_mcu.h index 7ec3c5842..0180fc466 100644 --- a/src/common/tusb_mcu.h +++ b/src/common/tusb_mcu.h @@ -309,6 +309,7 @@ #elif TU_CHECK_MCU(OPT_MCU_MSP432E4, OPT_MCU_TM4C123, OPT_MCU_TM4C129) #define TUP_USBIP_MUSB + #define TUP_USBIP_MUSB_TI #define TUP_DCD_ENDPOINT_MAX 8 //--------------------------------------------------------------------+ @@ -474,6 +475,7 @@ //--------------------------------------------------------------------+ #elif TU_CHECK_MCU(OPT_MCU_MAX32650, OPT_MCU_MAX32666, OPT_MCU_MAX32690, OPT_MCU_MAX78002) #define TUP_USBIP_MUSB + #define TUP_USBIP_MUSB_ADI #define TUP_DCD_ENDPOINT_MAX 12 #define TUP_RHPORT_HIGHSPEED 1 diff --git a/src/portable/mentor/musb/dcd_musb.c b/src/portable/mentor/musb/dcd_musb.c index 48f6e9d97..36690c952 100644 --- a/src/portable/mentor/musb/dcd_musb.c +++ b/src/portable/mentor/musb/dcd_musb.c @@ -41,10 +41,10 @@ _Pragma("GCC diagnostic ignored \"-Waddress-of-packed-member\""); // Following symbols must be defined by port header // - musb_dcd_int_enable/disable/clear/get_enable // - musb_dcd_int_handler_enter/exit -// - musb_dcd_setup_fifo/reset_fifo: Configuration of the EP's FIFO -#if TU_CHECK_MCU(OPT_MCU_MSP432E4, OPT_MCU_TM4C123, OPT_MCU_TM4C129) +// - musb_dcd_setup_fifo: Configuration of the EP's FIFO +#if defined(TUP_USBIP_MUSB_TI) #include "musb_ti.h" -#elif TU_CHECK_MCU(OPT_MCU_MAX32690, OPT_MCU_MAX32650, OPT_MCU_MAX32666, OPT_MCU_MAX78002) +#elif defined(TUP_USBIP_MUSB_ADI) #include "musb_max32.h" #else #error "Unsupported MCU" @@ -52,6 +52,8 @@ _Pragma("GCC diagnostic ignored \"-Waddress-of-packed-member\""); #define MUSB_REGS(rhport) ((musb_regs_t*) MUSB_BASES[rhport]) +#define MUSB_DEBUG 2 + /*------------------------------------------------------------------ * MACRO TYPEDEF CONSTANT ENUM DECLARATION *------------------------------------------------------------------*/ @@ -86,6 +88,18 @@ typedef struct *------------------------------------------------------------------*/ static dcd_data_t _dcd; +TU_ATTR_ALWAYS_INLINE static inline void fifo_reset(musb_regs_t* musb, unsigned epnum, unsigned dir_in) { + musb->index = epnum; + const uint8_t is_rx = 1 - dir_in; + +#if MUSB_CFG_DYNAMIC_FIFO + musb->fifo_size[is_rx] = 0; + musb->fifo_addr[is_rx] = 0; +#elif defined(TUP_USBIP_MUSB_ADI) + // Analog have custom double buffered in csrh register, disable it + musb->indexed_csr.maxp_csr[is_rx].csrh |= MUSB_CSRH_DISABLE_DOUBLE_PACKET(is_rx); +#endif +} static void pipe_write_packet(void *buf, volatile void *fifo, unsigned len) { @@ -363,13 +377,13 @@ static void process_ep0(uint8_t rhport) /* Received SETUP or DATA OUT packet */ if (req == REQUEST_TYPE_INVALID) { /* SETUP */ - TU_ASSERT(sizeof(tusb_control_request_t) == ep_csr->rx_count,); + TU_ASSERT(sizeof(tusb_control_request_t) == ep_csr->count0,); process_setup_packet(rhport); return; } if (_dcd.pipe0.buf) { /* DATA OUT */ - const unsigned vld = ep_csr->rx_count; + const unsigned vld = ep_csr->count0; const unsigned rem = _dcd.pipe0.remaining; const unsigned len = TU_MIN(TU_MIN(rem, 64), vld); volatile void *fifo_ptr = &musb_regs->fifo[0]; @@ -445,47 +459,70 @@ static void process_edpt_n(uint8_t rhport, uint_fast8_t ep_addr) } } -static void process_bus_reset(uint8_t rhport) -{ - musb_regs_t* musb_regs = MUSB_REGS(rhport); - /* When bmRequestType is REQUEST_TYPE_INVALID(0xFF), - * a control transfer state is SETUP or STATUS stage. */ +// Upon BUS RESET is detected, hardware havs already done: +// faddr = 0, index = 0, flushes all ep fifos, clears all ep csr, enabled all ep interrupts +static void process_bus_reset(uint8_t rhport) { + musb_regs_t* musb = MUSB_REGS(rhport); + /* When bmRequestType is REQUEST_TYPE_INVALID(0xFF), a control transfer state is SETUP or STATUS stage. */ _dcd.setup_packet.bmRequestType = REQUEST_TYPE_INVALID; _dcd.status_out = 0; /* When pipe0.buf has not NULL, DATA stage works in progress. */ _dcd.pipe0.buf = NULL; - musb_regs->intr_txen = 1; /* Enable only EP0 */ - musb_regs->intr_rxen = 0; + musb->intr_txen = 1; /* Enable only EP0 */ + musb->intr_rxen = 0; /* Clear FIFO settings */ for (unsigned i = 1; i < TUP_DCD_ENDPOINT_MAX; ++i) { - musb_dcd_reset_fifo(rhport, i, 0); - musb_dcd_reset_fifo(rhport, i, 1); + fifo_reset(musb, i, 0); + fifo_reset(musb, i, 1); } - dcd_event_bus_reset(rhport, (musb_regs->power & USB_POWER_HSMODE) ? TUSB_SPEED_HIGH : TUSB_SPEED_FULL, true); + dcd_event_bus_reset(rhport, (musb->power & USB_POWER_HSMODE) ? TUSB_SPEED_HIGH : TUSB_SPEED_FULL, true); } /*------------------------------------------------------------------ * Device API *------------------------------------------------------------------*/ -void dcd_init(uint8_t rhport) -{ +#if CFG_TUSB_DEBUG >= MUSB_DEBUG +void print_musb_info(musb_regs_t* musb_regs) { + // print version, epinfo, raminfo, config_data0, fifo_size + TU_LOG1("musb version = %u.%u\r\n", musb_regs->hwvers_bit.major, musb_regs->hwvers_bit.minor); + TU_LOG1("Number of endpoints: %u TX, %u RX\r\n", musb_regs->epinfo_bit.tx_ep_num, musb_regs->epinfo_bit.rx_ep_num); + TU_LOG1("RAM Info: %u DMA Channel, %u RAM address width\r\n", musb_regs->raminfo_bit.dma_channel, musb_regs->raminfo_bit.ram_bits); + + musb_regs->index = 0; + TU_LOG1("config_data0 = 0x%x\r\n", musb_regs->indexed_csr.config_data0); + +#if MUSB_CFG_DYNAMIC_FIFO + TU_LOG1("Dynamic FIFO configuration\r\n"); +#else + for (uint8_t i=1; i <= musb_regs->epinfo_bit.tx_ep_num; i++) { + musb_regs->index = i; + TU_LOG1("FIFO %u Size: TX %u RX %u\r\n", i, musb_regs->indexed_csr.fifo_size_bit.tx, musb_regs->indexed_csr.fifo_size_bit.rx); + } +#endif +} +#endif + +void dcd_init(uint8_t rhport) { musb_regs_t* musb_regs = MUSB_REGS(rhport); - musb_regs->intrusben |= USB_IE_SUSPND; + +#if CFG_TUSB_DEBUG >= MUSB_DEBUG + print_musb_info(musb_regs); +#endif + + musb_regs->intr_usben |= USB_IE_SUSPND; musb_dcd_int_clear(rhport); musb_dcd_phy_init(rhport); dcd_connect(rhport); } -void dcd_int_enable(uint8_t rhport) -{ +void dcd_int_enable(uint8_t rhport) { musb_dcd_int_enable(rhport); } -void dcd_int_disable(uint8_t rhport) -{ +void dcd_int_disable(uint8_t rhport) { musb_dcd_int_disable(rhport); } @@ -559,25 +596,17 @@ bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const * ep_desc) musb_regs_t* musb_regs = MUSB_REGS(rhport); musb_ep_csr_t* ep_csr = get_ep_csr(musb_regs, epn); - if (dir_in) { - ep_csr->tx_maxp = mps; - ep_csr->tx_csrh = (xfer == TUSB_XFER_ISOCHRONOUS) ? USB_TXCSRH1_ISO : 0; - if (ep_csr->tx_csrl & USB_TXCSRL1_TXRDY) { - ep_csr->tx_csrl = USB_TXCSRL1_CLRDT | USB_TXCSRL1_FLUSH; - } else { - ep_csr->tx_csrl = USB_TXCSRL1_CLRDT; - } - musb_regs->intr_txen |= TU_BIT(epn); - } else { - ep_csr->rx_maxp = mps; - ep_csr->rx_csrh = (xfer == TUSB_XFER_ISOCHRONOUS) ? USB_RXCSRH1_ISO : 0; - if (ep_csr->rx_csrl & USB_RXCSRL1_RXRDY) { - ep_csr->rx_csrl = USB_RXCSRL1_CLRDT | USB_RXCSRL1_FLUSH; - } else { - ep_csr->rx_csrl = USB_RXCSRL1_CLRDT; - } - musb_regs->intr_rxen |= TU_BIT(epn); + + const uint8_t is_rx = 1 - dir_in; + ep_csr->maxp_csr[is_rx].maxp = mps; + ep_csr->maxp_csr[is_rx].csrh = (xfer == TUSB_XFER_ISOCHRONOUS) ? USB_RXCSRH1_ISO : 0; + + uint8_t csrl = MUSB_CSRL_CLEAR_DATA_TOGGLE(is_rx); + if (ep_csr->maxp_csr[is_rx].csrl & MUSB_CSRL_PACKET_READY(is_rx)) { + csrl |= MUSB_CSRL_FLUSH_FIFO(is_rx); } + ep_csr->maxp_csr[is_rx].csrl = csrl; + musb_regs->intren_ep[is_rx] |= TU_BIT(epn); /* Setup FIFO */ musb_dcd_setup_fifo(rhport, epn, dir_in, mps); @@ -587,13 +616,13 @@ bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const * ep_desc) void dcd_edpt_close_all(uint8_t rhport) { - musb_regs_t* musb_regs = MUSB_REGS(rhport); + musb_regs_t* musb = MUSB_REGS(rhport); unsigned const ie = musb_dcd_get_int_enable(rhport); musb_dcd_int_disable(rhport); - musb_regs->intr_txen = 1; /* Enable only EP0 */ - musb_regs->intr_rxen = 0; + musb->intr_txen = 1; /* Enable only EP0 */ + musb->intr_rxen = 0; for (unsigned i = 1; i < TUP_DCD_ENDPOINT_MAX; ++i) { - musb_ep_csr_t* ep_csr = get_ep_csr(musb_regs, i); + musb_ep_csr_t* ep_csr = get_ep_csr(musb, i); ep_csr->tx_maxp = 0; ep_csr->tx_csrh = 0; if (ep_csr->tx_csrl & USB_TXCSRL1_TXRDY) @@ -609,8 +638,8 @@ void dcd_edpt_close_all(uint8_t rhport) ep_csr->rx_csrl = USB_RXCSRL1_CLRDT; } - musb_dcd_reset_fifo(rhport, i, 0); - musb_dcd_reset_fifo(rhport, i, 1); + fifo_reset(musb, i, 0); + fifo_reset(musb, i, 1); } if (ie) musb_dcd_int_enable(rhport); @@ -620,12 +649,12 @@ void dcd_edpt_close(uint8_t rhport, uint8_t ep_addr) { unsigned const epn = tu_edpt_number(ep_addr); unsigned const dir_in = tu_edpt_dir(ep_addr); - musb_regs_t* musb_regs = MUSB_REGS(rhport); - musb_ep_csr_t* ep_csr = get_ep_csr(musb_regs, epn); + musb_regs_t* musb = MUSB_REGS(rhport); + musb_ep_csr_t* ep_csr = get_ep_csr(musb, epn); unsigned const ie = musb_dcd_get_int_enable(rhport); musb_dcd_int_disable(rhport); if (dir_in) { - musb_regs->intr_txen &= ~TU_BIT(epn); + musb->intr_txen &= ~TU_BIT(epn); ep_csr->tx_maxp = 0; ep_csr->tx_csrh = 0; if (ep_csr->tx_csrl & USB_TXCSRL1_TXRDY) { @@ -634,7 +663,7 @@ void dcd_edpt_close(uint8_t rhport, uint8_t ep_addr) ep_csr->tx_csrl = USB_TXCSRL1_CLRDT; } } else { - musb_regs->intr_rxen &= ~TU_BIT(epn); + musb->intr_rxen &= ~TU_BIT(epn); ep_csr->rx_maxp = 0; ep_csr->rx_csrh = 0; if (ep_csr->rx_csrl & USB_RXCSRL1_RXRDY) { @@ -643,7 +672,7 @@ void dcd_edpt_close(uint8_t rhport, uint8_t ep_addr) ep_csr->rx_csrl = USB_RXCSRL1_CLRDT; } } - musb_dcd_reset_fifo(rhport, epn, dir_in); + fifo_reset(musb, epn, dir_in); if (ie) musb_dcd_int_enable(rhport); } @@ -726,51 +755,48 @@ void dcd_edpt_clear_stall(uint8_t rhport, uint8_t ep_addr) /*------------------------------------------------------------------- * ISR *-------------------------------------------------------------------*/ -void dcd_int_handler(uint8_t rhport) -{ - uint_fast8_t is, txis, rxis; - +void dcd_int_handler(uint8_t rhport) { //Part specific ISR setup/entry musb_dcd_int_handler_enter(rhport); musb_regs_t* musb_regs = MUSB_REGS(rhport); - - is = musb_regs->intrusb; /* read and clear interrupt status */ - txis = musb_regs->intr_tx; /* read and clear interrupt status */ - rxis = musb_regs->intr_rx; /* read and clear interrupt status */ + uint_fast8_t intr_usb = musb_regs->intr_usb; // a read will clear this interrupt status + uint_fast8_t intr_tx = musb_regs->intr_tx; // a read will clear this interrupt status + uint_fast8_t intr_rx = musb_regs->intr_rx; // a read will clear this interrupt status // TU_LOG1("D%2x T%2x R%2x\r\n", is, txis, rxis); - is &= musb_regs->intrusben; /* Clear disabled interrupts */ - if (is & USB_IS_DISCON) { + intr_usb &= musb_regs->intr_usben; /* Clear disabled interrupts */ + if (intr_usb & USB_IS_DISCON) { } - if (is & USB_IS_SOF) { + if (intr_usb & USB_IS_SOF) { dcd_event_bus_signal(rhport, DCD_EVENT_SOF, true); } - if (is & USB_IS_RESET) { + if (intr_usb & USB_IS_RESET) { process_bus_reset(rhport); } - if (is & USB_IS_RESUME) { + if (intr_usb & USB_IS_RESUME) { dcd_event_bus_signal(rhport, DCD_EVENT_RESUME, true); } - if (is & USB_IS_SUSPEND) { + if (intr_usb & USB_IS_SUSPEND) { dcd_event_bus_signal(rhport, DCD_EVENT_SUSPEND, true); } - txis &= musb_regs->intr_txen; /* Clear disabled interrupts */ - if (txis & USB_TXIE_EP0) { + intr_tx &= musb_regs->intr_txen; /* Clear disabled interrupts */ + if (intr_tx & TU_BIT(0)) { process_ep0(rhport); - txis &= ~TU_BIT(0); + intr_tx &= ~TU_BIT(0); } - while (txis) { - unsigned const num = __builtin_ctz(txis); + while (intr_tx) { + unsigned const num = __builtin_ctz(intr_tx); process_edpt_n(rhport, tu_edpt_addr(num, TUSB_DIR_IN)); - txis &= ~TU_BIT(num); + intr_tx &= ~TU_BIT(num); } - rxis &= musb_regs->intr_rxen; /* Clear disabled interrupts */ - while (rxis) { - unsigned const num = __builtin_ctz(rxis); + + intr_rx &= musb_regs->intr_rxen; /* Clear disabled interrupts */ + while (intr_rx) { + unsigned const num = __builtin_ctz(intr_rx); process_edpt_n(rhport, tu_edpt_addr(num, TUSB_DIR_OUT)); - rxis &= ~TU_BIT(num); + intr_rx &= ~TU_BIT(num); } //Part specific ISR exit diff --git a/src/portable/mentor/musb/musb_max32.h b/src/portable/mentor/musb/musb_max32.h index 43f56de3c..73f63ee2e 100644 --- a/src/portable/mentor/musb/musb_max32.h +++ b/src/portable/mentor/musb/musb_max32.h @@ -34,6 +34,8 @@ extern "C" { #include "mxc_device.h" #include "usbhs_regs.h" +#define MUSB_CFG_DYNAMIC_FIFO 0 + const uintptr_t MUSB_BASES[] = { MXC_BASE_USBHS }; #if CFG_TUD_ENABLED @@ -100,40 +102,43 @@ static inline void musb_dcd_int_handler_exit(uint8_t rhport) { } static inline void musb_dcd_phy_init(uint8_t rhport) { - //Interrupt for VBUS disconnect - musb_periph_inst[rhport]->mxm_int_en |= MXC_F_USBHS_MXM_INT_EN_NOVBUS; + (void) rhport; + mxc_usbhs_regs_t* hs_phy = MXC_USBHS; + + // Interrupt for VBUS disconnect + hs_phy->mxm_int_en |= MXC_F_USBHS_MXM_INT_EN_NOVBUS; musb_dcd_int_clear(rhport); - //Unsuspend the MAC - musb_periph_inst[rhport]->mxm_suspend = 0; + // Unsuspend the MAC + hs_phy->mxm_suspend = 0; // Configure PHY - musb_periph_inst[rhport]->m31_phy_xcfgi_31_0 = (0x1 << 3) | (0x1 << 11); - musb_periph_inst[rhport]->m31_phy_xcfgi_63_32 = 0; - musb_periph_inst[rhport]->m31_phy_xcfgi_95_64 = 0x1 << (72 - 64); - musb_periph_inst[rhport]->m31_phy_xcfgi_127_96 = 0; + hs_phy->m31_phy_xcfgi_31_0 = (0x1 << 3) | (0x1 << 11); + hs_phy->m31_phy_xcfgi_63_32 = 0; + hs_phy->m31_phy_xcfgi_95_64 = 0x1 << (72 - 64); + hs_phy->m31_phy_xcfgi_127_96 = 0; #ifdef USBHS_M31_CLOCK_RECOVERY - musb_periph_inst[rhport]->m31_phy_noncry_rstb = 1; - musb_periph_inst[rhport]->m31_phy_noncry_en = 1; - musb_periph_inst[rhport]->m31_phy_outclksel = 0; - musb_periph_inst[rhport]->m31_phy_coreclkin = 0; - musb_periph_inst[rhport]->m31_phy_xtlsel = 2; /* Select 25 MHz clock */ + hs_phy->m31_phy_noncry_rstb = 1; + hs_phy->m31_phy_noncry_en = 1; + hs_phy->m31_phy_outclksel = 0; + hs_phy->m31_phy_coreclkin = 0; + hs_phy->m31_phy_xtlsel = 2; /* Select 25 MHz clock */ #else - musb_periph_inst[rhport]->m31_phy_noncry_rstb = 0; - musb_periph_inst[rhport]->m31_phy_noncry_en = 0; - musb_periph_inst[rhport]->m31_phy_outclksel = 1; - musb_periph_inst[rhport]->m31_phy_coreclkin = 1; - musb_periph_inst[rhport]->m31_phy_xtlsel = 3; /* Select 30 MHz clock */ + hs_phy->m31_phy_noncry_rstb = 0; + hs_phy->m31_phy_noncry_en = 0; + hs_phy->m31_phy_outclksel = 1; + hs_phy->m31_phy_coreclkin = 1; + hs_phy->m31_phy_xtlsel = 3; /* Select 30 MHz clock */ #endif - musb_periph_inst[rhport]->m31_phy_pll_en = 1; - musb_periph_inst[rhport]->m31_phy_oscouten = 1; + hs_phy->m31_phy_pll_en = 1; + hs_phy->m31_phy_oscouten = 1; /* Reset PHY */ - musb_periph_inst[rhport]->m31_phy_ponrst = 0; - musb_periph_inst[rhport]->m31_phy_ponrst = 1; + hs_phy->m31_phy_ponrst = 0; + hs_phy->m31_phy_ponrst = 1; } static inline void musb_dcd_setup_fifo(uint8_t rhport, unsigned epnum, unsigned dir_in, unsigned mps) { @@ -155,23 +160,6 @@ static inline void musb_dcd_setup_fifo(uint8_t rhport, unsigned epnum, unsigned musb_periph_inst[rhport]->index = saved_index; } -static inline void musb_dcd_reset_fifo(uint8_t rhport, unsigned epnum, unsigned dir_in) { - //Most likely the caller has already grabbed the right register block. But - //as a precaution save and restore the register bank anyways - unsigned saved_index = musb_periph_inst[rhport]->index; - - musb_periph_inst[rhport]->index = epnum; - - //Disable double buffering - if (dir_in) { - musb_periph_inst[rhport]->incsru |= (MXC_F_USBHS_INCSRU_DPKTBUFDIS); - } else { - musb_periph_inst[rhport]->outcsru |= (MXC_F_USBHS_OUTCSRU_DPKTBUFDIS); - } - - musb_periph_inst[rhport]->index = saved_index; -} - #endif // CFG_TUD_ENABLED #ifdef __cplusplus diff --git a/src/portable/mentor/musb/musb_ti.h b/src/portable/mentor/musb/musb_ti.h index d1a0aa4f9..e43b3d3c0 100644 --- a/src/portable/mentor/musb/musb_ti.h +++ b/src/portable/mentor/musb/musb_ti.h @@ -42,8 +42,10 @@ #error "Unsupported MCUs" #endif -const uintptr_t MUSB_BASES[] = { USB0_BASE }; +#define MUSB_CFG_DYNAMIC_FIFO 1 +#define MUSB_CFG_DYNAMIC_FIFO_SIZE 4096 +const uintptr_t MUSB_BASES[] = { USB0_BASE }; // Header supports both device and host modes. Only include what's necessary #if CFG_TUD_ENABLED @@ -63,36 +65,28 @@ static inline void musb_dcd_phy_init(uint8_t rhport){ //Nothing to do for this part } -TU_ATTR_ALWAYS_INLINE -static inline void musb_dcd_int_enable(uint8_t rhport) -{ +TU_ATTR_ALWAYS_INLINE static inline void musb_dcd_int_enable(uint8_t rhport) { NVIC_EnableIRQ(musb_irqs[rhport]); } -TU_ATTR_ALWAYS_INLINE -static inline void musb_dcd_int_disable(uint8_t rhport) -{ +TU_ATTR_ALWAYS_INLINE static inline void musb_dcd_int_disable(uint8_t rhport) { NVIC_DisableIRQ(musb_irqs[rhport]); } -TU_ATTR_ALWAYS_INLINE -static inline unsigned musb_dcd_get_int_enable(uint8_t rhport) -{ +TU_ATTR_ALWAYS_INLINE static inline unsigned musb_dcd_get_int_enable(uint8_t rhport) { return NVIC_GetEnableIRQ(musb_irqs[rhport]); } -TU_ATTR_ALWAYS_INLINE -static inline void musb_dcd_int_clear(uint8_t rhport) -{ - NVIC_ClearPendingIRQ(musb_irqs[rhport]); +TU_ATTR_ALWAYS_INLINE static inline void musb_dcd_int_clear(uint8_t rhport) { + NVIC_ClearPendingIRQ(musb_irqs[rhport]); } -static inline void musb_dcd_int_handler_enter(uint8_t rhport){ +static inline void musb_dcd_int_handler_enter(uint8_t rhport) { (void)rhport; //Nothing to do for this part } -static inline void musb_dcd_int_handler_exit(uint8_t rhport){ +static inline void musb_dcd_int_handler_exit(uint8_t rhport) { (void)rhport; //Nothing to do for this part } @@ -102,15 +96,13 @@ typedef struct { uint_fast16_t end; /* offset of excluding the last element */ } free_block_t; -static inline free_block_t *find_containing_block(free_block_t *beg, free_block_t *end, uint_fast16_t addr) -{ +static inline free_block_t *find_containing_block(free_block_t *beg, free_block_t *end, uint_fast16_t addr) { free_block_t *cur = beg; for (; cur < end && ((addr < cur->beg) || (cur->end <= addr)); ++cur) ; return cur; } -static inline int update_free_block_list(free_block_t *blks, unsigned num, uint_fast16_t addr, uint_fast16_t size) -{ +static inline int update_free_block_list(free_block_t *blks, unsigned num, uint_fast16_t addr, uint_fast16_t size) { free_block_t *p = find_containing_block(blks, blks + num, addr); TU_ASSERT(p != blks + num, -2); if (p->beg == addr) { @@ -150,8 +142,7 @@ static inline int update_free_block_list(free_block_t *blks, unsigned num, uint_ } } -static inline unsigned free_block_size(free_block_t const *blk) -{ +static inline unsigned free_block_size(free_block_t const *blk) { return blk->end - blk->beg; } @@ -234,18 +225,6 @@ static inline void musb_dcd_setup_fifo(uint8_t rhport, unsigned epnum, unsigned } } -static inline void musb_dcd_reset_fifo(uint8_t rhport, unsigned epnum, unsigned dir_in) -{ - musb_periph_inst[rhport]->EPIDX = epnum; - if (dir_in) { - musb_periph_inst[rhport]->TXFIFOADD = 0; - musb_periph_inst[rhport]->TXFIFOSZ = 0; - } else { - musb_periph_inst[rhport]->RXFIFOADD = 0; - musb_periph_inst[rhport]->RXFIFOSZ = 0; - } -} - #endif // CFG_TUD_ENABLED #ifdef __cplusplus diff --git a/src/portable/mentor/musb/musb_type.h b/src/portable/mentor/musb/musb_type.h index 57ab2aefa..ee0187270 100644 --- a/src/portable/mentor/musb/musb_type.h +++ b/src/portable/mentor/musb/musb_type.h @@ -83,20 +83,37 @@ #define __R volatile const #endif +// 0: TX (device IN, host OUT) +// 1: RX (device OUT, host IN) typedef struct TU_ATTR_PACKED { - __IO uint16_t tx_maxp; // 0x00: TXMAXP union { - __IO uint8_t csr0l; // 0x02: CSR0 - __IO uint8_t tx_csrl; // 0x02: TX CSRL + struct { + __IO uint16_t tx_maxp; // 0x00: TXMAXP + union { + __IO uint8_t csr0l; // 0x02: CSR0 + __IO uint8_t tx_csrl; // 0x02: TX CSRL + }; + union { + __IO uint8_t csr0h; // 0x03: CSR0H + __IO uint8_t tx_csrh; // 0x03: TX CSRH + }; + + __IO uint16_t rx_maxp; // 0x04: RX MAXP + __IO uint8_t rx_csrl; // 0x06: RX CSRL + __IO uint8_t rx_csrh; // 0x07: RX CSRH + }; + + struct { + __IO uint16_t maxp; // 0x00: MAXP + __IO uint8_t csrl; // 0x02: CSRL + __IO uint8_t csrh; // 0x03: CSRH + }maxp_csr[2]; }; + union { - __IO uint8_t csr0h; // 0x03: CSR0H - __IO uint8_t tx_csrh; // 0x03: TX CSRH + __IO uint16_t count0; // 0x08: COUNT0 + __IO uint16_t rx_count; // 0x08: RX COUNT }; - __IO uint16_t rx_maxp; // 0x04: RX MAXP - __IO uint8_t rx_csrl; // 0x06: RX CSRL - __IO uint8_t rx_csrh; // 0x07: RX CSRH - __IO uint16_t rx_count; // 0x08: RX COUNT union { __IO uint8_t type0; // 0x0A: TYPE0 (host only) __IO uint8_t tx_type; // 0x0A: TX TYPE @@ -106,32 +123,71 @@ typedef struct TU_ATTR_PACKED { __IO uint8_t rx_interval; // 0x0D: RX INTERVAL __IO uint8_t reserved_0x0e; // 0x0E: Reserved union { - __IO uint8_t config_data; // 0x0F: CONFIG DATA + __IO uint8_t config_data0; // 0x0F: CONFIG DATA + struct { + __IO uint8_t utmi_data_width : 1; // [0] UTMI Data Width + __IO uint8_t softconn_en : 1; // [1] Soft Connect Enable + __IO uint8_t dynamic_fifo : 1; // [2] Dynamic FIFO Sizing + __IO uint8_t hb_tx_en : 1; // [3] High Bandwidth TX ISO Enable + __IO uint8_t hb_rx_en : 1; // [4] High Bandwidth RX ISO Enable + __IO uint8_t big_endian : 1; // [5] Big Endian + __IO uint8_t mp_tx_en : 1; // [6] Auto splitting BULK TX Enable + __IO uint8_t mp_rx_en : 1; // [7] Auto amalgamation BULK RX Enable + } config_data0_bit; + __IO uint8_t fifo_size; // 0x0F: FIFO_SIZE + struct { + __IO uint8_t tx : 4; // [3:0] TX FIFO Size + __IO uint8_t rx : 4; // [7:4] RX FIFO Size + }fifo_size_bit; }; } musb_ep_csr_t; TU_VERIFY_STATIC(sizeof(musb_ep_csr_t) == 16, "size is not correct"); -typedef struct { +typedef struct TU_ATTR_PACKED { //------------- Common -------------// __IO uint8_t faddr; // 0x00: FADDR - __IO uint8_t power; // 0x01: POWER + union { + __IO uint8_t power; // 0x01: POWER + struct { + __IO uint8_t suspend_mode_en : 1; // [0] SUSPEND Mode Enable + __IO uint8_t suspend_mode : 1; // [1] SUSPEND Mode + __IO uint8_t resume_mode : 1; // [2] RESUME + __IO uint8_t reset : 1; // [3] RESET + __IO uint8_t highspeed_mode : 1; // [4] High Speed Mode + __IO uint8_t highspeed_en : 1; // [5] High Speed Enable + __IO uint8_t soft_conn : 1; // [6] Soft Connect/Disconnect + __IO uint8_t iso_update : 1; // [7] Isochronous Update + } power_bit; + }; - __IO uint16_t intr_tx; // 0x02: INTR_TX - __IO uint16_t intr_rx; // 0x04: INTR_RX + union { + struct { + __IO uint16_t intr_tx; // 0x02: INTR_TX + __IO uint16_t intr_rx; // 0x04: INTR_RX + }; - __IO uint16_t intr_txen; // 0x06: INTR_TXEN - __IO uint16_t intr_rxen; // 0x08: INTR_RXEN + __IO uint16_t intr_ep[2]; // 0x02-0x05: INTR_EP0-1 + }; - __IO uint8_t intrusb; // 0x0A: INTRUSB - __IO uint8_t intrusben; // 0x0B: INTRUSBEN + union { + struct { + __IO uint16_t intr_txen; // 0x06: INTR_TXEN + __IO uint16_t intr_rxen; // 0x08: INTR_RXEN + }; + + __IO uint16_t intren_ep[2]; // 0x06-0x09: INTREN_EP0-1 + }; + + __IO uint8_t intr_usb; // 0x0A: INTRUSB + __IO uint8_t intr_usben; // 0x0B: INTRUSBEN __IO uint16_t frame; // 0x0C: FRAME __IO uint8_t index; // 0x0E: INDEX __IO uint8_t testmode; // 0x0F: TESTMODE - //------------- CSR (indexed) -------------// + //------------- Endpoint CSR (indexed) -------------// musb_ep_csr_t indexed_csr; // 0x10-0x1F: Indexed CSR 0-15 //------------- FIFOs -------------// @@ -142,35 +198,68 @@ typedef struct { __IO uint8_t misc; // 0x61: MISC //------------- Dynammic FIFO (indexed) -------------// - __IO uint8_t txfifo_sz; // 0x62: TXFIFO_SZ - __IO uint8_t rxfifo_sz; // 0x63: RXFIFO_SZ - __IO uint16_t txfifo_addr; // 0x64: TXFIFO_ADDR - __IO uint16_t rxfifo_addr; // 0x66: RXFIFO_ADDR - - //------------- Additional Control/Status -------------// union { - __O uint32_t vcontrol; // 0x68: VCONTROL - __IO uint32_t vstatus; // 0x68: VSTATUS + struct { + __IO uint8_t txfifo_sz; // 0x62: TXFIFO_SZ + __IO uint8_t rxfifo_sz; // 0x63: RXFIFO_SZ + }; + __IO uint8_t fifo_size[2]; + }; + + union { + struct { + __IO uint16_t txfifo_addr; // 0x64: TXFIFO_ADDR + __IO uint16_t rxfifo_addr; // 0x66: RXFIFO_ADDR + }; + __IO uint16_t fifo_addr[2]; + }; + + //------------- Additional Control and Configuration -------------// + union { + __O uint32_t vcontrol; // 0x68: PHY VCONTROL + __IO uint32_t vstatus; // 0x68: PHY VSTATUS + }; + union { + __IO uint16_t hwvers; // 0x6C: HWVERS + struct { + __IO uint16_t minor : 10; // [9:0] Minor + __IO uint16_t major : 5; // [14:10] Major + __IO uint16_t rc : 1; // [15] Release Candidate + } hwvers_bit; }; - __IO uint16_t hwvers; // 0x6c: HWVERS __R uint16_t rsv_0x6e_0x77[5]; // 0x6E-0x77: Reserved //------------- Additional Configuration -------------// - __IO uint8_t epinfo; // 0x78: EPINFO - __IO uint8_t raminfo; // 0x79: RAMINFO - __IO uint8_t softreset; // 0x7A: SOFTRESET (Analog), Link info + union { + __IO uint8_t epinfo; // 0x78: EPINFO + struct { + __IO uint8_t tx_ep_num : 4; // [3:0] TX Endpoints + __IO uint8_t rx_ep_num : 4; // [7:4] RX Endpoints + } epinfo_bit; + }; + union { + __IO uint8_t raminfo; // 0x79: RAMINFO + struct { + __IO uint8_t ram_bits : 4; // [3:0] RAM Address Bus Width + __IO uint8_t dma_channel : 4; // [7:4] DMA Channels + }raminfo_bit; + }; + union { + __IO uint8_t link_info; // 0x7A: LINK_INFO + __IO uint8_t adi_softreset; // 0x7A: AnalogDevice SOFTRESET + }; __IO uint8_t vplen; // 0x7B: VPLEN __IO uint8_t hs_eof1; // 0x7C: HS_EOF1 __IO uint8_t fs_eof1; // 0x7D: FS_EOF1 __IO uint8_t ls_eof1; // 0x7E: LS_EOF1 __IO uint8_t soft_rst; // 0x7F: SOFT_RST - //------------- Extended -------------// + //------------- Target Endpoints (multipoint option) -------------// __IO uint16_t ctuch; // 0x80: CTUCH __IO uint16_t cthsrtn; // 0x82: CTHSRTN __R uint32_t rsv_0x84_0xff[31]; // 0x84-0xFF: Reserved - //------------- Absolute CSR (used index to remap to Indexed above) -------------// + //------------- Non-Indexed Endpoint CSRs -------------// // TI tm4c can access this directly, but should use indexed_csr for portability musb_ep_csr_t ep_csr[16]; // 0x100-0x1FF: EP0-15 CSR } musb_regs_t; @@ -185,267 +274,151 @@ TU_ATTR_ALWAYS_INLINE static inline musb_ep_csr_t* get_ep_csr(musb_regs_t* musb_ return &musb_regs->indexed_csr; } -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_FADDR register. -// -//***************************************************************************** -#define USB_FADDR_M 0x0000007F // Function Address -#define USB_FADDR_S 0 +//--------------------------------------------------------------------+ +// Register Bit Field +//--------------------------------------------------------------------+ -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_POWER register. -// -//***************************************************************************** -#define USB_POWER_ISOUP 0x00000080 // Isochronous Update -#define USB_POWER_SOFTCONN 0x00000040 // Soft Connect/Disconnect -#define USB_POWER_HSENAB 0x00000020 // High Speed Enable -#define USB_POWER_HSMODE 0x00000010 // High Speed Enable -#define USB_POWER_RESET 0x00000008 // RESET Signaling -#define USB_POWER_RESUME 0x00000004 // RESUME Signaling -#define USB_POWER_SUSPEND 0x00000002 // SUSPEND Mode -#define USB_POWER_PWRDNPHY 0x00000001 // Power Down PHY +// 0x01: Power +#define USB_POWER_ISOUP 0x0080 // Isochronous Update +#define USB_POWER_SOFTCONN 0x0040 // Soft Connect/Disconnect +#define USB_POWER_HSENAB 0x0020 // High Speed Enable +#define USB_POWER_HSMODE 0x0010 // High Speed Enable +#define USB_POWER_RESET 0x0008 // RESET Signaling +#define USB_POWER_RESUME 0x0004 // RESUME Signaling +#define USB_POWER_SUSPEND 0x0002 // SUSPEND Mode +#define USB_POWER_PWRDNPHY 0x0001 // Power Down PHY -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_TXIS register. -// -//***************************************************************************** -#define USB_TXIS_EP7 0x00000080 // TX Endpoint 7 Interrupt -#define USB_TXIS_EP6 0x00000040 // TX Endpoint 6 Interrupt -#define USB_TXIS_EP5 0x00000020 // TX Endpoint 5 Interrupt -#define USB_TXIS_EP4 0x00000010 // TX Endpoint 4 Interrupt -#define USB_TXIS_EP3 0x00000008 // TX Endpoint 3 Interrupt -#define USB_TXIS_EP2 0x00000004 // TX Endpoint 2 Interrupt -#define USB_TXIS_EP1 0x00000002 // TX Endpoint 1 Interrupt -#define USB_TXIS_EP0 0x00000001 // TX and RX Endpoint 0 Interrupt +// Interrupt TX/RX Status and Enable: each bit is for an endpoint -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_RXIS register. -// -//***************************************************************************** -#define USB_RXIS_EP7 0x00000080 // RX Endpoint 7 Interrupt -#define USB_RXIS_EP6 0x00000040 // RX Endpoint 6 Interrupt -#define USB_RXIS_EP5 0x00000020 // RX Endpoint 5 Interrupt -#define USB_RXIS_EP4 0x00000010 // RX Endpoint 4 Interrupt -#define USB_RXIS_EP3 0x00000008 // RX Endpoint 3 Interrupt -#define USB_RXIS_EP2 0x00000004 // RX Endpoint 2 Interrupt -#define USB_RXIS_EP1 0x00000002 // RX Endpoint 1 Interrupt +// 0x6c: HWVERS +#define MUSB_HWVERS_RC_SHIFT 15 +#define MUSB_HWVERS_RC_MASK 0x8000 +#define MUSB_HWVERS_MAJOR_SHIFT 10 +#define MUSB_HWVERS_MAJOR_MASK 0x7C00 +#define MUSB_HWVERS_MINOR_SHIFT 0 +#define MUSB_HWVERS_MINOR_MASK 0x03FF -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_TXIE register. -// -//***************************************************************************** -#define USB_TXIE_EP7 0x00000080 // TX Endpoint 7 Interrupt Enable -#define USB_TXIE_EP6 0x00000040 // TX Endpoint 6 Interrupt Enable -#define USB_TXIE_EP5 0x00000020 // TX Endpoint 5 Interrupt Enable -#define USB_TXIE_EP4 0x00000010 // TX Endpoint 4 Interrupt Enable -#define USB_TXIE_EP3 0x00000008 // TX Endpoint 3 Interrupt Enable -#define USB_TXIE_EP2 0x00000004 // TX Endpoint 2 Interrupt Enable -#define USB_TXIE_EP1 0x00000002 // TX Endpoint 1 Interrupt Enable -#define USB_TXIE_EP0 0x00000001 // TX and RX Endpoint 0 Interrupt - // Enable +// 0x12, 0x16: TX/RX CSRL +#define MUSB_CSRL_PACKET_READY(_rx) (1u << 0) +#define MUSB_CSRL_FLUSH_FIFO(_rx) (1u << ((_rx) ? 4 : 3)) +#define MUSB_CSRL_SEND_STALL(_rx) (1u << ((_rx) ? 5 : 4)) +#define MUSB_CSRL_SENT_STALL(_rx) (1u << ((_rx) ? 6 : 5)) +#define MUSB_CSRL_CLEAR_DATA_TOGGLE(_rx) (1u << ((_rx) ? 7 : 6)) + +// 0x13, 0x17: TX/RX CSRH +#define MUSB_CSRH_DISABLE_DOUBLE_PACKET(_rx) (1u << 1) -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_RXIE register. -// -//***************************************************************************** -#define USB_RXIE_EP7 0x00000080 // RX Endpoint 7 Interrupt Enable -#define USB_RXIE_EP6 0x00000040 // RX Endpoint 6 Interrupt Enable -#define USB_RXIE_EP5 0x00000020 // RX Endpoint 5 Interrupt Enable -#define USB_RXIE_EP4 0x00000010 // RX Endpoint 4 Interrupt Enable -#define USB_RXIE_EP3 0x00000008 // RX Endpoint 3 Interrupt Enable -#define USB_RXIE_EP2 0x00000004 // RX Endpoint 2 Interrupt Enable -#define USB_RXIE_EP1 0x00000002 // RX Endpoint 1 Interrupt Enable //***************************************************************************** // // The following are defines for the bit fields in the USB_O_IS register. // //***************************************************************************** -#define USB_IS_VBUSERR 0x00000080 // VBUS Error (OTG only) -#define USB_IS_SESREQ 0x00000040 // SESSION REQUEST (OTG only) -#define USB_IS_DISCON 0x00000020 // Session Disconnect (OTG only) -#define USB_IS_CONN 0x00000010 // Session Connect -#define USB_IS_SOF 0x00000008 // Start of Frame -#define USB_IS_BABBLE 0x00000004 // Babble Detected -#define USB_IS_RESET 0x00000004 // RESET Signaling Detected -#define USB_IS_RESUME 0x00000002 // RESUME Signaling Detected -#define USB_IS_SUSPEND 0x00000001 // SUSPEND Signaling Detected +#define USB_IS_VBUSERR 0x0080 // VBUS Error (OTG only) +#define USB_IS_SESREQ 0x0040 // SESSION REQUEST (OTG only) +#define USB_IS_DISCON 0x0020 // Session Disconnect (OTG only) +#define USB_IS_CONN 0x0010 // Session Connect +#define USB_IS_SOF 0x0008 // Start of Frame +#define USB_IS_BABBLE 0x0004 // Babble Detected +#define USB_IS_RESET 0x0004 // RESET Signaling Detected +#define USB_IS_RESUME 0x0002 // RESUME Signaling Detected +#define USB_IS_SUSPEND 0x0001 // SUSPEND Signaling Detected //***************************************************************************** // // The following are defines for the bit fields in the USB_O_IE register. // //***************************************************************************** -#define USB_IE_VBUSERR 0x00000080 // Enable VBUS Error Interrupt (OTG - // only) -#define USB_IE_SESREQ 0x00000040 // Enable Session Request (OTG - // only) -#define USB_IE_DISCON 0x00000020 // Enable Disconnect Interrupt -#define USB_IE_CONN 0x00000010 // Enable Connect Interrupt -#define USB_IE_SOF 0x00000008 // Enable Start-of-Frame Interrupt -#define USB_IE_BABBLE 0x00000004 // Enable Babble Interrupt -#define USB_IE_RESET 0x00000004 // Enable RESET Interrupt -#define USB_IE_RESUME 0x00000002 // Enable RESUME Interrupt -#define USB_IE_SUSPND 0x00000001 // Enable SUSPEND Interrupt +#define USB_IE_VBUSERR 0x0080 // Enable VBUS Error Interrupt (OTG only) +#define USB_IE_SESREQ 0x0040 // Enable Session Request (OTG only) +#define USB_IE_DISCON 0x0020 // Enable Disconnect Interrupt +#define USB_IE_CONN 0x0010 // Enable Connect Interrupt +#define USB_IE_SOF 0x0008 // Enable Start-of-Frame Interrupt +#define USB_IE_BABBLE 0x0004 // Enable Babble Interrupt +#define USB_IE_RESET 0x0004 // Enable RESET Interrupt +#define USB_IE_RESUME 0x0002 // Enable RESUME Interrupt +#define USB_IE_SUSPND 0x0001 // Enable SUSPEND Interrupt //***************************************************************************** // // The following are defines for the bit fields in the USB_O_FRAME register. // //***************************************************************************** -#define USB_FRAME_M 0x000007FF // Frame Number +#define USB_FRAME_M 0x07FF // Frame Number #define USB_FRAME_S 0 -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_EPIDX register. -// -//***************************************************************************** -#define USB_EPIDX_EPIDX_M 0x0000000F // Endpoint Index -#define USB_EPIDX_EPIDX_S 0 - //***************************************************************************** // // The following are defines for the bit fields in the USB_O_TEST register. // //***************************************************************************** -#define USB_TEST_FORCEH 0x00000080 // Force Host Mode -#define USB_TEST_FIFOACC 0x00000040 // FIFO Access -#define USB_TEST_FORCEFS 0x00000020 // Force Full-Speed Mode -#define USB_TEST_FORCEHS 0x00000010 // Force High-Speed Mode -#define USB_TEST_TESTPKT 0x00000008 // Test Packet Mode Enable -#define USB_TEST_TESTK 0x00000004 // Test_K Mode Enable -#define USB_TEST_TESTJ 0x00000002 // Test_J Mode Enable -#define USB_TEST_TESTSE0NAK 0x00000001 // Test_SE0_NAK Test Mode Enable - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_FIFO0 register. -// -//***************************************************************************** -#define USB_FIFO0_EPDATA_M 0xFFFFFFFF // Endpoint Data -#define USB_FIFO0_EPDATA_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_FIFO1 register. -// -//***************************************************************************** -#define USB_FIFO1_EPDATA_M 0xFFFFFFFF // Endpoint Data -#define USB_FIFO1_EPDATA_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_FIFO2 register. -// -//***************************************************************************** -#define USB_FIFO2_EPDATA_M 0xFFFFFFFF // Endpoint Data -#define USB_FIFO2_EPDATA_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_FIFO3 register. -// -//***************************************************************************** -#define USB_FIFO3_EPDATA_M 0xFFFFFFFF // Endpoint Data -#define USB_FIFO3_EPDATA_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_FIFO4 register. -// -//***************************************************************************** -#define USB_FIFO4_EPDATA_M 0xFFFFFFFF // Endpoint Data -#define USB_FIFO4_EPDATA_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_FIFO5 register. -// -//***************************************************************************** -#define USB_FIFO5_EPDATA_M 0xFFFFFFFF // Endpoint Data -#define USB_FIFO5_EPDATA_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_FIFO6 register. -// -//***************************************************************************** -#define USB_FIFO6_EPDATA_M 0xFFFFFFFF // Endpoint Data -#define USB_FIFO6_EPDATA_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_FIFO7 register. -// -//***************************************************************************** -#define USB_FIFO7_EPDATA_M 0xFFFFFFFF // Endpoint Data -#define USB_FIFO7_EPDATA_S 0 +#define USB_TEST_FORCEH 0x0080 // Force Host Mode +#define USB_TEST_FIFOACC 0x0040 // FIFO Access +#define USB_TEST_FORCEFS 0x0020 // Force Full-Speed Mode +#define USB_TEST_FORCEHS 0x0010 // Force High-Speed Mode +#define USB_TEST_TESTPKT 0x0008 // Test Packet Mode Enable +#define USB_TEST_TESTK 0x0004 // Test_K Mode Enable +#define USB_TEST_TESTJ 0x0002 // Test_J Mode Enable +#define USB_TEST_TESTSE0NAK 0x0001 // Test_SE0_NAK Test Mode Enable //***************************************************************************** // // The following are defines for the bit fields in the USB_O_DEVCTL register. // //***************************************************************************** -#define USB_DEVCTL_DEV 0x00000080 // Device Mode (OTG only) -#define USB_DEVCTL_FSDEV 0x00000040 // Full-Speed Device Detected -#define USB_DEVCTL_LSDEV 0x00000020 // Low-Speed Device Detected -#define USB_DEVCTL_VBUS_M 0x00000018 // VBUS Level (OTG only) -#define USB_DEVCTL_VBUS_NONE 0x00000000 // Below SessionEnd -#define USB_DEVCTL_VBUS_SEND 0x00000008 // Above SessionEnd, below AValid -#define USB_DEVCTL_VBUS_AVALID 0x00000010 // Above AValid, below VBUSValid -#define USB_DEVCTL_VBUS_VALID 0x00000018 // Above VBUSValid -#define USB_DEVCTL_HOST 0x00000004 // Host Mode -#define USB_DEVCTL_HOSTREQ 0x00000002 // Host Request (OTG only) -#define USB_DEVCTL_SESSION 0x00000001 // Session Start/End (OTG only) +#define USB_DEVCTL_DEV 0x0080 // Device Mode (OTG only) +#define USB_DEVCTL_FSDEV 0x0040 // Full-Speed Device Detected +#define USB_DEVCTL_LSDEV 0x0020 // Low-Speed Device Detected +#define USB_DEVCTL_VBUS_M 0x0018 // VBUS Level (OTG only) +#define USB_DEVCTL_VBUS_NONE 0x0000 // Below SessionEnd +#define USB_DEVCTL_VBUS_SEND 0x0008 // Above SessionEnd, below AValid +#define USB_DEVCTL_VBUS_AVALID 0x0010 // Above AValid, below VBUSValid +#define USB_DEVCTL_VBUS_VALID 0x0018 // Above VBUSValid +#define USB_DEVCTL_HOST 0x0004 // Host Mode +#define USB_DEVCTL_HOSTREQ 0x0002 // Host Request (OTG only) +#define USB_DEVCTL_SESSION 0x0001 // Session Start/End (OTG only) //***************************************************************************** // // The following are defines for the bit fields in the USB_O_CCONF register. // //***************************************************************************** -#define USB_CCONF_TXEDMA 0x00000002 // TX Early DMA Enable -#define USB_CCONF_RXEDMA 0x00000001 // TX Early DMA Enable +#define USB_CCONF_TXEDMA 0x0002 // TX Early DMA Enable +#define USB_CCONF_RXEDMA 0x0001 // TX Early DMA Enable //***************************************************************************** // // The following are defines for the bit fields in the USB_O_TXFIFOSZ register. // //***************************************************************************** -#define USB_TXFIFOSZ_DPB 0x00000010 // Double Packet Buffer Support -#define USB_TXFIFOSZ_SIZE_M 0x0000000F // Max Packet Size -#define USB_TXFIFOSZ_SIZE_8 0x00000000 // 8 -#define USB_TXFIFOSZ_SIZE_16 0x00000001 // 16 -#define USB_TXFIFOSZ_SIZE_32 0x00000002 // 32 -#define USB_TXFIFOSZ_SIZE_64 0x00000003 // 64 -#define USB_TXFIFOSZ_SIZE_128 0x00000004 // 128 -#define USB_TXFIFOSZ_SIZE_256 0x00000005 // 256 -#define USB_TXFIFOSZ_SIZE_512 0x00000006 // 512 -#define USB_TXFIFOSZ_SIZE_1024 0x00000007 // 1024 -#define USB_TXFIFOSZ_SIZE_2048 0x00000008 // 2048 +#define USB_TXFIFOSZ_DPB 0x0010 // Double Packet Buffer Support +#define USB_TXFIFOSZ_SIZE_M 0x000F // Max Packet Size +#define USB_TXFIFOSZ_SIZE_8 0x0000 // 8 +#define USB_TXFIFOSZ_SIZE_16 0x0001 // 16 +#define USB_TXFIFOSZ_SIZE_32 0x0002 // 32 +#define USB_TXFIFOSZ_SIZE_64 0x0003 // 64 +#define USB_TXFIFOSZ_SIZE_128 0x0004 // 128 +#define USB_TXFIFOSZ_SIZE_256 0x0005 // 256 +#define USB_TXFIFOSZ_SIZE_512 0x0006 // 512 +#define USB_TXFIFOSZ_SIZE_1024 0x0007 // 1024 +#define USB_TXFIFOSZ_SIZE_2048 0x0008 // 2048 //***************************************************************************** // // The following are defines for the bit fields in the USB_O_RXFIFOSZ register. // //***************************************************************************** -#define USB_RXFIFOSZ_DPB 0x00000010 // Double Packet Buffer Support -#define USB_RXFIFOSZ_SIZE_M 0x0000000F // Max Packet Size -#define USB_RXFIFOSZ_SIZE_8 0x00000000 // 8 -#define USB_RXFIFOSZ_SIZE_16 0x00000001 // 16 -#define USB_RXFIFOSZ_SIZE_32 0x00000002 // 32 -#define USB_RXFIFOSZ_SIZE_64 0x00000003 // 64 -#define USB_RXFIFOSZ_SIZE_128 0x00000004 // 128 -#define USB_RXFIFOSZ_SIZE_256 0x00000005 // 256 -#define USB_RXFIFOSZ_SIZE_512 0x00000006 // 512 -#define USB_RXFIFOSZ_SIZE_1024 0x00000007 // 1024 -#define USB_RXFIFOSZ_SIZE_2048 0x00000008 // 2048 +#define USB_RXFIFOSZ_DPB 0x0010 // Double Packet Buffer Support +#define USB_RXFIFOSZ_SIZE_M 0x000F // Max Packet Size +#define USB_RXFIFOSZ_SIZE_8 0x0000 // 8 +#define USB_RXFIFOSZ_SIZE_16 0x0001 // 16 +#define USB_RXFIFOSZ_SIZE_32 0x0002 // 32 +#define USB_RXFIFOSZ_SIZE_64 0x0003 // 64 +#define USB_RXFIFOSZ_SIZE_128 0x0004 // 128 +#define USB_RXFIFOSZ_SIZE_256 0x0005 // 256 +#define USB_RXFIFOSZ_SIZE_512 0x0006 // 512 +#define USB_RXFIFOSZ_SIZE_1024 0x0007 // 1024 +#define USB_RXFIFOSZ_SIZE_2048 0x0008 // 2048 //***************************************************************************** // @@ -453,7 +426,7 @@ TU_ATTR_ALWAYS_INLINE static inline musb_ep_csr_t* get_ep_csr(musb_regs_t* musb_ // register. // //***************************************************************************** -#define USB_TXFIFOADD_ADDR_M 0x000001FF // Transmit/Receive Start Address +#define USB_TXFIFOADD_ADDR_M 0x01FF // Transmit/Receive Start Address #define USB_TXFIFOADD_ADDR_S 0 //***************************************************************************** @@ -462,7 +435,7 @@ TU_ATTR_ALWAYS_INLINE static inline musb_ep_csr_t* get_ep_csr(musb_regs_t* musb_ // register. // //***************************************************************************** -#define USB_RXFIFOADD_ADDR_M 0x000001FF // Transmit/Receive Start Address +#define USB_RXFIFOADD_ADDR_M 0x01FF // Transmit/Receive Start Address #define USB_RXFIFOADD_ADDR_S 0 //***************************************************************************** @@ -471,10 +444,8 @@ TU_ATTR_ALWAYS_INLINE static inline musb_ep_csr_t* get_ep_csr(musb_regs_t* musb_ // register. // //***************************************************************************** -#define USB_ULPIVBUSCTL_USEEXTVBUSIND \ - 0x00000002 // Use External VBUS Indicator -#define USB_ULPIVBUSCTL_USEEXTVBUS \ - 0x00000001 // Use External VBUS +#define USB_ULPIVBUSCTL_USEEXTVBUSIND 0x0002 // Use External VBUS Indicator +#define USB_ULPIVBUSCTL_USEEXTVBUS 0x0001 // Use External VBUS //***************************************************************************** // @@ -482,18 +453,15 @@ TU_ATTR_ALWAYS_INLINE static inline musb_ep_csr_t* get_ep_csr(musb_regs_t* musb_ // register. // //***************************************************************************** -#define USB_ULPIREGDATA_REGDATA_M \ - 0x000000FF // Register Data -#define USB_ULPIREGDATA_REGDATA_S \ - 0 - +#define USB_ULPIREGDATA_REGDATA_M 0x00FF // Register Data +#define USB_ULPIREGDATA_REGDATA_S 0 //***************************************************************************** // // The following are defines for the bit fields in the USB_O_ULPIREGADDR // register. // //***************************************************************************** -#define USB_ULPIREGADDR_ADDR_M 0x000000FF // Register Address +#define USB_ULPIREGADDR_ADDR_M 0x00FF // Register Address #define USB_ULPIREGADDR_ADDR_S 0 //***************************************************************************** @@ -502,17 +470,17 @@ TU_ATTR_ALWAYS_INLINE static inline musb_ep_csr_t* get_ep_csr(musb_regs_t* musb_ // register. // //***************************************************************************** -#define USB_ULPIREGCTL_RDWR 0x00000004 // Read/Write Control -#define USB_ULPIREGCTL_REGCMPLT 0x00000002 // Register Access Complete -#define USB_ULPIREGCTL_REGACC 0x00000001 // Initiate Register Access +#define USB_ULPIREGCTL_RDWR 0x0004 // Read/Write Control +#define USB_ULPIREGCTL_REGCMPLT 0x0002 // Register Access Complete +#define USB_ULPIREGCTL_REGACC 0x0001 // Initiate Register Access //***************************************************************************** // // The following are defines for the bit fields in the USB_O_EPINFO register. // //***************************************************************************** -#define USB_EPINFO_RXEP_M 0x000000F0 // RX Endpoints -#define USB_EPINFO_TXEP_M 0x0000000F // TX Endpoints +#define USB_EPINFO_RXEP_M 0x00F0 // RX Endpoints +#define USB_EPINFO_TXEP_M 0x000F // TX Endpoints #define USB_EPINFO_RXEP_S 4 #define USB_EPINFO_TXEP_S 0 @@ -521,8 +489,8 @@ TU_ATTR_ALWAYS_INLINE static inline musb_ep_csr_t* get_ep_csr(musb_regs_t* musb_ // The following are defines for the bit fields in the USB_O_RAMINFO register. // //***************************************************************************** -#define USB_RAMINFO_DMACHAN_M 0x000000F0 // DMA Channels -#define USB_RAMINFO_RAMBITS_M 0x0000000F // RAM Address Bus Width +#define USB_RAMINFO_DMACHAN_M 0x00F0 // DMA Channels +#define USB_RAMINFO_RAMBITS_M 0x000F // RAM Address Bus Width #define USB_RAMINFO_DMACHAN_S 4 #define USB_RAMINFO_RAMBITS_S 0 @@ -531,8 +499,8 @@ TU_ATTR_ALWAYS_INLINE static inline musb_ep_csr_t* get_ep_csr(musb_regs_t* musb_ // The following are defines for the bit fields in the USB_O_CONTIM register. // //***************************************************************************** -#define USB_CONTIM_WTCON_M 0x000000F0 // Connect Wait -#define USB_CONTIM_WTID_M 0x0000000F // Wait ID +#define USB_CONTIM_WTCON_M 0x00F0 // Connect Wait +#define USB_CONTIM_WTID_M 0x000F // Wait ID #define USB_CONTIM_WTCON_S 4 #define USB_CONTIM_WTID_S 0 @@ -541,7 +509,7 @@ TU_ATTR_ALWAYS_INLINE static inline musb_ep_csr_t* get_ep_csr(musb_regs_t* musb_ // The following are defines for the bit fields in the USB_O_VPLEN register. // //***************************************************************************** -#define USB_VPLEN_VPLEN_M 0x000000FF // VBUS Pulse Length +#define USB_VPLEN_VPLEN_M 0x00FF // VBUS Pulse Length #define USB_VPLEN_VPLEN_S 0 //***************************************************************************** @@ -549,7 +517,7 @@ TU_ATTR_ALWAYS_INLINE static inline musb_ep_csr_t* get_ep_csr(musb_regs_t* musb_ // The following are defines for the bit fields in the USB_O_HSEOF register. // //***************************************************************************** -#define USB_HSEOF_HSEOFG_M 0x000000FF // HIgh-Speed End-of-Frame Gap +#define USB_HSEOF_HSEOFG_M 0x00FF // HIgh-Speed End-of-Frame Gap #define USB_HSEOF_HSEOFG_S 0 //***************************************************************************** @@ -557,7 +525,7 @@ TU_ATTR_ALWAYS_INLINE static inline musb_ep_csr_t* get_ep_csr(musb_regs_t* musb_ // The following are defines for the bit fields in the USB_O_FSEOF register. // //***************************************************************************** -#define USB_FSEOF_FSEOFG_M 0x000000FF // Full-Speed End-of-Frame Gap +#define USB_FSEOF_FSEOFG_M 0x00FF // Full-Speed End-of-Frame Gap #define USB_FSEOF_FSEOFG_S 0 //***************************************************************************** @@ -565,449 +533,44 @@ TU_ATTR_ALWAYS_INLINE static inline musb_ep_csr_t* get_ep_csr(musb_regs_t* musb_ // The following are defines for the bit fields in the USB_O_LSEOF register. // //***************************************************************************** -#define USB_LSEOF_LSEOFG_M 0x000000FF // Low-Speed End-of-Frame Gap +#define USB_LSEOF_LSEOFG_M 0x00FF // Low-Speed End-of-Frame Gap #define USB_LSEOF_LSEOFG_S 0 -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_TXFUNCADDR0 -// register. -// -//***************************************************************************** -#define USB_TXFUNCADDR0_ADDR_M 0x0000007F // Device Address -#define USB_TXFUNCADDR0_ADDR_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_TXHUBADDR0 -// register. -// -//***************************************************************************** -#define USB_TXHUBADDR0_ADDR_M 0x0000007F // Hub Address -#define USB_TXHUBADDR0_ADDR_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_TXHUBPORT0 -// register. -// -//***************************************************************************** -#define USB_TXHUBPORT0_PORT_M 0x0000007F // Hub Port -#define USB_TXHUBPORT0_PORT_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_TXFUNCADDR1 -// register. -// -//***************************************************************************** -#define USB_TXFUNCADDR1_ADDR_M 0x0000007F // Device Address -#define USB_TXFUNCADDR1_ADDR_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_TXHUBADDR1 -// register. -// -//***************************************************************************** -#define USB_TXHUBADDR1_ADDR_M 0x0000007F // Hub Address -#define USB_TXHUBADDR1_ADDR_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_TXHUBPORT1 -// register. -// -//***************************************************************************** -#define USB_TXHUBPORT1_PORT_M 0x0000007F // Hub Port -#define USB_TXHUBPORT1_PORT_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_RXFUNCADDR1 -// register. -// -//***************************************************************************** -#define USB_RXFUNCADDR1_ADDR_M 0x0000007F // Device Address -#define USB_RXFUNCADDR1_ADDR_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_RXHUBADDR1 -// register. -// -//***************************************************************************** -#define USB_RXHUBADDR1_ADDR_M 0x0000007F // Hub Address -#define USB_RXHUBADDR1_ADDR_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_RXHUBPORT1 -// register. -// -//***************************************************************************** -#define USB_RXHUBPORT1_PORT_M 0x0000007F // Hub Port -#define USB_RXHUBPORT1_PORT_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_TXFUNCADDR2 -// register. -// -//***************************************************************************** -#define USB_TXFUNCADDR2_ADDR_M 0x0000007F // Device Address -#define USB_TXFUNCADDR2_ADDR_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_TXHUBADDR2 -// register. -// -//***************************************************************************** -#define USB_TXHUBADDR2_ADDR_M 0x0000007F // Hub Address -#define USB_TXHUBADDR2_ADDR_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_TXHUBPORT2 -// register. -// -//***************************************************************************** -#define USB_TXHUBPORT2_PORT_M 0x0000007F // Hub Port -#define USB_TXHUBPORT2_PORT_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_RXFUNCADDR2 -// register. -// -//***************************************************************************** -#define USB_RXFUNCADDR2_ADDR_M 0x0000007F // Device Address -#define USB_RXFUNCADDR2_ADDR_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_RXHUBADDR2 -// register. -// -//***************************************************************************** -#define USB_RXHUBADDR2_ADDR_M 0x0000007F // Hub Address -#define USB_RXHUBADDR2_ADDR_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_RXHUBPORT2 -// register. -// -//***************************************************************************** -#define USB_RXHUBPORT2_PORT_M 0x0000007F // Hub Port -#define USB_RXHUBPORT2_PORT_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_TXFUNCADDR3 -// register. -// -//***************************************************************************** -#define USB_TXFUNCADDR3_ADDR_M 0x0000007F // Device Address -#define USB_TXFUNCADDR3_ADDR_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_TXHUBADDR3 -// register. -// -//***************************************************************************** -#define USB_TXHUBADDR3_ADDR_M 0x0000007F // Hub Address -#define USB_TXHUBADDR3_ADDR_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_TXHUBPORT3 -// register. -// -//***************************************************************************** -#define USB_TXHUBPORT3_PORT_M 0x0000007F // Hub Port -#define USB_TXHUBPORT3_PORT_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_RXFUNCADDR3 -// register. -// -//***************************************************************************** -#define USB_RXFUNCADDR3_ADDR_M 0x0000007F // Device Address -#define USB_RXFUNCADDR3_ADDR_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_RXHUBADDR3 -// register. -// -//***************************************************************************** -#define USB_RXHUBADDR3_ADDR_M 0x0000007F // Hub Address -#define USB_RXHUBADDR3_ADDR_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_RXHUBPORT3 -// register. -// -//***************************************************************************** -#define USB_RXHUBPORT3_PORT_M 0x0000007F // Hub Port -#define USB_RXHUBPORT3_PORT_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_TXFUNCADDR4 -// register. -// -//***************************************************************************** -#define USB_TXFUNCADDR4_ADDR_M 0x0000007F // Device Address -#define USB_TXFUNCADDR4_ADDR_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_TXHUBADDR4 -// register. -// -//***************************************************************************** -#define USB_TXHUBADDR4_ADDR_M 0x0000007F // Hub Address -#define USB_TXHUBADDR4_ADDR_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_TXHUBPORT4 -// register. -// -//***************************************************************************** -#define USB_TXHUBPORT4_PORT_M 0x0000007F // Hub Port -#define USB_TXHUBPORT4_PORT_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_RXFUNCADDR4 -// register. -// -//***************************************************************************** -#define USB_RXFUNCADDR4_ADDR_M 0x0000007F // Device Address -#define USB_RXFUNCADDR4_ADDR_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_RXHUBADDR4 -// register. -// -//***************************************************************************** -#define USB_RXHUBADDR4_ADDR_M 0x0000007F // Hub Address -#define USB_RXHUBADDR4_ADDR_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_RXHUBPORT4 -// register. -// -//***************************************************************************** -#define USB_RXHUBPORT4_PORT_M 0x0000007F // Hub Port -#define USB_RXHUBPORT4_PORT_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_TXFUNCADDR5 -// register. -// -//***************************************************************************** -#define USB_TXFUNCADDR5_ADDR_M 0x0000007F // Device Address -#define USB_TXFUNCADDR5_ADDR_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_TXHUBADDR5 -// register. -// -//***************************************************************************** -#define USB_TXHUBADDR5_ADDR_M 0x0000007F // Hub Address -#define USB_TXHUBADDR5_ADDR_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_TXHUBPORT5 -// register. -// -//***************************************************************************** -#define USB_TXHUBPORT5_PORT_M 0x0000007F // Hub Port -#define USB_TXHUBPORT5_PORT_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_RXFUNCADDR5 -// register. -// -//***************************************************************************** -#define USB_RXFUNCADDR5_ADDR_M 0x0000007F // Device Address -#define USB_RXFUNCADDR5_ADDR_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_RXHUBADDR5 -// register. -// -//***************************************************************************** -#define USB_RXHUBADDR5_ADDR_M 0x0000007F // Hub Address -#define USB_RXHUBADDR5_ADDR_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_RXHUBPORT5 -// register. -// -//***************************************************************************** -#define USB_RXHUBPORT5_PORT_M 0x0000007F // Hub Port -#define USB_RXHUBPORT5_PORT_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_TXFUNCADDR6 -// register. -// -//***************************************************************************** -#define USB_TXFUNCADDR6_ADDR_M 0x0000007F // Device Address -#define USB_TXFUNCADDR6_ADDR_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_TXHUBADDR6 -// register. -// -//***************************************************************************** -#define USB_TXHUBADDR6_ADDR_M 0x0000007F // Hub Address -#define USB_TXHUBADDR6_ADDR_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_TXHUBPORT6 -// register. -// -//***************************************************************************** -#define USB_TXHUBPORT6_PORT_M 0x0000007F // Hub Port -#define USB_TXHUBPORT6_PORT_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_RXFUNCADDR6 -// register. -// -//***************************************************************************** -#define USB_RXFUNCADDR6_ADDR_M 0x0000007F // Device Address -#define USB_RXFUNCADDR6_ADDR_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_RXHUBADDR6 -// register. -// -//***************************************************************************** -#define USB_RXHUBADDR6_ADDR_M 0x0000007F // Hub Address -#define USB_RXHUBADDR6_ADDR_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_RXHUBPORT6 -// register. -// -//***************************************************************************** -#define USB_RXHUBPORT6_PORT_M 0x0000007F // Hub Port -#define USB_RXHUBPORT6_PORT_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_TXFUNCADDR7 -// register. -// -//***************************************************************************** -#define USB_TXFUNCADDR7_ADDR_M 0x0000007F // Device Address -#define USB_TXFUNCADDR7_ADDR_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_TXHUBADDR7 -// register. -// -//***************************************************************************** -#define USB_TXHUBADDR7_ADDR_M 0x0000007F // Hub Address -#define USB_TXHUBADDR7_ADDR_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_TXHUBPORT7 -// register. -// -//***************************************************************************** -#define USB_TXHUBPORT7_PORT_M 0x0000007F // Hub Port -#define USB_TXHUBPORT7_PORT_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_RXFUNCADDR7 -// register. -// -//***************************************************************************** -#define USB_RXFUNCADDR7_ADDR_M 0x0000007F // Device Address -#define USB_RXFUNCADDR7_ADDR_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_RXHUBADDR7 -// register. -// -//***************************************************************************** -#define USB_RXHUBADDR7_ADDR_M 0x0000007F // Hub Address -#define USB_RXHUBADDR7_ADDR_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_RXHUBPORT7 -// register. -// -//***************************************************************************** -#define USB_RXHUBPORT7_PORT_M 0x0000007F // Hub Port -#define USB_RXHUBPORT7_PORT_S 0 - //***************************************************************************** // // The following are defines for the bit fields in the USB_O_CSRL0 register. // //***************************************************************************** -#define USB_CSRL0_NAKTO 0x00000080 // NAK Timeout -#define USB_CSRL0_SETENDC 0x00000080 // Setup End Clear -#define USB_CSRL0_STATUS 0x00000040 // STATUS Packet -#define USB_CSRL0_RXRDYC 0x00000040 // RXRDY Clear -#define USB_CSRL0_REQPKT 0x00000020 // Request Packet -#define USB_CSRL0_STALL 0x00000020 // Send Stall -#define USB_CSRL0_SETEND 0x00000010 // Setup End -#define USB_CSRL0_ERROR 0x00000010 // Error -#define USB_CSRL0_DATAEND 0x00000008 // Data End -#define USB_CSRL0_SETUP 0x00000008 // Setup Packet -#define USB_CSRL0_STALLED 0x00000004 // Endpoint Stalled -#define USB_CSRL0_TXRDY 0x00000002 // Transmit Packet Ready -#define USB_CSRL0_RXRDY 0x00000001 // Receive Packet Ready +#define USB_CSRL0_NAKTO 0x0080 // NAK Timeout +#define USB_CSRL0_SETENDC 0x0080 // Setup End Clear +#define USB_CSRL0_STATUS 0x0040 // STATUS Packet +#define USB_CSRL0_RXRDYC 0x0040 // RXRDY Clear +#define USB_CSRL0_REQPKT 0x0020 // Request Packet +#define USB_CSRL0_STALL 0x0020 // Send Stall +#define USB_CSRL0_SETEND 0x0010 // Setup End +#define USB_CSRL0_ERROR 0x0010 // Error +#define USB_CSRL0_DATAEND 0x0008 // Data End +#define USB_CSRL0_SETUP 0x0008 // Setup Packet +#define USB_CSRL0_STALLED 0x0004 // Endpoint Stalled +#define USB_CSRL0_TXRDY 0x0002 // Transmit Packet Ready +#define USB_CSRL0_RXRDY 0x0001 // Receive Packet Ready //***************************************************************************** // // The following are defines for the bit fields in the USB_O_CSRH0 register. // //***************************************************************************** -#define USB_CSRH0_DISPING 0x00000008 // PING Disable -#define USB_CSRH0_DTWE 0x00000004 // Data Toggle Write Enable -#define USB_CSRH0_DT 0x00000002 // Data Toggle -#define USB_CSRH0_FLUSH 0x00000001 // Flush FIFO +#define USB_CSRH0_DISPING 0x0008 // PING Disable +#define USB_CSRH0_DTWE 0x0004 // Data Toggle Write Enable +#define USB_CSRH0_DT 0x0002 // Data Toggle +#define USB_CSRH0_FLUSH 0x0001 // Flush FIFO //***************************************************************************** // // The following are defines for the bit fields in the USB_O_COUNT0 register. // //***************************************************************************** -#define USB_COUNT0_COUNT_M 0x0000007F // FIFO Count +#define USB_COUNT0_COUNT_M 0x007F // FIFO Count #define USB_COUNT0_COUNT_S 0 //***************************************************************************** @@ -1015,17 +578,17 @@ TU_ATTR_ALWAYS_INLINE static inline musb_ep_csr_t* get_ep_csr(musb_regs_t* musb_ // The following are defines for the bit fields in the USB_O_TYPE0 register. // //***************************************************************************** -#define USB_TYPE0_SPEED_M 0x000000C0 // Operating Speed -#define USB_TYPE0_SPEED_HIGH 0x00000040 // High -#define USB_TYPE0_SPEED_FULL 0x00000080 // Full -#define USB_TYPE0_SPEED_LOW 0x000000C0 // Low +#define USB_TYPE0_SPEED_M 0x00C0 // Operating Speed +#define USB_TYPE0_SPEED_HIGH 0x0040 // High +#define USB_TYPE0_SPEED_FULL 0x0080 // Full +#define USB_TYPE0_SPEED_LOW 0x00C0 // Low //***************************************************************************** // // The following are defines for the bit fields in the USB_O_NAKLMT register. // //***************************************************************************** -#define USB_NAKLMT_NAKLMT_M 0x0000001F // EP0 NAK Limit +#define USB_NAKLMT_NAKLMT_M 0x001F // EP0 NAK Limit #define USB_NAKLMT_NAKLMT_S 0 //***************************************************************************** @@ -1033,7 +596,7 @@ TU_ATTR_ALWAYS_INLINE static inline musb_ep_csr_t* get_ep_csr(musb_regs_t* musb_ // The following are defines for the bit fields in the USB_O_TXMAXP1 register. // //***************************************************************************** -#define USB_TXMAXP1_MAXLOAD_M 0x000007FF // Maximum Payload +#define USB_TXMAXP1_MAXLOAD_M 0x07FF // Maximum Payload #define USB_TXMAXP1_MAXLOAD_S 0 //***************************************************************************** @@ -1041,37 +604,37 @@ TU_ATTR_ALWAYS_INLINE static inline musb_ep_csr_t* get_ep_csr(musb_regs_t* musb_ // The following are defines for the bit fields in the USB_O_TXCSRL1 register. // //***************************************************************************** -#define USB_TXCSRL1_NAKTO 0x00000080 // NAK Timeout -#define USB_TXCSRL1_CLRDT 0x00000040 // Clear Data Toggle -#define USB_TXCSRL1_STALLED 0x00000020 // Endpoint Stalled -#define USB_TXCSRL1_STALL 0x00000010 // Send STALL -#define USB_TXCSRL1_SETUP 0x00000010 // Setup Packet -#define USB_TXCSRL1_FLUSH 0x00000008 // Flush FIFO -#define USB_TXCSRL1_ERROR 0x00000004 // Error -#define USB_TXCSRL1_UNDRN 0x00000004 // Underrun -#define USB_TXCSRL1_FIFONE 0x00000002 // FIFO Not Empty -#define USB_TXCSRL1_TXRDY 0x00000001 // Transmit Packet Ready +#define USB_TXCSRL1_NAKTO 0x0080 // NAK Timeout +#define USB_TXCSRL1_CLRDT 0x0040 // Clear Data Toggle +#define USB_TXCSRL1_STALLED 0x0020 // Endpoint Stalled +#define USB_TXCSRL1_STALL 0x0010 // Send STALL +#define USB_TXCSRL1_SETUP 0x0010 // Setup Packet +#define USB_TXCSRL1_FLUSH 0x0008 // Flush FIFO +#define USB_TXCSRL1_ERROR 0x0004 // Error +#define USB_TXCSRL1_UNDRN 0x0004 // Underrun +#define USB_TXCSRL1_FIFONE 0x0002 // FIFO Not Empty +#define USB_TXCSRL1_TXRDY 0x0001 // Transmit Packet Ready //***************************************************************************** // // The following are defines for the bit fields in the USB_O_TXCSRH1 register. // //***************************************************************************** -#define USB_TXCSRH1_AUTOSET 0x00000080 // Auto Set -#define USB_TXCSRH1_ISO 0x00000040 // Isochronous Transfers -#define USB_TXCSRH1_MODE 0x00000020 // Mode -#define USB_TXCSRH1_DMAEN 0x00000010 // DMA Request Enable -#define USB_TXCSRH1_FDT 0x00000008 // Force Data Toggle -#define USB_TXCSRH1_DMAMOD 0x00000004 // DMA Request Mode -#define USB_TXCSRH1_DTWE 0x00000002 // Data Toggle Write Enable -#define USB_TXCSRH1_DT 0x00000001 // Data Toggle +#define USB_TXCSRH1_AUTOSET 0x0080 // Auto Set +#define USB_TXCSRH1_ISO 0x0040 // Isochronous Transfers +#define USB_TXCSRH1_MODE 0x0020 // Mode +#define USB_TXCSRH1_DMAEN 0x0010 // DMA Request Enable +#define USB_TXCSRH1_FDT 0x0008 // Force Data Toggle +#define USB_TXCSRH1_DMAMOD 0x0004 // DMA Request Mode +#define USB_TXCSRH1_DTWE 0x0002 // Data Toggle Write Enable +#define USB_TXCSRH1_DT 0x0001 // Data Toggle //***************************************************************************** // // The following are defines for the bit fields in the USB_O_RXMAXP1 register. // //***************************************************************************** -#define USB_RXMAXP1_MAXLOAD_M 0x000007FF // Maximum Payload +#define USB_RXMAXP1_MAXLOAD_M 0x07FF // Maximum Payload #define USB_RXMAXP1_MAXLOAD_S 0 //***************************************************************************** @@ -1079,33 +642,33 @@ TU_ATTR_ALWAYS_INLINE static inline musb_ep_csr_t* get_ep_csr(musb_regs_t* musb_ // The following are defines for the bit fields in the USB_O_RXCSRL1 register. // //***************************************************************************** -#define USB_RXCSRL1_CLRDT 0x00000080 // Clear Data Toggle -#define USB_RXCSRL1_STALLED 0x00000040 // Endpoint Stalled -#define USB_RXCSRL1_STALL 0x00000020 // Send STALL -#define USB_RXCSRL1_REQPKT 0x00000020 // Request Packet -#define USB_RXCSRL1_FLUSH 0x00000010 // Flush FIFO -#define USB_RXCSRL1_DATAERR 0x00000008 // Data Error -#define USB_RXCSRL1_NAKTO 0x00000008 // NAK Timeout -#define USB_RXCSRL1_OVER 0x00000004 // Overrun -#define USB_RXCSRL1_ERROR 0x00000004 // Error -#define USB_RXCSRL1_FULL 0x00000002 // FIFO Full -#define USB_RXCSRL1_RXRDY 0x00000001 // Receive Packet Ready +#define USB_RXCSRL1_CLRDT 0x0080 // Clear Data Toggle +#define USB_RXCSRL1_STALLED 0x0040 // Endpoint Stalled +#define USB_RXCSRL1_STALL 0x0020 // Send STALL +#define USB_RXCSRL1_REQPKT 0x0020 // Request Packet +#define USB_RXCSRL1_FLUSH 0x0010 // Flush FIFO +#define USB_RXCSRL1_DATAERR 0x0008 // Data Error +#define USB_RXCSRL1_NAKTO 0x0008 // NAK Timeout +#define USB_RXCSRL1_OVER 0x0004 // Overrun +#define USB_RXCSRL1_ERROR 0x0004 // Error +#define USB_RXCSRL1_FULL 0x0002 // FIFO Full +#define USB_RXCSRL1_RXRDY 0x0001 // Receive Packet Ready //***************************************************************************** // // The following are defines for the bit fields in the USB_O_RXCSRH1 register. // //***************************************************************************** -#define USB_RXCSRH1_AUTOCL 0x00000080 // Auto Clear -#define USB_RXCSRH1_AUTORQ 0x00000040 // Auto Request -#define USB_RXCSRH1_ISO 0x00000040 // Isochronous Transfers -#define USB_RXCSRH1_DMAEN 0x00000020 // DMA Request Enable -#define USB_RXCSRH1_DISNYET 0x00000010 // Disable NYET -#define USB_RXCSRH1_PIDERR 0x00000010 // PID Error -#define USB_RXCSRH1_DMAMOD 0x00000008 // DMA Request Mode -#define USB_RXCSRH1_DTWE 0x00000004 // Data Toggle Write Enable -#define USB_RXCSRH1_DT 0x00000002 // Data Toggle -#define USB_RXCSRH1_INCOMPRX 0x00000001 // Incomplete RX Transmission +#define USB_RXCSRH1_AUTOCL 0x0080 // Auto Clear +#define USB_RXCSRH1_AUTORQ 0x0040 // Auto Request +#define USB_RXCSRH1_ISO 0x0040 // Isochronous Transfers +#define USB_RXCSRH1_DMAEN 0x0020 // DMA Request Enable +#define USB_RXCSRH1_DISNYET 0x0010 // Disable NYET +#define USB_RXCSRH1_PIDERR 0x0010 // PID Error +#define USB_RXCSRH1_DMAMOD 0x0008 // DMA Request Mode +#define USB_RXCSRH1_DTWE 0x0004 // Data Toggle Write Enable +#define USB_RXCSRH1_DT 0x0002 // Data Toggle +#define USB_RXCSRH1_INCOMPRX 0x0001 // Incomplete RX Transmission // Status //***************************************************************************** @@ -1113,7 +676,7 @@ TU_ATTR_ALWAYS_INLINE static inline musb_ep_csr_t* get_ep_csr(musb_regs_t* musb_ // The following are defines for the bit fields in the USB_O_RXCOUNT1 register. // //***************************************************************************** -#define USB_RXCOUNT1_COUNT_M 0x00001FFF // Receive Packet Count +#define USB_RXCOUNT1_COUNT_M 0x1FFF // Receive Packet Count #define USB_RXCOUNT1_COUNT_S 0 //***************************************************************************** @@ -1121,17 +684,17 @@ TU_ATTR_ALWAYS_INLINE static inline musb_ep_csr_t* get_ep_csr(musb_regs_t* musb_ // The following are defines for the bit fields in the USB_O_TXTYPE1 register. // //***************************************************************************** -#define USB_TXTYPE1_SPEED_M 0x000000C0 // Operating Speed -#define USB_TXTYPE1_SPEED_DFLT 0x00000000 // Default -#define USB_TXTYPE1_SPEED_HIGH 0x00000040 // High -#define USB_TXTYPE1_SPEED_FULL 0x00000080 // Full -#define USB_TXTYPE1_SPEED_LOW 0x000000C0 // Low -#define USB_TXTYPE1_PROTO_M 0x00000030 // Protocol -#define USB_TXTYPE1_PROTO_CTRL 0x00000000 // Control -#define USB_TXTYPE1_PROTO_ISOC 0x00000010 // Isochronous -#define USB_TXTYPE1_PROTO_BULK 0x00000020 // Bulk -#define USB_TXTYPE1_PROTO_INT 0x00000030 // Interrupt -#define USB_TXTYPE1_TEP_M 0x0000000F // Target Endpoint Number +#define USB_TXTYPE1_SPEED_M 0x00C0 // Operating Speed +#define USB_TXTYPE1_SPEED_DFLT 0x0000 // Default +#define USB_TXTYPE1_SPEED_HIGH 0x0040 // High +#define USB_TXTYPE1_SPEED_FULL 0x0080 // Full +#define USB_TXTYPE1_SPEED_LOW 0x00C0 // Low +#define USB_TXTYPE1_PROTO_M 0x0030 // Protocol +#define USB_TXTYPE1_PROTO_CTRL 0x0000 // Control +#define USB_TXTYPE1_PROTO_ISOC 0x0010 // Isochronous +#define USB_TXTYPE1_PROTO_BULK 0x0020 // Bulk +#define USB_TXTYPE1_PROTO_INT 0x0030 // Interrupt +#define USB_TXTYPE1_TEP_M 0x000F // Target Endpoint Number #define USB_TXTYPE1_TEP_S 0 //***************************************************************************** @@ -1140,31 +703,27 @@ TU_ATTR_ALWAYS_INLINE static inline musb_ep_csr_t* get_ep_csr(musb_regs_t* musb_ // register. // //***************************************************************************** -#define USB_TXINTERVAL1_NAKLMT_M \ - 0x000000FF // NAK Limit -#define USB_TXINTERVAL1_TXPOLL_M \ - 0x000000FF // TX Polling -#define USB_TXINTERVAL1_TXPOLL_S \ - 0 -#define USB_TXINTERVAL1_NAKLMT_S \ - 0 +#define USB_TXINTERVAL1_NAKLMT_M 0x00FF // NAK Limit +#define USB_TXINTERVAL1_TXPOLL_M 0x00FF // TX Polling +#define USB_TXINTERVAL1_TXPOLL_S 0 +#define USB_TXINTERVAL1_NAKLMT_S 0 //***************************************************************************** // // The following are defines for the bit fields in the USB_O_RXTYPE1 register. // //***************************************************************************** -#define USB_RXTYPE1_SPEED_M 0x000000C0 // Operating Speed -#define USB_RXTYPE1_SPEED_DFLT 0x00000000 // Default -#define USB_RXTYPE1_SPEED_HIGH 0x00000040 // High -#define USB_RXTYPE1_SPEED_FULL 0x00000080 // Full -#define USB_RXTYPE1_SPEED_LOW 0x000000C0 // Low -#define USB_RXTYPE1_PROTO_M 0x00000030 // Protocol -#define USB_RXTYPE1_PROTO_CTRL 0x00000000 // Control -#define USB_RXTYPE1_PROTO_ISOC 0x00000010 // Isochronous -#define USB_RXTYPE1_PROTO_BULK 0x00000020 // Bulk -#define USB_RXTYPE1_PROTO_INT 0x00000030 // Interrupt -#define USB_RXTYPE1_TEP_M 0x0000000F // Target Endpoint Number +#define USB_RXTYPE1_SPEED_M 0x00C0 // Operating Speed +#define USB_RXTYPE1_SPEED_DFLT 0x0000 // Default +#define USB_RXTYPE1_SPEED_HIGH 0x0040 // High +#define USB_RXTYPE1_SPEED_FULL 0x0080 // Full +#define USB_RXTYPE1_SPEED_LOW 0x00C0 // Low +#define USB_RXTYPE1_PROTO_M 0x0030 // Protocol +#define USB_RXTYPE1_PROTO_CTRL 0x0000 // Control +#define USB_RXTYPE1_PROTO_ISOC 0x0010 // Isochronous +#define USB_RXTYPE1_PROTO_BULK 0x0020 // Bulk +#define USB_RXTYPE1_PROTO_INT 0x0030 // Interrupt +#define USB_RXTYPE1_TEP_M 0x000F // Target Endpoint Number #define USB_RXTYPE1_TEP_S 0 //***************************************************************************** @@ -1173,21 +732,17 @@ TU_ATTR_ALWAYS_INLINE static inline musb_ep_csr_t* get_ep_csr(musb_regs_t* musb_ // register. // //***************************************************************************** -#define USB_RXINTERVAL1_TXPOLL_M \ - 0x000000FF // RX Polling -#define USB_RXINTERVAL1_NAKLMT_M \ - 0x000000FF // NAK Limit -#define USB_RXINTERVAL1_TXPOLL_S \ - 0 -#define USB_RXINTERVAL1_NAKLMT_S \ - 0 +#define USB_RXINTERVAL1_TXPOLL_M 0x00FF // RX Polling +#define USB_RXINTERVAL1_NAKLMT_M 0x00FF // NAK Limit +#define USB_RXINTERVAL1_TXPOLL_S 0 +#define USB_RXINTERVAL1_NAKLMT_S 0 //***************************************************************************** // // The following are defines for the bit fields in the USB_O_TXMAXP2 register. // //***************************************************************************** -#define USB_TXMAXP2_MAXLOAD_M 0x000007FF // Maximum Payload +#define USB_TXMAXP2_MAXLOAD_M 0x07FF // Maximum Payload #define USB_TXMAXP2_MAXLOAD_S 0 //***************************************************************************** @@ -1195,37 +750,37 @@ TU_ATTR_ALWAYS_INLINE static inline musb_ep_csr_t* get_ep_csr(musb_regs_t* musb_ // The following are defines for the bit fields in the USB_O_TXCSRL2 register. // //***************************************************************************** -#define USB_TXCSRL2_NAKTO 0x00000080 // NAK Timeout -#define USB_TXCSRL2_CLRDT 0x00000040 // Clear Data Toggle -#define USB_TXCSRL2_STALLED 0x00000020 // Endpoint Stalled -#define USB_TXCSRL2_SETUP 0x00000010 // Setup Packet -#define USB_TXCSRL2_STALL 0x00000010 // Send STALL -#define USB_TXCSRL2_FLUSH 0x00000008 // Flush FIFO -#define USB_TXCSRL2_ERROR 0x00000004 // Error -#define USB_TXCSRL2_UNDRN 0x00000004 // Underrun -#define USB_TXCSRL2_FIFONE 0x00000002 // FIFO Not Empty -#define USB_TXCSRL2_TXRDY 0x00000001 // Transmit Packet Ready +#define USB_TXCSRL2_NAKTO 0x0080 // NAK Timeout +#define USB_TXCSRL2_CLRDT 0x0040 // Clear Data Toggle +#define USB_TXCSRL2_STALLED 0x0020 // Endpoint Stalled +#define USB_TXCSRL2_SETUP 0x0010 // Setup Packet +#define USB_TXCSRL2_STALL 0x0010 // Send STALL +#define USB_TXCSRL2_FLUSH 0x0008 // Flush FIFO +#define USB_TXCSRL2_ERROR 0x0004 // Error +#define USB_TXCSRL2_UNDRN 0x0004 // Underrun +#define USB_TXCSRL2_FIFONE 0x0002 // FIFO Not Empty +#define USB_TXCSRL2_TXRDY 0x0001 // Transmit Packet Ready //***************************************************************************** // // The following are defines for the bit fields in the USB_O_TXCSRH2 register. // //***************************************************************************** -#define USB_TXCSRH2_AUTOSET 0x00000080 // Auto Set -#define USB_TXCSRH2_ISO 0x00000040 // Isochronous Transfers -#define USB_TXCSRH2_MODE 0x00000020 // Mode -#define USB_TXCSRH2_DMAEN 0x00000010 // DMA Request Enable -#define USB_TXCSRH2_FDT 0x00000008 // Force Data Toggle -#define USB_TXCSRH2_DMAMOD 0x00000004 // DMA Request Mode -#define USB_TXCSRH2_DTWE 0x00000002 // Data Toggle Write Enable -#define USB_TXCSRH2_DT 0x00000001 // Data Toggle +#define USB_TXCSRH2_AUTOSET 0x0080 // Auto Set +#define USB_TXCSRH2_ISO 0x0040 // Isochronous Transfers +#define USB_TXCSRH2_MODE 0x0020 // Mode +#define USB_TXCSRH2_DMAEN 0x0010 // DMA Request Enable +#define USB_TXCSRH2_FDT 0x0008 // Force Data Toggle +#define USB_TXCSRH2_DMAMOD 0x0004 // DMA Request Mode +#define USB_TXCSRH2_DTWE 0x0002 // Data Toggle Write Enable +#define USB_TXCSRH2_DT 0x0001 // Data Toggle //***************************************************************************** // // The following are defines for the bit fields in the USB_O_RXMAXP2 register. // //***************************************************************************** -#define USB_RXMAXP2_MAXLOAD_M 0x000007FF // Maximum Payload +#define USB_RXMAXP2_MAXLOAD_M 0x07FF // Maximum Payload #define USB_RXMAXP2_MAXLOAD_S 0 //***************************************************************************** @@ -1233,33 +788,33 @@ TU_ATTR_ALWAYS_INLINE static inline musb_ep_csr_t* get_ep_csr(musb_regs_t* musb_ // The following are defines for the bit fields in the USB_O_RXCSRL2 register. // //***************************************************************************** -#define USB_RXCSRL2_CLRDT 0x00000080 // Clear Data Toggle -#define USB_RXCSRL2_STALLED 0x00000040 // Endpoint Stalled -#define USB_RXCSRL2_REQPKT 0x00000020 // Request Packet -#define USB_RXCSRL2_STALL 0x00000020 // Send STALL -#define USB_RXCSRL2_FLUSH 0x00000010 // Flush FIFO -#define USB_RXCSRL2_DATAERR 0x00000008 // Data Error -#define USB_RXCSRL2_NAKTO 0x00000008 // NAK Timeout -#define USB_RXCSRL2_ERROR 0x00000004 // Error -#define USB_RXCSRL2_OVER 0x00000004 // Overrun -#define USB_RXCSRL2_FULL 0x00000002 // FIFO Full -#define USB_RXCSRL2_RXRDY 0x00000001 // Receive Packet Ready +#define USB_RXCSRL2_CLRDT 0x0080 // Clear Data Toggle +#define USB_RXCSRL2_STALLED 0x0040 // Endpoint Stalled +#define USB_RXCSRL2_REQPKT 0x0020 // Request Packet +#define USB_RXCSRL2_STALL 0x0020 // Send STALL +#define USB_RXCSRL2_FLUSH 0x0010 // Flush FIFO +#define USB_RXCSRL2_DATAERR 0x0008 // Data Error +#define USB_RXCSRL2_NAKTO 0x0008 // NAK Timeout +#define USB_RXCSRL2_ERROR 0x0004 // Error +#define USB_RXCSRL2_OVER 0x0004 // Overrun +#define USB_RXCSRL2_FULL 0x0002 // FIFO Full +#define USB_RXCSRL2_RXRDY 0x0001 // Receive Packet Ready //***************************************************************************** // // The following are defines for the bit fields in the USB_O_RXCSRH2 register. // //***************************************************************************** -#define USB_RXCSRH2_AUTOCL 0x00000080 // Auto Clear -#define USB_RXCSRH2_AUTORQ 0x00000040 // Auto Request -#define USB_RXCSRH2_ISO 0x00000040 // Isochronous Transfers -#define USB_RXCSRH2_DMAEN 0x00000020 // DMA Request Enable -#define USB_RXCSRH2_DISNYET 0x00000010 // Disable NYET -#define USB_RXCSRH2_PIDERR 0x00000010 // PID Error -#define USB_RXCSRH2_DMAMOD 0x00000008 // DMA Request Mode -#define USB_RXCSRH2_DTWE 0x00000004 // Data Toggle Write Enable -#define USB_RXCSRH2_DT 0x00000002 // Data Toggle -#define USB_RXCSRH2_INCOMPRX 0x00000001 // Incomplete RX Transmission +#define USB_RXCSRH2_AUTOCL 0x0080 // Auto Clear +#define USB_RXCSRH2_AUTORQ 0x0040 // Auto Request +#define USB_RXCSRH2_ISO 0x0040 // Isochronous Transfers +#define USB_RXCSRH2_DMAEN 0x0020 // DMA Request Enable +#define USB_RXCSRH2_DISNYET 0x0010 // Disable NYET +#define USB_RXCSRH2_PIDERR 0x0010 // PID Error +#define USB_RXCSRH2_DMAMOD 0x0008 // DMA Request Mode +#define USB_RXCSRH2_DTWE 0x0004 // Data Toggle Write Enable +#define USB_RXCSRH2_DT 0x0002 // Data Toggle +#define USB_RXCSRH2_INCOMPRX 0x0001 // Incomplete RX Transmission // Status //***************************************************************************** @@ -1267,7 +822,7 @@ TU_ATTR_ALWAYS_INLINE static inline musb_ep_csr_t* get_ep_csr(musb_regs_t* musb_ // The following are defines for the bit fields in the USB_O_RXCOUNT2 register. // //***************************************************************************** -#define USB_RXCOUNT2_COUNT_M 0x00001FFF // Receive Packet Count +#define USB_RXCOUNT2_COUNT_M 0x1FFF // Receive Packet Count #define USB_RXCOUNT2_COUNT_S 0 //***************************************************************************** @@ -1275,17 +830,17 @@ TU_ATTR_ALWAYS_INLINE static inline musb_ep_csr_t* get_ep_csr(musb_regs_t* musb_ // The following are defines for the bit fields in the USB_O_TXTYPE2 register. // //***************************************************************************** -#define USB_TXTYPE2_SPEED_M 0x000000C0 // Operating Speed -#define USB_TXTYPE2_SPEED_DFLT 0x00000000 // Default -#define USB_TXTYPE2_SPEED_HIGH 0x00000040 // High -#define USB_TXTYPE2_SPEED_FULL 0x00000080 // Full -#define USB_TXTYPE2_SPEED_LOW 0x000000C0 // Low -#define USB_TXTYPE2_PROTO_M 0x00000030 // Protocol -#define USB_TXTYPE2_PROTO_CTRL 0x00000000 // Control -#define USB_TXTYPE2_PROTO_ISOC 0x00000010 // Isochronous -#define USB_TXTYPE2_PROTO_BULK 0x00000020 // Bulk -#define USB_TXTYPE2_PROTO_INT 0x00000030 // Interrupt -#define USB_TXTYPE2_TEP_M 0x0000000F // Target Endpoint Number +#define USB_TXTYPE2_SPEED_M 0x00C0 // Operating Speed +#define USB_TXTYPE2_SPEED_DFLT 0x0000 // Default +#define USB_TXTYPE2_SPEED_HIGH 0x0040 // High +#define USB_TXTYPE2_SPEED_FULL 0x0080 // Full +#define USB_TXTYPE2_SPEED_LOW 0x00C0 // Low +#define USB_TXTYPE2_PROTO_M 0x0030 // Protocol +#define USB_TXTYPE2_PROTO_CTRL 0x0000 // Control +#define USB_TXTYPE2_PROTO_ISOC 0x0010 // Isochronous +#define USB_TXTYPE2_PROTO_BULK 0x0020 // Bulk +#define USB_TXTYPE2_PROTO_INT 0x0030 // Interrupt +#define USB_TXTYPE2_TEP_M 0x000F // Target Endpoint Number #define USB_TXTYPE2_TEP_S 0 //***************************************************************************** @@ -1294,31 +849,27 @@ TU_ATTR_ALWAYS_INLINE static inline musb_ep_csr_t* get_ep_csr(musb_regs_t* musb_ // register. // //***************************************************************************** -#define USB_TXINTERVAL2_TXPOLL_M \ - 0x000000FF // TX Polling -#define USB_TXINTERVAL2_NAKLMT_M \ - 0x000000FF // NAK Limit -#define USB_TXINTERVAL2_NAKLMT_S \ - 0 -#define USB_TXINTERVAL2_TXPOLL_S \ - 0 +#define USB_TXINTERVAL2_TXPOLL_M 0x00FF // TX Polling +#define USB_TXINTERVAL2_NAKLMT_M 0x00FF // NAK Limit +#define USB_TXINTERVAL2_NAKLMT_S 0 +#define USB_TXINTERVAL2_TXPOLL_S 0 //***************************************************************************** // // The following are defines for the bit fields in the USB_O_RXTYPE2 register. // //***************************************************************************** -#define USB_RXTYPE2_SPEED_M 0x000000C0 // Operating Speed -#define USB_RXTYPE2_SPEED_DFLT 0x00000000 // Default -#define USB_RXTYPE2_SPEED_HIGH 0x00000040 // High -#define USB_RXTYPE2_SPEED_FULL 0x00000080 // Full -#define USB_RXTYPE2_SPEED_LOW 0x000000C0 // Low -#define USB_RXTYPE2_PROTO_M 0x00000030 // Protocol -#define USB_RXTYPE2_PROTO_CTRL 0x00000000 // Control -#define USB_RXTYPE2_PROTO_ISOC 0x00000010 // Isochronous -#define USB_RXTYPE2_PROTO_BULK 0x00000020 // Bulk -#define USB_RXTYPE2_PROTO_INT 0x00000030 // Interrupt -#define USB_RXTYPE2_TEP_M 0x0000000F // Target Endpoint Number +#define USB_RXTYPE2_SPEED_M 0x00C0 // Operating Speed +#define USB_RXTYPE2_SPEED_DFLT 0x0000 // Default +#define USB_RXTYPE2_SPEED_HIGH 0x0040 // High +#define USB_RXTYPE2_SPEED_FULL 0x0080 // Full +#define USB_RXTYPE2_SPEED_LOW 0x00C0 // Low +#define USB_RXTYPE2_PROTO_M 0x0030 // Protocol +#define USB_RXTYPE2_PROTO_CTRL 0x0000 // Control +#define USB_RXTYPE2_PROTO_ISOC 0x0010 // Isochronous +#define USB_RXTYPE2_PROTO_BULK 0x0020 // Bulk +#define USB_RXTYPE2_PROTO_INT 0x0030 // Interrupt +#define USB_RXTYPE2_TEP_M 0x000F // Target Endpoint Number #define USB_RXTYPE2_TEP_S 0 //***************************************************************************** @@ -1327,21 +878,17 @@ TU_ATTR_ALWAYS_INLINE static inline musb_ep_csr_t* get_ep_csr(musb_regs_t* musb_ // register. // //***************************************************************************** -#define USB_RXINTERVAL2_TXPOLL_M \ - 0x000000FF // RX Polling -#define USB_RXINTERVAL2_NAKLMT_M \ - 0x000000FF // NAK Limit -#define USB_RXINTERVAL2_TXPOLL_S \ - 0 -#define USB_RXINTERVAL2_NAKLMT_S \ - 0 +#define USB_RXINTERVAL2_TXPOLL_M 0x00FF // RX Polling +#define USB_RXINTERVAL2_NAKLMT_M 0x00FF // NAK Limit +#define USB_RXINTERVAL2_TXPOLL_S 0 +#define USB_RXINTERVAL2_NAKLMT_S 0 //***************************************************************************** // // The following are defines for the bit fields in the USB_O_TXMAXP3 register. // //***************************************************************************** -#define USB_TXMAXP3_MAXLOAD_M 0x000007FF // Maximum Payload +#define USB_TXMAXP3_MAXLOAD_M 0x07FF // Maximum Payload #define USB_TXMAXP3_MAXLOAD_S 0 //***************************************************************************** @@ -1349,37 +896,37 @@ TU_ATTR_ALWAYS_INLINE static inline musb_ep_csr_t* get_ep_csr(musb_regs_t* musb_ // The following are defines for the bit fields in the USB_O_TXCSRL3 register. // //***************************************************************************** -#define USB_TXCSRL3_NAKTO 0x00000080 // NAK Timeout -#define USB_TXCSRL3_CLRDT 0x00000040 // Clear Data Toggle -#define USB_TXCSRL3_STALLED 0x00000020 // Endpoint Stalled -#define USB_TXCSRL3_SETUP 0x00000010 // Setup Packet -#define USB_TXCSRL3_STALL 0x00000010 // Send STALL -#define USB_TXCSRL3_FLUSH 0x00000008 // Flush FIFO -#define USB_TXCSRL3_ERROR 0x00000004 // Error -#define USB_TXCSRL3_UNDRN 0x00000004 // Underrun -#define USB_TXCSRL3_FIFONE 0x00000002 // FIFO Not Empty -#define USB_TXCSRL3_TXRDY 0x00000001 // Transmit Packet Ready +#define USB_TXCSRL3_NAKTO 0x0080 // NAK Timeout +#define USB_TXCSRL3_CLRDT 0x0040 // Clear Data Toggle +#define USB_TXCSRL3_STALLED 0x0020 // Endpoint Stalled +#define USB_TXCSRL3_SETUP 0x0010 // Setup Packet +#define USB_TXCSRL3_STALL 0x0010 // Send STALL +#define USB_TXCSRL3_FLUSH 0x0008 // Flush FIFO +#define USB_TXCSRL3_ERROR 0x0004 // Error +#define USB_TXCSRL3_UNDRN 0x0004 // Underrun +#define USB_TXCSRL3_FIFONE 0x0002 // FIFO Not Empty +#define USB_TXCSRL3_TXRDY 0x0001 // Transmit Packet Ready //***************************************************************************** // // The following are defines for the bit fields in the USB_O_TXCSRH3 register. // //***************************************************************************** -#define USB_TXCSRH3_AUTOSET 0x00000080 // Auto Set -#define USB_TXCSRH3_ISO 0x00000040 // Isochronous Transfers -#define USB_TXCSRH3_MODE 0x00000020 // Mode -#define USB_TXCSRH3_DMAEN 0x00000010 // DMA Request Enable -#define USB_TXCSRH3_FDT 0x00000008 // Force Data Toggle -#define USB_TXCSRH3_DMAMOD 0x00000004 // DMA Request Mode -#define USB_TXCSRH3_DTWE 0x00000002 // Data Toggle Write Enable -#define USB_TXCSRH3_DT 0x00000001 // Data Toggle +#define USB_TXCSRH3_AUTOSET 0x0080 // Auto Set +#define USB_TXCSRH3_ISO 0x0040 // Isochronous Transfers +#define USB_TXCSRH3_MODE 0x0020 // Mode +#define USB_TXCSRH3_DMAEN 0x0010 // DMA Request Enable +#define USB_TXCSRH3_FDT 0x0008 // Force Data Toggle +#define USB_TXCSRH3_DMAMOD 0x0004 // DMA Request Mode +#define USB_TXCSRH3_DTWE 0x0002 // Data Toggle Write Enable +#define USB_TXCSRH3_DT 0x0001 // Data Toggle //***************************************************************************** // // The following are defines for the bit fields in the USB_O_RXMAXP3 register. // //***************************************************************************** -#define USB_RXMAXP3_MAXLOAD_M 0x000007FF // Maximum Payload +#define USB_RXMAXP3_MAXLOAD_M 0x07FF // Maximum Payload #define USB_RXMAXP3_MAXLOAD_S 0 //***************************************************************************** @@ -1387,33 +934,33 @@ TU_ATTR_ALWAYS_INLINE static inline musb_ep_csr_t* get_ep_csr(musb_regs_t* musb_ // The following are defines for the bit fields in the USB_O_RXCSRL3 register. // //***************************************************************************** -#define USB_RXCSRL3_CLRDT 0x00000080 // Clear Data Toggle -#define USB_RXCSRL3_STALLED 0x00000040 // Endpoint Stalled -#define USB_RXCSRL3_STALL 0x00000020 // Send STALL -#define USB_RXCSRL3_REQPKT 0x00000020 // Request Packet -#define USB_RXCSRL3_FLUSH 0x00000010 // Flush FIFO -#define USB_RXCSRL3_DATAERR 0x00000008 // Data Error -#define USB_RXCSRL3_NAKTO 0x00000008 // NAK Timeout -#define USB_RXCSRL3_ERROR 0x00000004 // Error -#define USB_RXCSRL3_OVER 0x00000004 // Overrun -#define USB_RXCSRL3_FULL 0x00000002 // FIFO Full -#define USB_RXCSRL3_RXRDY 0x00000001 // Receive Packet Ready +#define USB_RXCSRL3_CLRDT 0x0080 // Clear Data Toggle +#define USB_RXCSRL3_STALLED 0x0040 // Endpoint Stalled +#define USB_RXCSRL3_STALL 0x0020 // Send STALL +#define USB_RXCSRL3_REQPKT 0x0020 // Request Packet +#define USB_RXCSRL3_FLUSH 0x0010 // Flush FIFO +#define USB_RXCSRL3_DATAERR 0x0008 // Data Error +#define USB_RXCSRL3_NAKTO 0x0008 // NAK Timeout +#define USB_RXCSRL3_ERROR 0x0004 // Error +#define USB_RXCSRL3_OVER 0x0004 // Overrun +#define USB_RXCSRL3_FULL 0x0002 // FIFO Full +#define USB_RXCSRL3_RXRDY 0x0001 // Receive Packet Ready //***************************************************************************** // // The following are defines for the bit fields in the USB_O_RXCSRH3 register. // //***************************************************************************** -#define USB_RXCSRH3_AUTOCL 0x00000080 // Auto Clear -#define USB_RXCSRH3_AUTORQ 0x00000040 // Auto Request -#define USB_RXCSRH3_ISO 0x00000040 // Isochronous Transfers -#define USB_RXCSRH3_DMAEN 0x00000020 // DMA Request Enable -#define USB_RXCSRH3_DISNYET 0x00000010 // Disable NYET -#define USB_RXCSRH3_PIDERR 0x00000010 // PID Error -#define USB_RXCSRH3_DMAMOD 0x00000008 // DMA Request Mode -#define USB_RXCSRH3_DTWE 0x00000004 // Data Toggle Write Enable -#define USB_RXCSRH3_DT 0x00000002 // Data Toggle -#define USB_RXCSRH3_INCOMPRX 0x00000001 // Incomplete RX Transmission +#define USB_RXCSRH3_AUTOCL 0x0080 // Auto Clear +#define USB_RXCSRH3_AUTORQ 0x0040 // Auto Request +#define USB_RXCSRH3_ISO 0x0040 // Isochronous Transfers +#define USB_RXCSRH3_DMAEN 0x0020 // DMA Request Enable +#define USB_RXCSRH3_DISNYET 0x0010 // Disable NYET +#define USB_RXCSRH3_PIDERR 0x0010 // PID Error +#define USB_RXCSRH3_DMAMOD 0x0008 // DMA Request Mode +#define USB_RXCSRH3_DTWE 0x0004 // Data Toggle Write Enable +#define USB_RXCSRH3_DT 0x0002 // Data Toggle +#define USB_RXCSRH3_INCOMPRX 0x0001 // Incomplete RX Transmission // Status //***************************************************************************** @@ -1421,7 +968,7 @@ TU_ATTR_ALWAYS_INLINE static inline musb_ep_csr_t* get_ep_csr(musb_regs_t* musb_ // The following are defines for the bit fields in the USB_O_RXCOUNT3 register. // //***************************************************************************** -#define USB_RXCOUNT3_COUNT_M 0x00001FFF // Receive Packet Count +#define USB_RXCOUNT3_COUNT_M 0x1FFF // Receive Packet Count #define USB_RXCOUNT3_COUNT_S 0 //***************************************************************************** @@ -1429,17 +976,17 @@ TU_ATTR_ALWAYS_INLINE static inline musb_ep_csr_t* get_ep_csr(musb_regs_t* musb_ // The following are defines for the bit fields in the USB_O_TXTYPE3 register. // //***************************************************************************** -#define USB_TXTYPE3_SPEED_M 0x000000C0 // Operating Speed -#define USB_TXTYPE3_SPEED_DFLT 0x00000000 // Default -#define USB_TXTYPE3_SPEED_HIGH 0x00000040 // High -#define USB_TXTYPE3_SPEED_FULL 0x00000080 // Full -#define USB_TXTYPE3_SPEED_LOW 0x000000C0 // Low -#define USB_TXTYPE3_PROTO_M 0x00000030 // Protocol -#define USB_TXTYPE3_PROTO_CTRL 0x00000000 // Control -#define USB_TXTYPE3_PROTO_ISOC 0x00000010 // Isochronous -#define USB_TXTYPE3_PROTO_BULK 0x00000020 // Bulk -#define USB_TXTYPE3_PROTO_INT 0x00000030 // Interrupt -#define USB_TXTYPE3_TEP_M 0x0000000F // Target Endpoint Number +#define USB_TXTYPE3_SPEED_M 0x00C0 // Operating Speed +#define USB_TXTYPE3_SPEED_DFLT 0x0000 // Default +#define USB_TXTYPE3_SPEED_HIGH 0x0040 // High +#define USB_TXTYPE3_SPEED_FULL 0x0080 // Full +#define USB_TXTYPE3_SPEED_LOW 0x00C0 // Low +#define USB_TXTYPE3_PROTO_M 0x0030 // Protocol +#define USB_TXTYPE3_PROTO_CTRL 0x0000 // Control +#define USB_TXTYPE3_PROTO_ISOC 0x0010 // Isochronous +#define USB_TXTYPE3_PROTO_BULK 0x0020 // Bulk +#define USB_TXTYPE3_PROTO_INT 0x0030 // Interrupt +#define USB_TXTYPE3_TEP_M 0x000F // Target Endpoint Number #define USB_TXTYPE3_TEP_S 0 //***************************************************************************** @@ -1448,31 +995,27 @@ TU_ATTR_ALWAYS_INLINE static inline musb_ep_csr_t* get_ep_csr(musb_regs_t* musb_ // register. // //***************************************************************************** -#define USB_TXINTERVAL3_TXPOLL_M \ - 0x000000FF // TX Polling -#define USB_TXINTERVAL3_NAKLMT_M \ - 0x000000FF // NAK Limit -#define USB_TXINTERVAL3_TXPOLL_S \ - 0 -#define USB_TXINTERVAL3_NAKLMT_S \ - 0 +#define USB_TXINTERVAL3_TXPOLL_M 0x00FF // TX Polling +#define USB_TXINTERVAL3_NAKLMT_M 0x00FF // NAK Limit +#define USB_TXINTERVAL3_TXPOLL_S 0 +#define USB_TXINTERVAL3_NAKLMT_S 0 //***************************************************************************** // // The following are defines for the bit fields in the USB_O_RXTYPE3 register. // //***************************************************************************** -#define USB_RXTYPE3_SPEED_M 0x000000C0 // Operating Speed -#define USB_RXTYPE3_SPEED_DFLT 0x00000000 // Default -#define USB_RXTYPE3_SPEED_HIGH 0x00000040 // High -#define USB_RXTYPE3_SPEED_FULL 0x00000080 // Full -#define USB_RXTYPE3_SPEED_LOW 0x000000C0 // Low -#define USB_RXTYPE3_PROTO_M 0x00000030 // Protocol -#define USB_RXTYPE3_PROTO_CTRL 0x00000000 // Control -#define USB_RXTYPE3_PROTO_ISOC 0x00000010 // Isochronous -#define USB_RXTYPE3_PROTO_BULK 0x00000020 // Bulk -#define USB_RXTYPE3_PROTO_INT 0x00000030 // Interrupt -#define USB_RXTYPE3_TEP_M 0x0000000F // Target Endpoint Number +#define USB_RXTYPE3_SPEED_M 0x00C0 // Operating Speed +#define USB_RXTYPE3_SPEED_DFLT 0x0000 // Default +#define USB_RXTYPE3_SPEED_HIGH 0x0040 // High +#define USB_RXTYPE3_SPEED_FULL 0x0080 // Full +#define USB_RXTYPE3_SPEED_LOW 0x00C0 // Low +#define USB_RXTYPE3_PROTO_M 0x0030 // Protocol +#define USB_RXTYPE3_PROTO_CTRL 0x0000 // Control +#define USB_RXTYPE3_PROTO_ISOC 0x0010 // Isochronous +#define USB_RXTYPE3_PROTO_BULK 0x0020 // Bulk +#define USB_RXTYPE3_PROTO_INT 0x0030 // Interrupt +#define USB_RXTYPE3_TEP_M 0x000F // Target Endpoint Number #define USB_RXTYPE3_TEP_S 0 //***************************************************************************** @@ -1481,21 +1024,17 @@ TU_ATTR_ALWAYS_INLINE static inline musb_ep_csr_t* get_ep_csr(musb_regs_t* musb_ // register. // //***************************************************************************** -#define USB_RXINTERVAL3_TXPOLL_M \ - 0x000000FF // RX Polling -#define USB_RXINTERVAL3_NAKLMT_M \ - 0x000000FF // NAK Limit -#define USB_RXINTERVAL3_TXPOLL_S \ - 0 -#define USB_RXINTERVAL3_NAKLMT_S \ - 0 +#define USB_RXINTERVAL3_TXPOLL_M 0x00FF // RX Polling +#define USB_RXINTERVAL3_NAKLMT_M 0x00FF // NAK Limit +#define USB_RXINTERVAL3_TXPOLL_S 0 +#define USB_RXINTERVAL3_NAKLMT_S 0 //***************************************************************************** // // The following are defines for the bit fields in the USB_O_TXMAXP4 register. // //***************************************************************************** -#define USB_TXMAXP4_MAXLOAD_M 0x000007FF // Maximum Payload +#define USB_TXMAXP4_MAXLOAD_M 0x07FF // Maximum Payload #define USB_TXMAXP4_MAXLOAD_S 0 //***************************************************************************** @@ -1503,37 +1042,37 @@ TU_ATTR_ALWAYS_INLINE static inline musb_ep_csr_t* get_ep_csr(musb_regs_t* musb_ // The following are defines for the bit fields in the USB_O_TXCSRL4 register. // //***************************************************************************** -#define USB_TXCSRL4_NAKTO 0x00000080 // NAK Timeout -#define USB_TXCSRL4_CLRDT 0x00000040 // Clear Data Toggle -#define USB_TXCSRL4_STALLED 0x00000020 // Endpoint Stalled -#define USB_TXCSRL4_SETUP 0x00000010 // Setup Packet -#define USB_TXCSRL4_STALL 0x00000010 // Send STALL -#define USB_TXCSRL4_FLUSH 0x00000008 // Flush FIFO -#define USB_TXCSRL4_ERROR 0x00000004 // Error -#define USB_TXCSRL4_UNDRN 0x00000004 // Underrun -#define USB_TXCSRL4_FIFONE 0x00000002 // FIFO Not Empty -#define USB_TXCSRL4_TXRDY 0x00000001 // Transmit Packet Ready +#define USB_TXCSRL4_NAKTO 0x0080 // NAK Timeout +#define USB_TXCSRL4_CLRDT 0x0040 // Clear Data Toggle +#define USB_TXCSRL4_STALLED 0x0020 // Endpoint Stalled +#define USB_TXCSRL4_SETUP 0x0010 // Setup Packet +#define USB_TXCSRL4_STALL 0x0010 // Send STALL +#define USB_TXCSRL4_FLUSH 0x0008 // Flush FIFO +#define USB_TXCSRL4_ERROR 0x0004 // Error +#define USB_TXCSRL4_UNDRN 0x0004 // Underrun +#define USB_TXCSRL4_FIFONE 0x0002 // FIFO Not Empty +#define USB_TXCSRL4_TXRDY 0x0001 // Transmit Packet Ready //***************************************************************************** // // The following are defines for the bit fields in the USB_O_TXCSRH4 register. // //***************************************************************************** -#define USB_TXCSRH4_AUTOSET 0x00000080 // Auto Set -#define USB_TXCSRH4_ISO 0x00000040 // Isochronous Transfers -#define USB_TXCSRH4_MODE 0x00000020 // Mode -#define USB_TXCSRH4_DMAEN 0x00000010 // DMA Request Enable -#define USB_TXCSRH4_FDT 0x00000008 // Force Data Toggle -#define USB_TXCSRH4_DMAMOD 0x00000004 // DMA Request Mode -#define USB_TXCSRH4_DTWE 0x00000002 // Data Toggle Write Enable -#define USB_TXCSRH4_DT 0x00000001 // Data Toggle +#define USB_TXCSRH4_AUTOSET 0x0080 // Auto Set +#define USB_TXCSRH4_ISO 0x0040 // Isochronous Transfers +#define USB_TXCSRH4_MODE 0x0020 // Mode +#define USB_TXCSRH4_DMAEN 0x0010 // DMA Request Enable +#define USB_TXCSRH4_FDT 0x0008 // Force Data Toggle +#define USB_TXCSRH4_DMAMOD 0x0004 // DMA Request Mode +#define USB_TXCSRH4_DTWE 0x0002 // Data Toggle Write Enable +#define USB_TXCSRH4_DT 0x0001 // Data Toggle //***************************************************************************** // // The following are defines for the bit fields in the USB_O_RXMAXP4 register. // //***************************************************************************** -#define USB_RXMAXP4_MAXLOAD_M 0x000007FF // Maximum Payload +#define USB_RXMAXP4_MAXLOAD_M 0x07FF // Maximum Payload #define USB_RXMAXP4_MAXLOAD_S 0 //***************************************************************************** @@ -1541,33 +1080,33 @@ TU_ATTR_ALWAYS_INLINE static inline musb_ep_csr_t* get_ep_csr(musb_regs_t* musb_ // The following are defines for the bit fields in the USB_O_RXCSRL4 register. // //***************************************************************************** -#define USB_RXCSRL4_CLRDT 0x00000080 // Clear Data Toggle -#define USB_RXCSRL4_STALLED 0x00000040 // Endpoint Stalled -#define USB_RXCSRL4_STALL 0x00000020 // Send STALL -#define USB_RXCSRL4_REQPKT 0x00000020 // Request Packet -#define USB_RXCSRL4_FLUSH 0x00000010 // Flush FIFO -#define USB_RXCSRL4_NAKTO 0x00000008 // NAK Timeout -#define USB_RXCSRL4_DATAERR 0x00000008 // Data Error -#define USB_RXCSRL4_OVER 0x00000004 // Overrun -#define USB_RXCSRL4_ERROR 0x00000004 // Error -#define USB_RXCSRL4_FULL 0x00000002 // FIFO Full -#define USB_RXCSRL4_RXRDY 0x00000001 // Receive Packet Ready +#define USB_RXCSRL4_CLRDT 0x0080 // Clear Data Toggle +#define USB_RXCSRL4_STALLED 0x0040 // Endpoint Stalled +#define USB_RXCSRL4_STALL 0x0020 // Send STALL +#define USB_RXCSRL4_REQPKT 0x0020 // Request Packet +#define USB_RXCSRL4_FLUSH 0x0010 // Flush FIFO +#define USB_RXCSRL4_NAKTO 0x0008 // NAK Timeout +#define USB_RXCSRL4_DATAERR 0x0008 // Data Error +#define USB_RXCSRL4_OVER 0x0004 // Overrun +#define USB_RXCSRL4_ERROR 0x0004 // Error +#define USB_RXCSRL4_FULL 0x0002 // FIFO Full +#define USB_RXCSRL4_RXRDY 0x0001 // Receive Packet Ready //***************************************************************************** // // The following are defines for the bit fields in the USB_O_RXCSRH4 register. // //***************************************************************************** -#define USB_RXCSRH4_AUTOCL 0x00000080 // Auto Clear -#define USB_RXCSRH4_AUTORQ 0x00000040 // Auto Request -#define USB_RXCSRH4_ISO 0x00000040 // Isochronous Transfers -#define USB_RXCSRH4_DMAEN 0x00000020 // DMA Request Enable -#define USB_RXCSRH4_DISNYET 0x00000010 // Disable NYET -#define USB_RXCSRH4_PIDERR 0x00000010 // PID Error -#define USB_RXCSRH4_DMAMOD 0x00000008 // DMA Request Mode -#define USB_RXCSRH4_DTWE 0x00000004 // Data Toggle Write Enable -#define USB_RXCSRH4_DT 0x00000002 // Data Toggle -#define USB_RXCSRH4_INCOMPRX 0x00000001 // Incomplete RX Transmission +#define USB_RXCSRH4_AUTOCL 0x0080 // Auto Clear +#define USB_RXCSRH4_AUTORQ 0x0040 // Auto Request +#define USB_RXCSRH4_ISO 0x0040 // Isochronous Transfers +#define USB_RXCSRH4_DMAEN 0x0020 // DMA Request Enable +#define USB_RXCSRH4_DISNYET 0x0010 // Disable NYET +#define USB_RXCSRH4_PIDERR 0x0010 // PID Error +#define USB_RXCSRH4_DMAMOD 0x0008 // DMA Request Mode +#define USB_RXCSRH4_DTWE 0x0004 // Data Toggle Write Enable +#define USB_RXCSRH4_DT 0x0002 // Data Toggle +#define USB_RXCSRH4_INCOMPRX 0x0001 // Incomplete RX Transmission // Status //***************************************************************************** @@ -1575,7 +1114,7 @@ TU_ATTR_ALWAYS_INLINE static inline musb_ep_csr_t* get_ep_csr(musb_regs_t* musb_ // The following are defines for the bit fields in the USB_O_RXCOUNT4 register. // //***************************************************************************** -#define USB_RXCOUNT4_COUNT_M 0x00001FFF // Receive Packet Count +#define USB_RXCOUNT4_COUNT_M 0x1FFF // Receive Packet Count #define USB_RXCOUNT4_COUNT_S 0 //***************************************************************************** @@ -1583,17 +1122,17 @@ TU_ATTR_ALWAYS_INLINE static inline musb_ep_csr_t* get_ep_csr(musb_regs_t* musb_ // The following are defines for the bit fields in the USB_O_TXTYPE4 register. // //***************************************************************************** -#define USB_TXTYPE4_SPEED_M 0x000000C0 // Operating Speed -#define USB_TXTYPE4_SPEED_DFLT 0x00000000 // Default -#define USB_TXTYPE4_SPEED_HIGH 0x00000040 // High -#define USB_TXTYPE4_SPEED_FULL 0x00000080 // Full -#define USB_TXTYPE4_SPEED_LOW 0x000000C0 // Low -#define USB_TXTYPE4_PROTO_M 0x00000030 // Protocol -#define USB_TXTYPE4_PROTO_CTRL 0x00000000 // Control -#define USB_TXTYPE4_PROTO_ISOC 0x00000010 // Isochronous -#define USB_TXTYPE4_PROTO_BULK 0x00000020 // Bulk -#define USB_TXTYPE4_PROTO_INT 0x00000030 // Interrupt -#define USB_TXTYPE4_TEP_M 0x0000000F // Target Endpoint Number +#define USB_TXTYPE4_SPEED_M 0x00C0 // Operating Speed +#define USB_TXTYPE4_SPEED_DFLT 0x0000 // Default +#define USB_TXTYPE4_SPEED_HIGH 0x0040 // High +#define USB_TXTYPE4_SPEED_FULL 0x0080 // Full +#define USB_TXTYPE4_SPEED_LOW 0x00C0 // Low +#define USB_TXTYPE4_PROTO_M 0x0030 // Protocol +#define USB_TXTYPE4_PROTO_CTRL 0x0000 // Control +#define USB_TXTYPE4_PROTO_ISOC 0x0010 // Isochronous +#define USB_TXTYPE4_PROTO_BULK 0x0020 // Bulk +#define USB_TXTYPE4_PROTO_INT 0x0030 // Interrupt +#define USB_TXTYPE4_TEP_M 0x000F // Target Endpoint Number #define USB_TXTYPE4_TEP_S 0 //***************************************************************************** @@ -1602,31 +1141,27 @@ TU_ATTR_ALWAYS_INLINE static inline musb_ep_csr_t* get_ep_csr(musb_regs_t* musb_ // register. // //***************************************************************************** -#define USB_TXINTERVAL4_TXPOLL_M \ - 0x000000FF // TX Polling -#define USB_TXINTERVAL4_NAKLMT_M \ - 0x000000FF // NAK Limit -#define USB_TXINTERVAL4_NAKLMT_S \ - 0 -#define USB_TXINTERVAL4_TXPOLL_S \ - 0 +#define USB_TXINTERVAL4_TXPOLL_M 0x00FF // TX Polling +#define USB_TXINTERVAL4_NAKLMT_M 0x00FF // NAK Limit +#define USB_TXINTERVAL4_NAKLMT_S 0 +#define USB_TXINTERVAL4_TXPOLL_S 0 //***************************************************************************** // // The following are defines for the bit fields in the USB_O_RXTYPE4 register. // //***************************************************************************** -#define USB_RXTYPE4_SPEED_M 0x000000C0 // Operating Speed -#define USB_RXTYPE4_SPEED_DFLT 0x00000000 // Default -#define USB_RXTYPE4_SPEED_HIGH 0x00000040 // High -#define USB_RXTYPE4_SPEED_FULL 0x00000080 // Full -#define USB_RXTYPE4_SPEED_LOW 0x000000C0 // Low -#define USB_RXTYPE4_PROTO_M 0x00000030 // Protocol -#define USB_RXTYPE4_PROTO_CTRL 0x00000000 // Control -#define USB_RXTYPE4_PROTO_ISOC 0x00000010 // Isochronous -#define USB_RXTYPE4_PROTO_BULK 0x00000020 // Bulk -#define USB_RXTYPE4_PROTO_INT 0x00000030 // Interrupt -#define USB_RXTYPE4_TEP_M 0x0000000F // Target Endpoint Number +#define USB_RXTYPE4_SPEED_M 0x00C0 // Operating Speed +#define USB_RXTYPE4_SPEED_DFLT 0x0000 // Default +#define USB_RXTYPE4_SPEED_HIGH 0x0040 // High +#define USB_RXTYPE4_SPEED_FULL 0x0080 // Full +#define USB_RXTYPE4_SPEED_LOW 0x00C0 // Low +#define USB_RXTYPE4_PROTO_M 0x0030 // Protocol +#define USB_RXTYPE4_PROTO_CTRL 0x0000 // Control +#define USB_RXTYPE4_PROTO_ISOC 0x0010 // Isochronous +#define USB_RXTYPE4_PROTO_BULK 0x0020 // Bulk +#define USB_RXTYPE4_PROTO_INT 0x0030 // Interrupt +#define USB_RXTYPE4_TEP_M 0x000F // Target Endpoint Number #define USB_RXTYPE4_TEP_S 0 //***************************************************************************** @@ -1635,21 +1170,17 @@ TU_ATTR_ALWAYS_INLINE static inline musb_ep_csr_t* get_ep_csr(musb_regs_t* musb_ // register. // //***************************************************************************** -#define USB_RXINTERVAL4_TXPOLL_M \ - 0x000000FF // RX Polling -#define USB_RXINTERVAL4_NAKLMT_M \ - 0x000000FF // NAK Limit -#define USB_RXINTERVAL4_NAKLMT_S \ - 0 -#define USB_RXINTERVAL4_TXPOLL_S \ - 0 +#define USB_RXINTERVAL4_TXPOLL_M 0x00FF // RX Polling +#define USB_RXINTERVAL4_NAKLMT_M 0x00FF // NAK Limit +#define USB_RXINTERVAL4_NAKLMT_S 0 +#define USB_RXINTERVAL4_TXPOLL_S 0 //***************************************************************************** // // The following are defines for the bit fields in the USB_O_TXMAXP5 register. // //***************************************************************************** -#define USB_TXMAXP5_MAXLOAD_M 0x000007FF // Maximum Payload +#define USB_TXMAXP5_MAXLOAD_M 0x07FF // Maximum Payload #define USB_TXMAXP5_MAXLOAD_S 0 //***************************************************************************** @@ -1657,37 +1188,37 @@ TU_ATTR_ALWAYS_INLINE static inline musb_ep_csr_t* get_ep_csr(musb_regs_t* musb_ // The following are defines for the bit fields in the USB_O_TXCSRL5 register. // //***************************************************************************** -#define USB_TXCSRL5_NAKTO 0x00000080 // NAK Timeout -#define USB_TXCSRL5_CLRDT 0x00000040 // Clear Data Toggle -#define USB_TXCSRL5_STALLED 0x00000020 // Endpoint Stalled -#define USB_TXCSRL5_SETUP 0x00000010 // Setup Packet -#define USB_TXCSRL5_STALL 0x00000010 // Send STALL -#define USB_TXCSRL5_FLUSH 0x00000008 // Flush FIFO -#define USB_TXCSRL5_ERROR 0x00000004 // Error -#define USB_TXCSRL5_UNDRN 0x00000004 // Underrun -#define USB_TXCSRL5_FIFONE 0x00000002 // FIFO Not Empty -#define USB_TXCSRL5_TXRDY 0x00000001 // Transmit Packet Ready +#define USB_TXCSRL5_NAKTO 0x0080 // NAK Timeout +#define USB_TXCSRL5_CLRDT 0x0040 // Clear Data Toggle +#define USB_TXCSRL5_STALLED 0x0020 // Endpoint Stalled +#define USB_TXCSRL5_SETUP 0x0010 // Setup Packet +#define USB_TXCSRL5_STALL 0x0010 // Send STALL +#define USB_TXCSRL5_FLUSH 0x0008 // Flush FIFO +#define USB_TXCSRL5_ERROR 0x0004 // Error +#define USB_TXCSRL5_UNDRN 0x0004 // Underrun +#define USB_TXCSRL5_FIFONE 0x0002 // FIFO Not Empty +#define USB_TXCSRL5_TXRDY 0x0001 // Transmit Packet Ready //***************************************************************************** // // The following are defines for the bit fields in the USB_O_TXCSRH5 register. // //***************************************************************************** -#define USB_TXCSRH5_AUTOSET 0x00000080 // Auto Set -#define USB_TXCSRH5_ISO 0x00000040 // Isochronous Transfers -#define USB_TXCSRH5_MODE 0x00000020 // Mode -#define USB_TXCSRH5_DMAEN 0x00000010 // DMA Request Enable -#define USB_TXCSRH5_FDT 0x00000008 // Force Data Toggle -#define USB_TXCSRH5_DMAMOD 0x00000004 // DMA Request Mode -#define USB_TXCSRH5_DTWE 0x00000002 // Data Toggle Write Enable -#define USB_TXCSRH5_DT 0x00000001 // Data Toggle +#define USB_TXCSRH5_AUTOSET 0x0080 // Auto Set +#define USB_TXCSRH5_ISO 0x0040 // Isochronous Transfers +#define USB_TXCSRH5_MODE 0x0020 // Mode +#define USB_TXCSRH5_DMAEN 0x0010 // DMA Request Enable +#define USB_TXCSRH5_FDT 0x0008 // Force Data Toggle +#define USB_TXCSRH5_DMAMOD 0x0004 // DMA Request Mode +#define USB_TXCSRH5_DTWE 0x0002 // Data Toggle Write Enable +#define USB_TXCSRH5_DT 0x0001 // Data Toggle //***************************************************************************** // // The following are defines for the bit fields in the USB_O_RXMAXP5 register. // //***************************************************************************** -#define USB_RXMAXP5_MAXLOAD_M 0x000007FF // Maximum Payload +#define USB_RXMAXP5_MAXLOAD_M 0x07FF // Maximum Payload #define USB_RXMAXP5_MAXLOAD_S 0 //***************************************************************************** @@ -1695,33 +1226,33 @@ TU_ATTR_ALWAYS_INLINE static inline musb_ep_csr_t* get_ep_csr(musb_regs_t* musb_ // The following are defines for the bit fields in the USB_O_RXCSRL5 register. // //***************************************************************************** -#define USB_RXCSRL5_CLRDT 0x00000080 // Clear Data Toggle -#define USB_RXCSRL5_STALLED 0x00000040 // Endpoint Stalled -#define USB_RXCSRL5_STALL 0x00000020 // Send STALL -#define USB_RXCSRL5_REQPKT 0x00000020 // Request Packet -#define USB_RXCSRL5_FLUSH 0x00000010 // Flush FIFO -#define USB_RXCSRL5_NAKTO 0x00000008 // NAK Timeout -#define USB_RXCSRL5_DATAERR 0x00000008 // Data Error -#define USB_RXCSRL5_ERROR 0x00000004 // Error -#define USB_RXCSRL5_OVER 0x00000004 // Overrun -#define USB_RXCSRL5_FULL 0x00000002 // FIFO Full -#define USB_RXCSRL5_RXRDY 0x00000001 // Receive Packet Ready +#define USB_RXCSRL5_CLRDT 0x0080 // Clear Data Toggle +#define USB_RXCSRL5_STALLED 0x0040 // Endpoint Stalled +#define USB_RXCSRL5_STALL 0x0020 // Send STALL +#define USB_RXCSRL5_REQPKT 0x0020 // Request Packet +#define USB_RXCSRL5_FLUSH 0x0010 // Flush FIFO +#define USB_RXCSRL5_NAKTO 0x0008 // NAK Timeout +#define USB_RXCSRL5_DATAERR 0x0008 // Data Error +#define USB_RXCSRL5_ERROR 0x0004 // Error +#define USB_RXCSRL5_OVER 0x0004 // Overrun +#define USB_RXCSRL5_FULL 0x0002 // FIFO Full +#define USB_RXCSRL5_RXRDY 0x0001 // Receive Packet Ready //***************************************************************************** // // The following are defines for the bit fields in the USB_O_RXCSRH5 register. // //***************************************************************************** -#define USB_RXCSRH5_AUTOCL 0x00000080 // Auto Clear -#define USB_RXCSRH5_AUTORQ 0x00000040 // Auto Request -#define USB_RXCSRH5_ISO 0x00000040 // Isochronous Transfers -#define USB_RXCSRH5_DMAEN 0x00000020 // DMA Request Enable -#define USB_RXCSRH5_DISNYET 0x00000010 // Disable NYET -#define USB_RXCSRH5_PIDERR 0x00000010 // PID Error -#define USB_RXCSRH5_DMAMOD 0x00000008 // DMA Request Mode -#define USB_RXCSRH5_DTWE 0x00000004 // Data Toggle Write Enable -#define USB_RXCSRH5_DT 0x00000002 // Data Toggle -#define USB_RXCSRH5_INCOMPRX 0x00000001 // Incomplete RX Transmission +#define USB_RXCSRH5_AUTOCL 0x0080 // Auto Clear +#define USB_RXCSRH5_AUTORQ 0x0040 // Auto Request +#define USB_RXCSRH5_ISO 0x0040 // Isochronous Transfers +#define USB_RXCSRH5_DMAEN 0x0020 // DMA Request Enable +#define USB_RXCSRH5_DISNYET 0x0010 // Disable NYET +#define USB_RXCSRH5_PIDERR 0x0010 // PID Error +#define USB_RXCSRH5_DMAMOD 0x0008 // DMA Request Mode +#define USB_RXCSRH5_DTWE 0x0004 // Data Toggle Write Enable +#define USB_RXCSRH5_DT 0x0002 // Data Toggle +#define USB_RXCSRH5_INCOMPRX 0x0001 // Incomplete RX Transmission // Status //***************************************************************************** @@ -1729,7 +1260,7 @@ TU_ATTR_ALWAYS_INLINE static inline musb_ep_csr_t* get_ep_csr(musb_regs_t* musb_ // The following are defines for the bit fields in the USB_O_RXCOUNT5 register. // //***************************************************************************** -#define USB_RXCOUNT5_COUNT_M 0x00001FFF // Receive Packet Count +#define USB_RXCOUNT5_COUNT_M 0x1FFF // Receive Packet Count #define USB_RXCOUNT5_COUNT_S 0 //***************************************************************************** @@ -1737,17 +1268,17 @@ TU_ATTR_ALWAYS_INLINE static inline musb_ep_csr_t* get_ep_csr(musb_regs_t* musb_ // The following are defines for the bit fields in the USB_O_TXTYPE5 register. // //***************************************************************************** -#define USB_TXTYPE5_SPEED_M 0x000000C0 // Operating Speed -#define USB_TXTYPE5_SPEED_DFLT 0x00000000 // Default -#define USB_TXTYPE5_SPEED_HIGH 0x00000040 // High -#define USB_TXTYPE5_SPEED_FULL 0x00000080 // Full -#define USB_TXTYPE5_SPEED_LOW 0x000000C0 // Low -#define USB_TXTYPE5_PROTO_M 0x00000030 // Protocol -#define USB_TXTYPE5_PROTO_CTRL 0x00000000 // Control -#define USB_TXTYPE5_PROTO_ISOC 0x00000010 // Isochronous -#define USB_TXTYPE5_PROTO_BULK 0x00000020 // Bulk -#define USB_TXTYPE5_PROTO_INT 0x00000030 // Interrupt -#define USB_TXTYPE5_TEP_M 0x0000000F // Target Endpoint Number +#define USB_TXTYPE5_SPEED_M 0x00C0 // Operating Speed +#define USB_TXTYPE5_SPEED_DFLT 0x0000 // Default +#define USB_TXTYPE5_SPEED_HIGH 0x0040 // High +#define USB_TXTYPE5_SPEED_FULL 0x0080 // Full +#define USB_TXTYPE5_SPEED_LOW 0x00C0 // Low +#define USB_TXTYPE5_PROTO_M 0x0030 // Protocol +#define USB_TXTYPE5_PROTO_CTRL 0x0000 // Control +#define USB_TXTYPE5_PROTO_ISOC 0x0010 // Isochronous +#define USB_TXTYPE5_PROTO_BULK 0x0020 // Bulk +#define USB_TXTYPE5_PROTO_INT 0x0030 // Interrupt +#define USB_TXTYPE5_TEP_M 0x000F // Target Endpoint Number #define USB_TXTYPE5_TEP_S 0 //***************************************************************************** @@ -1756,31 +1287,27 @@ TU_ATTR_ALWAYS_INLINE static inline musb_ep_csr_t* get_ep_csr(musb_regs_t* musb_ // register. // //***************************************************************************** -#define USB_TXINTERVAL5_TXPOLL_M \ - 0x000000FF // TX Polling -#define USB_TXINTERVAL5_NAKLMT_M \ - 0x000000FF // NAK Limit -#define USB_TXINTERVAL5_NAKLMT_S \ - 0 -#define USB_TXINTERVAL5_TXPOLL_S \ - 0 +#define USB_TXINTERVAL5_TXPOLL_M 0x00FF // TX Polling +#define USB_TXINTERVAL5_NAKLMT_M 0x00FF // NAK Limit +#define USB_TXINTERVAL5_NAKLMT_S 0 +#define USB_TXINTERVAL5_TXPOLL_S 0 //***************************************************************************** // // The following are defines for the bit fields in the USB_O_RXTYPE5 register. // //***************************************************************************** -#define USB_RXTYPE5_SPEED_M 0x000000C0 // Operating Speed -#define USB_RXTYPE5_SPEED_DFLT 0x00000000 // Default -#define USB_RXTYPE5_SPEED_HIGH 0x00000040 // High -#define USB_RXTYPE5_SPEED_FULL 0x00000080 // Full -#define USB_RXTYPE5_SPEED_LOW 0x000000C0 // Low -#define USB_RXTYPE5_PROTO_M 0x00000030 // Protocol -#define USB_RXTYPE5_PROTO_CTRL 0x00000000 // Control -#define USB_RXTYPE5_PROTO_ISOC 0x00000010 // Isochronous -#define USB_RXTYPE5_PROTO_BULK 0x00000020 // Bulk -#define USB_RXTYPE5_PROTO_INT 0x00000030 // Interrupt -#define USB_RXTYPE5_TEP_M 0x0000000F // Target Endpoint Number +#define USB_RXTYPE5_SPEED_M 0x00C0 // Operating Speed +#define USB_RXTYPE5_SPEED_DFLT 0x0000 // Default +#define USB_RXTYPE5_SPEED_HIGH 0x0040 // High +#define USB_RXTYPE5_SPEED_FULL 0x0080 // Full +#define USB_RXTYPE5_SPEED_LOW 0x00C0 // Low +#define USB_RXTYPE5_PROTO_M 0x0030 // Protocol +#define USB_RXTYPE5_PROTO_CTRL 0x0000 // Control +#define USB_RXTYPE5_PROTO_ISOC 0x0010 // Isochronous +#define USB_RXTYPE5_PROTO_BULK 0x0020 // Bulk +#define USB_RXTYPE5_PROTO_INT 0x0030 // Interrupt +#define USB_RXTYPE5_TEP_M 0x000F // Target Endpoint Number #define USB_RXTYPE5_TEP_S 0 //***************************************************************************** @@ -1789,21 +1316,17 @@ TU_ATTR_ALWAYS_INLINE static inline musb_ep_csr_t* get_ep_csr(musb_regs_t* musb_ // register. // //***************************************************************************** -#define USB_RXINTERVAL5_TXPOLL_M \ - 0x000000FF // RX Polling -#define USB_RXINTERVAL5_NAKLMT_M \ - 0x000000FF // NAK Limit -#define USB_RXINTERVAL5_TXPOLL_S \ - 0 -#define USB_RXINTERVAL5_NAKLMT_S \ - 0 +#define USB_RXINTERVAL5_TXPOLL_M 0x00FF // RX Polling +#define USB_RXINTERVAL5_NAKLMT_M 0x00FF // NAK Limit +#define USB_RXINTERVAL5_TXPOLL_S 0 +#define USB_RXINTERVAL5_NAKLMT_S 0 //***************************************************************************** // // The following are defines for the bit fields in the USB_O_TXMAXP6 register. // //***************************************************************************** -#define USB_TXMAXP6_MAXLOAD_M 0x000007FF // Maximum Payload +#define USB_TXMAXP6_MAXLOAD_M 0x07FF // Maximum Payload #define USB_TXMAXP6_MAXLOAD_S 0 //***************************************************************************** @@ -1811,37 +1334,37 @@ TU_ATTR_ALWAYS_INLINE static inline musb_ep_csr_t* get_ep_csr(musb_regs_t* musb_ // The following are defines for the bit fields in the USB_O_TXCSRL6 register. // //***************************************************************************** -#define USB_TXCSRL6_NAKTO 0x00000080 // NAK Timeout -#define USB_TXCSRL6_CLRDT 0x00000040 // Clear Data Toggle -#define USB_TXCSRL6_STALLED 0x00000020 // Endpoint Stalled -#define USB_TXCSRL6_STALL 0x00000010 // Send STALL -#define USB_TXCSRL6_SETUP 0x00000010 // Setup Packet -#define USB_TXCSRL6_FLUSH 0x00000008 // Flush FIFO -#define USB_TXCSRL6_ERROR 0x00000004 // Error -#define USB_TXCSRL6_UNDRN 0x00000004 // Underrun -#define USB_TXCSRL6_FIFONE 0x00000002 // FIFO Not Empty -#define USB_TXCSRL6_TXRDY 0x00000001 // Transmit Packet Ready +#define USB_TXCSRL6_NAKTO 0x0080 // NAK Timeout +#define USB_TXCSRL6_CLRDT 0x0040 // Clear Data Toggle +#define USB_TXCSRL6_STALLED 0x0020 // Endpoint Stalled +#define USB_TXCSRL6_STALL 0x0010 // Send STALL +#define USB_TXCSRL6_SETUP 0x0010 // Setup Packet +#define USB_TXCSRL6_FLUSH 0x0008 // Flush FIFO +#define USB_TXCSRL6_ERROR 0x0004 // Error +#define USB_TXCSRL6_UNDRN 0x0004 // Underrun +#define USB_TXCSRL6_FIFONE 0x0002 // FIFO Not Empty +#define USB_TXCSRL6_TXRDY 0x0001 // Transmit Packet Ready //***************************************************************************** // // The following are defines for the bit fields in the USB_O_TXCSRH6 register. // //***************************************************************************** -#define USB_TXCSRH6_AUTOSET 0x00000080 // Auto Set -#define USB_TXCSRH6_ISO 0x00000040 // Isochronous Transfers -#define USB_TXCSRH6_MODE 0x00000020 // Mode -#define USB_TXCSRH6_DMAEN 0x00000010 // DMA Request Enable -#define USB_TXCSRH6_FDT 0x00000008 // Force Data Toggle -#define USB_TXCSRH6_DMAMOD 0x00000004 // DMA Request Mode -#define USB_TXCSRH6_DTWE 0x00000002 // Data Toggle Write Enable -#define USB_TXCSRH6_DT 0x00000001 // Data Toggle +#define USB_TXCSRH6_AUTOSET 0x0080 // Auto Set +#define USB_TXCSRH6_ISO 0x0040 // Isochronous Transfers +#define USB_TXCSRH6_MODE 0x0020 // Mode +#define USB_TXCSRH6_DMAEN 0x0010 // DMA Request Enable +#define USB_TXCSRH6_FDT 0x0008 // Force Data Toggle +#define USB_TXCSRH6_DMAMOD 0x0004 // DMA Request Mode +#define USB_TXCSRH6_DTWE 0x0002 // Data Toggle Write Enable +#define USB_TXCSRH6_DT 0x0001 // Data Toggle //***************************************************************************** // // The following are defines for the bit fields in the USB_O_RXMAXP6 register. // //***************************************************************************** -#define USB_RXMAXP6_MAXLOAD_M 0x000007FF // Maximum Payload +#define USB_RXMAXP6_MAXLOAD_M 0x07FF // Maximum Payload #define USB_RXMAXP6_MAXLOAD_S 0 //***************************************************************************** @@ -1849,33 +1372,33 @@ TU_ATTR_ALWAYS_INLINE static inline musb_ep_csr_t* get_ep_csr(musb_regs_t* musb_ // The following are defines for the bit fields in the USB_O_RXCSRL6 register. // //***************************************************************************** -#define USB_RXCSRL6_CLRDT 0x00000080 // Clear Data Toggle -#define USB_RXCSRL6_STALLED 0x00000040 // Endpoint Stalled -#define USB_RXCSRL6_REQPKT 0x00000020 // Request Packet -#define USB_RXCSRL6_STALL 0x00000020 // Send STALL -#define USB_RXCSRL6_FLUSH 0x00000010 // Flush FIFO -#define USB_RXCSRL6_NAKTO 0x00000008 // NAK Timeout -#define USB_RXCSRL6_DATAERR 0x00000008 // Data Error -#define USB_RXCSRL6_ERROR 0x00000004 // Error -#define USB_RXCSRL6_OVER 0x00000004 // Overrun -#define USB_RXCSRL6_FULL 0x00000002 // FIFO Full -#define USB_RXCSRL6_RXRDY 0x00000001 // Receive Packet Ready +#define USB_RXCSRL6_CLRDT 0x0080 // Clear Data Toggle +#define USB_RXCSRL6_STALLED 0x0040 // Endpoint Stalled +#define USB_RXCSRL6_REQPKT 0x0020 // Request Packet +#define USB_RXCSRL6_STALL 0x0020 // Send STALL +#define USB_RXCSRL6_FLUSH 0x0010 // Flush FIFO +#define USB_RXCSRL6_NAKTO 0x0008 // NAK Timeout +#define USB_RXCSRL6_DATAERR 0x0008 // Data Error +#define USB_RXCSRL6_ERROR 0x0004 // Error +#define USB_RXCSRL6_OVER 0x0004 // Overrun +#define USB_RXCSRL6_FULL 0x0002 // FIFO Full +#define USB_RXCSRL6_RXRDY 0x0001 // Receive Packet Ready //***************************************************************************** // // The following are defines for the bit fields in the USB_O_RXCSRH6 register. // //***************************************************************************** -#define USB_RXCSRH6_AUTOCL 0x00000080 // Auto Clear -#define USB_RXCSRH6_AUTORQ 0x00000040 // Auto Request -#define USB_RXCSRH6_ISO 0x00000040 // Isochronous Transfers -#define USB_RXCSRH6_DMAEN 0x00000020 // DMA Request Enable -#define USB_RXCSRH6_DISNYET 0x00000010 // Disable NYET -#define USB_RXCSRH6_PIDERR 0x00000010 // PID Error -#define USB_RXCSRH6_DMAMOD 0x00000008 // DMA Request Mode -#define USB_RXCSRH6_DTWE 0x00000004 // Data Toggle Write Enable -#define USB_RXCSRH6_DT 0x00000002 // Data Toggle -#define USB_RXCSRH6_INCOMPRX 0x00000001 // Incomplete RX Transmission +#define USB_RXCSRH6_AUTOCL 0x0080 // Auto Clear +#define USB_RXCSRH6_AUTORQ 0x0040 // Auto Request +#define USB_RXCSRH6_ISO 0x0040 // Isochronous Transfers +#define USB_RXCSRH6_DMAEN 0x0020 // DMA Request Enable +#define USB_RXCSRH6_DISNYET 0x0010 // Disable NYET +#define USB_RXCSRH6_PIDERR 0x0010 // PID Error +#define USB_RXCSRH6_DMAMOD 0x0008 // DMA Request Mode +#define USB_RXCSRH6_DTWE 0x0004 // Data Toggle Write Enable +#define USB_RXCSRH6_DT 0x0002 // Data Toggle +#define USB_RXCSRH6_INCOMPRX 0x0001 // Incomplete RX Transmission // Status //***************************************************************************** @@ -1883,7 +1406,7 @@ TU_ATTR_ALWAYS_INLINE static inline musb_ep_csr_t* get_ep_csr(musb_regs_t* musb_ // The following are defines for the bit fields in the USB_O_RXCOUNT6 register. // //***************************************************************************** -#define USB_RXCOUNT6_COUNT_M 0x00001FFF // Receive Packet Count +#define USB_RXCOUNT6_COUNT_M 0x1FFF // Receive Packet Count #define USB_RXCOUNT6_COUNT_S 0 //***************************************************************************** @@ -1891,17 +1414,17 @@ TU_ATTR_ALWAYS_INLINE static inline musb_ep_csr_t* get_ep_csr(musb_regs_t* musb_ // The following are defines for the bit fields in the USB_O_TXTYPE6 register. // //***************************************************************************** -#define USB_TXTYPE6_SPEED_M 0x000000C0 // Operating Speed -#define USB_TXTYPE6_SPEED_DFLT 0x00000000 // Default -#define USB_TXTYPE6_SPEED_HIGH 0x00000040 // High -#define USB_TXTYPE6_SPEED_FULL 0x00000080 // Full -#define USB_TXTYPE6_SPEED_LOW 0x000000C0 // Low -#define USB_TXTYPE6_PROTO_M 0x00000030 // Protocol -#define USB_TXTYPE6_PROTO_CTRL 0x00000000 // Control -#define USB_TXTYPE6_PROTO_ISOC 0x00000010 // Isochronous -#define USB_TXTYPE6_PROTO_BULK 0x00000020 // Bulk -#define USB_TXTYPE6_PROTO_INT 0x00000030 // Interrupt -#define USB_TXTYPE6_TEP_M 0x0000000F // Target Endpoint Number +#define USB_TXTYPE6_SPEED_M 0x00C0 // Operating Speed +#define USB_TXTYPE6_SPEED_DFLT 0x0000 // Default +#define USB_TXTYPE6_SPEED_HIGH 0x0040 // High +#define USB_TXTYPE6_SPEED_FULL 0x0080 // Full +#define USB_TXTYPE6_SPEED_LOW 0x00C0 // Low +#define USB_TXTYPE6_PROTO_M 0x0030 // Protocol +#define USB_TXTYPE6_PROTO_CTRL 0x0000 // Control +#define USB_TXTYPE6_PROTO_ISOC 0x0010 // Isochronous +#define USB_TXTYPE6_PROTO_BULK 0x0020 // Bulk +#define USB_TXTYPE6_PROTO_INT 0x0030 // Interrupt +#define USB_TXTYPE6_TEP_M 0x000F // Target Endpoint Number #define USB_TXTYPE6_TEP_S 0 //***************************************************************************** @@ -1910,31 +1433,27 @@ TU_ATTR_ALWAYS_INLINE static inline musb_ep_csr_t* get_ep_csr(musb_regs_t* musb_ // register. // //***************************************************************************** -#define USB_TXINTERVAL6_TXPOLL_M \ - 0x000000FF // TX Polling -#define USB_TXINTERVAL6_NAKLMT_M \ - 0x000000FF // NAK Limit -#define USB_TXINTERVAL6_TXPOLL_S \ - 0 -#define USB_TXINTERVAL6_NAKLMT_S \ - 0 +#define USB_TXINTERVAL6_TXPOLL_M 0x00FF // TX Polling +#define USB_TXINTERVAL6_NAKLMT_M 0x00FF // NAK Limit +#define USB_TXINTERVAL6_TXPOLL_S 0 +#define USB_TXINTERVAL6_NAKLMT_S 0 //***************************************************************************** // // The following are defines for the bit fields in the USB_O_RXTYPE6 register. // //***************************************************************************** -#define USB_RXTYPE6_SPEED_M 0x000000C0 // Operating Speed -#define USB_RXTYPE6_SPEED_DFLT 0x00000000 // Default -#define USB_RXTYPE6_SPEED_HIGH 0x00000040 // High -#define USB_RXTYPE6_SPEED_FULL 0x00000080 // Full -#define USB_RXTYPE6_SPEED_LOW 0x000000C0 // Low -#define USB_RXTYPE6_PROTO_M 0x00000030 // Protocol -#define USB_RXTYPE6_PROTO_CTRL 0x00000000 // Control -#define USB_RXTYPE6_PROTO_ISOC 0x00000010 // Isochronous -#define USB_RXTYPE6_PROTO_BULK 0x00000020 // Bulk -#define USB_RXTYPE6_PROTO_INT 0x00000030 // Interrupt -#define USB_RXTYPE6_TEP_M 0x0000000F // Target Endpoint Number +#define USB_RXTYPE6_SPEED_M 0x00C0 // Operating Speed +#define USB_RXTYPE6_SPEED_DFLT 0x0000 // Default +#define USB_RXTYPE6_SPEED_HIGH 0x0040 // High +#define USB_RXTYPE6_SPEED_FULL 0x0080 // Full +#define USB_RXTYPE6_SPEED_LOW 0x00C0 // Low +#define USB_RXTYPE6_PROTO_M 0x0030 // Protocol +#define USB_RXTYPE6_PROTO_CTRL 0x0000 // Control +#define USB_RXTYPE6_PROTO_ISOC 0x0010 // Isochronous +#define USB_RXTYPE6_PROTO_BULK 0x0020 // Bulk +#define USB_RXTYPE6_PROTO_INT 0x0030 // Interrupt +#define USB_RXTYPE6_TEP_M 0x000F // Target Endpoint Number #define USB_RXTYPE6_TEP_S 0 //***************************************************************************** @@ -1943,21 +1462,17 @@ TU_ATTR_ALWAYS_INLINE static inline musb_ep_csr_t* get_ep_csr(musb_regs_t* musb_ // register. // //***************************************************************************** -#define USB_RXINTERVAL6_TXPOLL_M \ - 0x000000FF // RX Polling -#define USB_RXINTERVAL6_NAKLMT_M \ - 0x000000FF // NAK Limit -#define USB_RXINTERVAL6_NAKLMT_S \ - 0 -#define USB_RXINTERVAL6_TXPOLL_S \ - 0 +#define USB_RXINTERVAL6_TXPOLL_M 0x00FF // RX Polling +#define USB_RXINTERVAL6_NAKLMT_M 0x00FF // NAK Limit +#define USB_RXINTERVAL6_NAKLMT_S 0 +#define USB_RXINTERVAL6_TXPOLL_S 0 //***************************************************************************** // // The following are defines for the bit fields in the USB_O_TXMAXP7 register. // //***************************************************************************** -#define USB_TXMAXP7_MAXLOAD_M 0x000007FF // Maximum Payload +#define USB_TXMAXP7_MAXLOAD_M 0x07FF // Maximum Payload #define USB_TXMAXP7_MAXLOAD_S 0 //***************************************************************************** @@ -1965,37 +1480,37 @@ TU_ATTR_ALWAYS_INLINE static inline musb_ep_csr_t* get_ep_csr(musb_regs_t* musb_ // The following are defines for the bit fields in the USB_O_TXCSRL7 register. // //***************************************************************************** -#define USB_TXCSRL7_NAKTO 0x00000080 // NAK Timeout -#define USB_TXCSRL7_CLRDT 0x00000040 // Clear Data Toggle -#define USB_TXCSRL7_STALLED 0x00000020 // Endpoint Stalled -#define USB_TXCSRL7_STALL 0x00000010 // Send STALL -#define USB_TXCSRL7_SETUP 0x00000010 // Setup Packet -#define USB_TXCSRL7_FLUSH 0x00000008 // Flush FIFO -#define USB_TXCSRL7_ERROR 0x00000004 // Error -#define USB_TXCSRL7_UNDRN 0x00000004 // Underrun -#define USB_TXCSRL7_FIFONE 0x00000002 // FIFO Not Empty -#define USB_TXCSRL7_TXRDY 0x00000001 // Transmit Packet Ready +#define USB_TXCSRL7_NAKTO 0x0080 // NAK Timeout +#define USB_TXCSRL7_CLRDT 0x0040 // Clear Data Toggle +#define USB_TXCSRL7_STALLED 0x0020 // Endpoint Stalled +#define USB_TXCSRL7_STALL 0x0010 // Send STALL +#define USB_TXCSRL7_SETUP 0x0010 // Setup Packet +#define USB_TXCSRL7_FLUSH 0x0008 // Flush FIFO +#define USB_TXCSRL7_ERROR 0x0004 // Error +#define USB_TXCSRL7_UNDRN 0x0004 // Underrun +#define USB_TXCSRL7_FIFONE 0x0002 // FIFO Not Empty +#define USB_TXCSRL7_TXRDY 0x0001 // Transmit Packet Ready //***************************************************************************** // // The following are defines for the bit fields in the USB_O_TXCSRH7 register. // //***************************************************************************** -#define USB_TXCSRH7_AUTOSET 0x00000080 // Auto Set -#define USB_TXCSRH7_ISO 0x00000040 // Isochronous Transfers -#define USB_TXCSRH7_MODE 0x00000020 // Mode -#define USB_TXCSRH7_DMAEN 0x00000010 // DMA Request Enable -#define USB_TXCSRH7_FDT 0x00000008 // Force Data Toggle -#define USB_TXCSRH7_DMAMOD 0x00000004 // DMA Request Mode -#define USB_TXCSRH7_DTWE 0x00000002 // Data Toggle Write Enable -#define USB_TXCSRH7_DT 0x00000001 // Data Toggle +#define USB_TXCSRH7_AUTOSET 0x0080 // Auto Set +#define USB_TXCSRH7_ISO 0x0040 // Isochronous Transfers +#define USB_TXCSRH7_MODE 0x0020 // Mode +#define USB_TXCSRH7_DMAEN 0x0010 // DMA Request Enable +#define USB_TXCSRH7_FDT 0x0008 // Force Data Toggle +#define USB_TXCSRH7_DMAMOD 0x0004 // DMA Request Mode +#define USB_TXCSRH7_DTWE 0x0002 // Data Toggle Write Enable +#define USB_TXCSRH7_DT 0x0001 // Data Toggle //***************************************************************************** // // The following are defines for the bit fields in the USB_O_RXMAXP7 register. // //***************************************************************************** -#define USB_RXMAXP7_MAXLOAD_M 0x000007FF // Maximum Payload +#define USB_RXMAXP7_MAXLOAD_M 0x07FF // Maximum Payload #define USB_RXMAXP7_MAXLOAD_S 0 //***************************************************************************** @@ -2003,33 +1518,33 @@ TU_ATTR_ALWAYS_INLINE static inline musb_ep_csr_t* get_ep_csr(musb_regs_t* musb_ // The following are defines for the bit fields in the USB_O_RXCSRL7 register. // //***************************************************************************** -#define USB_RXCSRL7_CLRDT 0x00000080 // Clear Data Toggle -#define USB_RXCSRL7_STALLED 0x00000040 // Endpoint Stalled -#define USB_RXCSRL7_REQPKT 0x00000020 // Request Packet -#define USB_RXCSRL7_STALL 0x00000020 // Send STALL -#define USB_RXCSRL7_FLUSH 0x00000010 // Flush FIFO -#define USB_RXCSRL7_DATAERR 0x00000008 // Data Error -#define USB_RXCSRL7_NAKTO 0x00000008 // NAK Timeout -#define USB_RXCSRL7_ERROR 0x00000004 // Error -#define USB_RXCSRL7_OVER 0x00000004 // Overrun -#define USB_RXCSRL7_FULL 0x00000002 // FIFO Full -#define USB_RXCSRL7_RXRDY 0x00000001 // Receive Packet Ready +#define USB_RXCSRL7_CLRDT 0x0080 // Clear Data Toggle +#define USB_RXCSRL7_STALLED 0x0040 // Endpoint Stalled +#define USB_RXCSRL7_REQPKT 0x0020 // Request Packet +#define USB_RXCSRL7_STALL 0x0020 // Send STALL +#define USB_RXCSRL7_FLUSH 0x0010 // Flush FIFO +#define USB_RXCSRL7_DATAERR 0x0008 // Data Error +#define USB_RXCSRL7_NAKTO 0x0008 // NAK Timeout +#define USB_RXCSRL7_ERROR 0x0004 // Error +#define USB_RXCSRL7_OVER 0x0004 // Overrun +#define USB_RXCSRL7_FULL 0x0002 // FIFO Full +#define USB_RXCSRL7_RXRDY 0x0001 // Receive Packet Ready //***************************************************************************** // // The following are defines for the bit fields in the USB_O_RXCSRH7 register. // //***************************************************************************** -#define USB_RXCSRH7_AUTOCL 0x00000080 // Auto Clear -#define USB_RXCSRH7_ISO 0x00000040 // Isochronous Transfers -#define USB_RXCSRH7_AUTORQ 0x00000040 // Auto Request -#define USB_RXCSRH7_DMAEN 0x00000020 // DMA Request Enable -#define USB_RXCSRH7_PIDERR 0x00000010 // PID Error -#define USB_RXCSRH7_DISNYET 0x00000010 // Disable NYET -#define USB_RXCSRH7_DMAMOD 0x00000008 // DMA Request Mode -#define USB_RXCSRH7_DTWE 0x00000004 // Data Toggle Write Enable -#define USB_RXCSRH7_DT 0x00000002 // Data Toggle -#define USB_RXCSRH7_INCOMPRX 0x00000001 // Incomplete RX Transmission +#define USB_RXCSRH7_AUTOCL 0x0080 // Auto Clear +#define USB_RXCSRH7_ISO 0x0040 // Isochronous Transfers +#define USB_RXCSRH7_AUTORQ 0x0040 // Auto Request +#define USB_RXCSRH7_DMAEN 0x0020 // DMA Request Enable +#define USB_RXCSRH7_PIDERR 0x0010 // PID Error +#define USB_RXCSRH7_DISNYET 0x0010 // Disable NYET +#define USB_RXCSRH7_DMAMOD 0x0008 // DMA Request Mode +#define USB_RXCSRH7_DTWE 0x0004 // Data Toggle Write Enable +#define USB_RXCSRH7_DT 0x0002 // Data Toggle +#define USB_RXCSRH7_INCOMPRX 0x0001 // Incomplete RX Transmission // Status //***************************************************************************** @@ -2037,7 +1552,7 @@ TU_ATTR_ALWAYS_INLINE static inline musb_ep_csr_t* get_ep_csr(musb_regs_t* musb_ // The following are defines for the bit fields in the USB_O_RXCOUNT7 register. // //***************************************************************************** -#define USB_RXCOUNT7_COUNT_M 0x00001FFF // Receive Packet Count +#define USB_RXCOUNT7_COUNT_M 0x1FFF // Receive Packet Count #define USB_RXCOUNT7_COUNT_S 0 //***************************************************************************** @@ -2045,17 +1560,17 @@ TU_ATTR_ALWAYS_INLINE static inline musb_ep_csr_t* get_ep_csr(musb_regs_t* musb_ // The following are defines for the bit fields in the USB_O_TXTYPE7 register. // //***************************************************************************** -#define USB_TXTYPE7_SPEED_M 0x000000C0 // Operating Speed -#define USB_TXTYPE7_SPEED_DFLT 0x00000000 // Default -#define USB_TXTYPE7_SPEED_HIGH 0x00000040 // High -#define USB_TXTYPE7_SPEED_FULL 0x00000080 // Full -#define USB_TXTYPE7_SPEED_LOW 0x000000C0 // Low -#define USB_TXTYPE7_PROTO_M 0x00000030 // Protocol -#define USB_TXTYPE7_PROTO_CTRL 0x00000000 // Control -#define USB_TXTYPE7_PROTO_ISOC 0x00000010 // Isochronous -#define USB_TXTYPE7_PROTO_BULK 0x00000020 // Bulk -#define USB_TXTYPE7_PROTO_INT 0x00000030 // Interrupt -#define USB_TXTYPE7_TEP_M 0x0000000F // Target Endpoint Number +#define USB_TXTYPE7_SPEED_M 0x00C0 // Operating Speed +#define USB_TXTYPE7_SPEED_DFLT 0x0000 // Default +#define USB_TXTYPE7_SPEED_HIGH 0x0040 // High +#define USB_TXTYPE7_SPEED_FULL 0x0080 // Full +#define USB_TXTYPE7_SPEED_LOW 0x00C0 // Low +#define USB_TXTYPE7_PROTO_M 0x0030 // Protocol +#define USB_TXTYPE7_PROTO_CTRL 0x0000 // Control +#define USB_TXTYPE7_PROTO_ISOC 0x0010 // Isochronous +#define USB_TXTYPE7_PROTO_BULK 0x0020 // Bulk +#define USB_TXTYPE7_PROTO_INT 0x0030 // Interrupt +#define USB_TXTYPE7_TEP_M 0x000F // Target Endpoint Number #define USB_TXTYPE7_TEP_S 0 //***************************************************************************** @@ -2064,31 +1579,27 @@ TU_ATTR_ALWAYS_INLINE static inline musb_ep_csr_t* get_ep_csr(musb_regs_t* musb_ // register. // //***************************************************************************** -#define USB_TXINTERVAL7_TXPOLL_M \ - 0x000000FF // TX Polling -#define USB_TXINTERVAL7_NAKLMT_M \ - 0x000000FF // NAK Limit -#define USB_TXINTERVAL7_NAKLMT_S \ - 0 -#define USB_TXINTERVAL7_TXPOLL_S \ - 0 +#define USB_TXINTERVAL7_TXPOLL_M 0x00FF // TX Polling +#define USB_TXINTERVAL7_NAKLMT_M 0x00FF // NAK Limit +#define USB_TXINTERVAL7_NAKLMT_S 0 +#define USB_TXINTERVAL7_TXPOLL_S 0 //***************************************************************************** // // The following are defines for the bit fields in the USB_O_RXTYPE7 register. // //***************************************************************************** -#define USB_RXTYPE7_SPEED_M 0x000000C0 // Operating Speed -#define USB_RXTYPE7_SPEED_DFLT 0x00000000 // Default -#define USB_RXTYPE7_SPEED_HIGH 0x00000040 // High -#define USB_RXTYPE7_SPEED_FULL 0x00000080 // Full -#define USB_RXTYPE7_SPEED_LOW 0x000000C0 // Low -#define USB_RXTYPE7_PROTO_M 0x00000030 // Protocol -#define USB_RXTYPE7_PROTO_CTRL 0x00000000 // Control -#define USB_RXTYPE7_PROTO_ISOC 0x00000010 // Isochronous -#define USB_RXTYPE7_PROTO_BULK 0x00000020 // Bulk -#define USB_RXTYPE7_PROTO_INT 0x00000030 // Interrupt -#define USB_RXTYPE7_TEP_M 0x0000000F // Target Endpoint Number +#define USB_RXTYPE7_SPEED_M 0x00C0 // Operating Speed +#define USB_RXTYPE7_SPEED_DFLT 0x0000 // Default +#define USB_RXTYPE7_SPEED_HIGH 0x0040 // High +#define USB_RXTYPE7_SPEED_FULL 0x0080 // Full +#define USB_RXTYPE7_SPEED_LOW 0x00C0 // Low +#define USB_RXTYPE7_PROTO_M 0x0030 // Protocol +#define USB_RXTYPE7_PROTO_CTRL 0x0000 // Control +#define USB_RXTYPE7_PROTO_ISOC 0x0010 // Isochronous +#define USB_RXTYPE7_PROTO_BULK 0x0020 // Bulk +#define USB_RXTYPE7_PROTO_INT 0x0030 // Interrupt +#define USB_RXTYPE7_TEP_M 0x000F // Target Endpoint Number #define USB_RXTYPE7_TEP_S 0 //***************************************************************************** @@ -2097,47 +1608,43 @@ TU_ATTR_ALWAYS_INLINE static inline musb_ep_csr_t* get_ep_csr(musb_regs_t* musb_ // register. // //***************************************************************************** -#define USB_RXINTERVAL7_TXPOLL_M \ - 0x000000FF // RX Polling -#define USB_RXINTERVAL7_NAKLMT_M \ - 0x000000FF // NAK Limit -#define USB_RXINTERVAL7_NAKLMT_S \ - 0 -#define USB_RXINTERVAL7_TXPOLL_S \ - 0 +#define USB_RXINTERVAL7_TXPOLL_M 0x00FF // RX Polling +#define USB_RXINTERVAL7_NAKLMT_M 0x00FF // NAK Limit +#define USB_RXINTERVAL7_NAKLMT_S 0 +#define USB_RXINTERVAL7_TXPOLL_S 0 //***************************************************************************** // // The following are defines for the bit fields in the USB_O_DMAINTR register. // //***************************************************************************** -#define USB_DMAINTR_CH7 0x00000080 // Channel 7 DMA Interrupt -#define USB_DMAINTR_CH6 0x00000040 // Channel 6 DMA Interrupt -#define USB_DMAINTR_CH5 0x00000020 // Channel 5 DMA Interrupt -#define USB_DMAINTR_CH4 0x00000010 // Channel 4 DMA Interrupt -#define USB_DMAINTR_CH3 0x00000008 // Channel 3 DMA Interrupt -#define USB_DMAINTR_CH2 0x00000004 // Channel 2 DMA Interrupt -#define USB_DMAINTR_CH1 0x00000002 // Channel 1 DMA Interrupt -#define USB_DMAINTR_CH0 0x00000001 // Channel 0 DMA Interrupt +#define USB_DMAINTR_CH7 0x0080 // Channel 7 DMA Interrupt +#define USB_DMAINTR_CH6 0x0040 // Channel 6 DMA Interrupt +#define USB_DMAINTR_CH5 0x0020 // Channel 5 DMA Interrupt +#define USB_DMAINTR_CH4 0x0010 // Channel 4 DMA Interrupt +#define USB_DMAINTR_CH3 0x0008 // Channel 3 DMA Interrupt +#define USB_DMAINTR_CH2 0x0004 // Channel 2 DMA Interrupt +#define USB_DMAINTR_CH1 0x0002 // Channel 1 DMA Interrupt +#define USB_DMAINTR_CH0 0x0001 // Channel 0 DMA Interrupt //***************************************************************************** // // The following are defines for the bit fields in the USB_O_DMACTL0 register. // //***************************************************************************** -#define USB_DMACTL0_BRSTM_M 0x00000600 // Burst Mode -#define USB_DMACTL0_BRSTM_ANY 0x00000000 // Bursts of unspecified length -#define USB_DMACTL0_BRSTM_INC4 0x00000200 // INCR4 or unspecified length -#define USB_DMACTL0_BRSTM_INC8 0x00000400 // INCR8, INCR4 or unspecified +#define USB_DMACTL0_BRSTM_M 0x0600 // Burst Mode +#define USB_DMACTL0_BRSTM_ANY 0x0000 // Bursts of unspecified length +#define USB_DMACTL0_BRSTM_INC4 0x0200 // INCR4 or unspecified length +#define USB_DMACTL0_BRSTM_INC8 0x0400 // INCR8, INCR4 or unspecified // length -#define USB_DMACTL0_BRSTM_INC16 0x00000600 // INCR16, INCR8, INCR4 or +#define USB_DMACTL0_BRSTM_INC16 0x0600 // INCR16, INCR8, INCR4 or // unspecified length -#define USB_DMACTL0_ERR 0x00000100 // Bus Error Bit -#define USB_DMACTL0_EP_M 0x000000F0 // Endpoint number -#define USB_DMACTL0_IE 0x00000008 // DMA Interrupt Enable -#define USB_DMACTL0_MODE 0x00000004 // DMA Transfer Mode -#define USB_DMACTL0_DIR 0x00000002 // DMA Direction -#define USB_DMACTL0_ENABLE 0x00000001 // DMA Transfer Enable +#define USB_DMACTL0_ERR 0x0100 // Bus Error Bit +#define USB_DMACTL0_EP_M 0x00F0 // Endpoint number +#define USB_DMACTL0_IE 0x0008 // DMA Interrupt Enable +#define USB_DMACTL0_MODE 0x0004 // DMA Transfer Mode +#define USB_DMACTL0_DIR 0x0002 // DMA Direction +#define USB_DMACTL0_ENABLE 0x0001 // DMA Transfer Enable #define USB_DMACTL0_EP_S 4 //***************************************************************************** @@ -2162,19 +1669,19 @@ TU_ATTR_ALWAYS_INLINE static inline musb_ep_csr_t* get_ep_csr(musb_regs_t* musb_ // The following are defines for the bit fields in the USB_O_DMACTL1 register. // //***************************************************************************** -#define USB_DMACTL1_BRSTM_M 0x00000600 // Burst Mode -#define USB_DMACTL1_BRSTM_ANY 0x00000000 // Bursts of unspecified length -#define USB_DMACTL1_BRSTM_INC4 0x00000200 // INCR4 or unspecified length -#define USB_DMACTL1_BRSTM_INC8 0x00000400 // INCR8, INCR4 or unspecified +#define USB_DMACTL1_BRSTM_M 0x0600 // Burst Mode +#define USB_DMACTL1_BRSTM_ANY 0x0000 // Bursts of unspecified length +#define USB_DMACTL1_BRSTM_INC4 0x0200 // INCR4 or unspecified length +#define USB_DMACTL1_BRSTM_INC8 0x0400 // INCR8, INCR4 or unspecified // length -#define USB_DMACTL1_BRSTM_INC16 0x00000600 // INCR16, INCR8, INCR4 or +#define USB_DMACTL1_BRSTM_INC16 0x0600 // INCR16, INCR8, INCR4 or // unspecified length -#define USB_DMACTL1_ERR 0x00000100 // Bus Error Bit -#define USB_DMACTL1_EP_M 0x000000F0 // Endpoint number -#define USB_DMACTL1_IE 0x00000008 // DMA Interrupt Enable -#define USB_DMACTL1_MODE 0x00000004 // DMA Transfer Mode -#define USB_DMACTL1_DIR 0x00000002 // DMA Direction -#define USB_DMACTL1_ENABLE 0x00000001 // DMA Transfer Enable +#define USB_DMACTL1_ERR 0x0100 // Bus Error Bit +#define USB_DMACTL1_EP_M 0x00F0 // Endpoint number +#define USB_DMACTL1_IE 0x0008 // DMA Interrupt Enable +#define USB_DMACTL1_MODE 0x0004 // DMA Transfer Mode +#define USB_DMACTL1_DIR 0x0002 // DMA Direction +#define USB_DMACTL1_ENABLE 0x0001 // DMA Transfer Enable #define USB_DMACTL1_EP_S 4 //***************************************************************************** @@ -2199,19 +1706,19 @@ TU_ATTR_ALWAYS_INLINE static inline musb_ep_csr_t* get_ep_csr(musb_regs_t* musb_ // The following are defines for the bit fields in the USB_O_DMACTL2 register. // //***************************************************************************** -#define USB_DMACTL2_BRSTM_M 0x00000600 // Burst Mode -#define USB_DMACTL2_BRSTM_ANY 0x00000000 // Bursts of unspecified length -#define USB_DMACTL2_BRSTM_INC4 0x00000200 // INCR4 or unspecified length -#define USB_DMACTL2_BRSTM_INC8 0x00000400 // INCR8, INCR4 or unspecified +#define USB_DMACTL2_BRSTM_M 0x0600 // Burst Mode +#define USB_DMACTL2_BRSTM_ANY 0x0000 // Bursts of unspecified length +#define USB_DMACTL2_BRSTM_INC4 0x0200 // INCR4 or unspecified length +#define USB_DMACTL2_BRSTM_INC8 0x0400 // INCR8, INCR4 or unspecified // length -#define USB_DMACTL2_BRSTM_INC16 0x00000600 // INCR16, INCR8, INCR4 or +#define USB_DMACTL2_BRSTM_INC16 0x0600 // INCR16, INCR8, INCR4 or // unspecified length -#define USB_DMACTL2_ERR 0x00000100 // Bus Error Bit -#define USB_DMACTL2_EP_M 0x000000F0 // Endpoint number -#define USB_DMACTL2_IE 0x00000008 // DMA Interrupt Enable -#define USB_DMACTL2_MODE 0x00000004 // DMA Transfer Mode -#define USB_DMACTL2_DIR 0x00000002 // DMA Direction -#define USB_DMACTL2_ENABLE 0x00000001 // DMA Transfer Enable +#define USB_DMACTL2_ERR 0x0100 // Bus Error Bit +#define USB_DMACTL2_EP_M 0x00F0 // Endpoint number +#define USB_DMACTL2_IE 0x0008 // DMA Interrupt Enable +#define USB_DMACTL2_MODE 0x0004 // DMA Transfer Mode +#define USB_DMACTL2_DIR 0x0002 // DMA Direction +#define USB_DMACTL2_ENABLE 0x0001 // DMA Transfer Enable #define USB_DMACTL2_EP_S 4 //***************************************************************************** @@ -2236,19 +1743,19 @@ TU_ATTR_ALWAYS_INLINE static inline musb_ep_csr_t* get_ep_csr(musb_regs_t* musb_ // The following are defines for the bit fields in the USB_O_DMACTL3 register. // //***************************************************************************** -#define USB_DMACTL3_BRSTM_M 0x00000600 // Burst Mode -#define USB_DMACTL3_BRSTM_ANY 0x00000000 // Bursts of unspecified length -#define USB_DMACTL3_BRSTM_INC4 0x00000200 // INCR4 or unspecified length -#define USB_DMACTL3_BRSTM_INC8 0x00000400 // INCR8, INCR4 or unspecified +#define USB_DMACTL3_BRSTM_M 0x0600 // Burst Mode +#define USB_DMACTL3_BRSTM_ANY 0x0000 // Bursts of unspecified length +#define USB_DMACTL3_BRSTM_INC4 0x0200 // INCR4 or unspecified length +#define USB_DMACTL3_BRSTM_INC8 0x0400 // INCR8, INCR4 or unspecified // length -#define USB_DMACTL3_BRSTM_INC16 0x00000600 // INCR16, INCR8, INCR4 or +#define USB_DMACTL3_BRSTM_INC16 0x0600 // INCR16, INCR8, INCR4 or // unspecified length -#define USB_DMACTL3_ERR 0x00000100 // Bus Error Bit -#define USB_DMACTL3_EP_M 0x000000F0 // Endpoint number -#define USB_DMACTL3_IE 0x00000008 // DMA Interrupt Enable -#define USB_DMACTL3_MODE 0x00000004 // DMA Transfer Mode -#define USB_DMACTL3_DIR 0x00000002 // DMA Direction -#define USB_DMACTL3_ENABLE 0x00000001 // DMA Transfer Enable +#define USB_DMACTL3_ERR 0x0100 // Bus Error Bit +#define USB_DMACTL3_EP_M 0x00F0 // Endpoint number +#define USB_DMACTL3_IE 0x0008 // DMA Interrupt Enable +#define USB_DMACTL3_MODE 0x0004 // DMA Transfer Mode +#define USB_DMACTL3_DIR 0x0002 // DMA Direction +#define USB_DMACTL3_ENABLE 0x0001 // DMA Transfer Enable #define USB_DMACTL3_EP_S 4 //***************************************************************************** @@ -2273,19 +1780,19 @@ TU_ATTR_ALWAYS_INLINE static inline musb_ep_csr_t* get_ep_csr(musb_regs_t* musb_ // The following are defines for the bit fields in the USB_O_DMACTL4 register. // //***************************************************************************** -#define USB_DMACTL4_BRSTM_M 0x00000600 // Burst Mode -#define USB_DMACTL4_BRSTM_ANY 0x00000000 // Bursts of unspecified length -#define USB_DMACTL4_BRSTM_INC4 0x00000200 // INCR4 or unspecified length -#define USB_DMACTL4_BRSTM_INC8 0x00000400 // INCR8, INCR4 or unspecified +#define USB_DMACTL4_BRSTM_M 0x0600 // Burst Mode +#define USB_DMACTL4_BRSTM_ANY 0x0000 // Bursts of unspecified length +#define USB_DMACTL4_BRSTM_INC4 0x0200 // INCR4 or unspecified length +#define USB_DMACTL4_BRSTM_INC8 0x0400 // INCR8, INCR4 or unspecified // length -#define USB_DMACTL4_BRSTM_INC16 0x00000600 // INCR16, INCR8, INCR4 or +#define USB_DMACTL4_BRSTM_INC16 0x0600 // INCR16, INCR8, INCR4 or // unspecified length -#define USB_DMACTL4_ERR 0x00000100 // Bus Error Bit -#define USB_DMACTL4_EP_M 0x000000F0 // Endpoint number -#define USB_DMACTL4_IE 0x00000008 // DMA Interrupt Enable -#define USB_DMACTL4_MODE 0x00000004 // DMA Transfer Mode -#define USB_DMACTL4_DIR 0x00000002 // DMA Direction -#define USB_DMACTL4_ENABLE 0x00000001 // DMA Transfer Enable +#define USB_DMACTL4_ERR 0x0100 // Bus Error Bit +#define USB_DMACTL4_EP_M 0x00F0 // Endpoint number +#define USB_DMACTL4_IE 0x0008 // DMA Interrupt Enable +#define USB_DMACTL4_MODE 0x0004 // DMA Transfer Mode +#define USB_DMACTL4_DIR 0x0002 // DMA Direction +#define USB_DMACTL4_ENABLE 0x0001 // DMA Transfer Enable #define USB_DMACTL4_EP_S 4 //***************************************************************************** @@ -2310,19 +1817,19 @@ TU_ATTR_ALWAYS_INLINE static inline musb_ep_csr_t* get_ep_csr(musb_regs_t* musb_ // The following are defines for the bit fields in the USB_O_DMACTL5 register. // //***************************************************************************** -#define USB_DMACTL5_BRSTM_M 0x00000600 // Burst Mode -#define USB_DMACTL5_BRSTM_ANY 0x00000000 // Bursts of unspecified length -#define USB_DMACTL5_BRSTM_INC4 0x00000200 // INCR4 or unspecified length -#define USB_DMACTL5_BRSTM_INC8 0x00000400 // INCR8, INCR4 or unspecified +#define USB_DMACTL5_BRSTM_M 0x0600 // Burst Mode +#define USB_DMACTL5_BRSTM_ANY 0x0000 // Bursts of unspecified length +#define USB_DMACTL5_BRSTM_INC4 0x0200 // INCR4 or unspecified length +#define USB_DMACTL5_BRSTM_INC8 0x0400 // INCR8, INCR4 or unspecified // length -#define USB_DMACTL5_BRSTM_INC16 0x00000600 // INCR16, INCR8, INCR4 or +#define USB_DMACTL5_BRSTM_INC16 0x0600 // INCR16, INCR8, INCR4 or // unspecified length -#define USB_DMACTL5_ERR 0x00000100 // Bus Error Bit -#define USB_DMACTL5_EP_M 0x000000F0 // Endpoint number -#define USB_DMACTL5_IE 0x00000008 // DMA Interrupt Enable -#define USB_DMACTL5_MODE 0x00000004 // DMA Transfer Mode -#define USB_DMACTL5_DIR 0x00000002 // DMA Direction -#define USB_DMACTL5_ENABLE 0x00000001 // DMA Transfer Enable +#define USB_DMACTL5_ERR 0x0100 // Bus Error Bit +#define USB_DMACTL5_EP_M 0x00F0 // Endpoint number +#define USB_DMACTL5_IE 0x0008 // DMA Interrupt Enable +#define USB_DMACTL5_MODE 0x0004 // DMA Transfer Mode +#define USB_DMACTL5_DIR 0x0002 // DMA Direction +#define USB_DMACTL5_ENABLE 0x0001 // DMA Transfer Enable #define USB_DMACTL5_EP_S 4 //***************************************************************************** @@ -2347,19 +1854,19 @@ TU_ATTR_ALWAYS_INLINE static inline musb_ep_csr_t* get_ep_csr(musb_regs_t* musb_ // The following are defines for the bit fields in the USB_O_DMACTL6 register. // //***************************************************************************** -#define USB_DMACTL6_BRSTM_M 0x00000600 // Burst Mode -#define USB_DMACTL6_BRSTM_ANY 0x00000000 // Bursts of unspecified length -#define USB_DMACTL6_BRSTM_INC4 0x00000200 // INCR4 or unspecified length -#define USB_DMACTL6_BRSTM_INC8 0x00000400 // INCR8, INCR4 or unspecified +#define USB_DMACTL6_BRSTM_M 0x0600 // Burst Mode +#define USB_DMACTL6_BRSTM_ANY 0x0000 // Bursts of unspecified length +#define USB_DMACTL6_BRSTM_INC4 0x0200 // INCR4 or unspecified length +#define USB_DMACTL6_BRSTM_INC8 0x0400 // INCR8, INCR4 or unspecified // length -#define USB_DMACTL6_BRSTM_INC16 0x00000600 // INCR16, INCR8, INCR4 or +#define USB_DMACTL6_BRSTM_INC16 0x0600 // INCR16, INCR8, INCR4 or // unspecified length -#define USB_DMACTL6_ERR 0x00000100 // Bus Error Bit -#define USB_DMACTL6_EP_M 0x000000F0 // Endpoint number -#define USB_DMACTL6_IE 0x00000008 // DMA Interrupt Enable -#define USB_DMACTL6_MODE 0x00000004 // DMA Transfer Mode -#define USB_DMACTL6_DIR 0x00000002 // DMA Direction -#define USB_DMACTL6_ENABLE 0x00000001 // DMA Transfer Enable +#define USB_DMACTL6_ERR 0x0100 // Bus Error Bit +#define USB_DMACTL6_EP_M 0x00F0 // Endpoint number +#define USB_DMACTL6_IE 0x0008 // DMA Interrupt Enable +#define USB_DMACTL6_MODE 0x0004 // DMA Transfer Mode +#define USB_DMACTL6_DIR 0x0002 // DMA Direction +#define USB_DMACTL6_ENABLE 0x0001 // DMA Transfer Enable #define USB_DMACTL6_EP_S 4 //***************************************************************************** @@ -2384,19 +1891,19 @@ TU_ATTR_ALWAYS_INLINE static inline musb_ep_csr_t* get_ep_csr(musb_regs_t* musb_ // The following are defines for the bit fields in the USB_O_DMACTL7 register. // //***************************************************************************** -#define USB_DMACTL7_BRSTM_M 0x00000600 // Burst Mode -#define USB_DMACTL7_BRSTM_ANY 0x00000000 // Bursts of unspecified length -#define USB_DMACTL7_BRSTM_INC4 0x00000200 // INCR4 or unspecified length -#define USB_DMACTL7_BRSTM_INC8 0x00000400 // INCR8, INCR4 or unspecified +#define USB_DMACTL7_BRSTM_M 0x0600 // Burst Mode +#define USB_DMACTL7_BRSTM_ANY 0x0000 // Bursts of unspecified length +#define USB_DMACTL7_BRSTM_INC4 0x0200 // INCR4 or unspecified length +#define USB_DMACTL7_BRSTM_INC8 0x0400 // INCR8, INCR4 or unspecified // length -#define USB_DMACTL7_BRSTM_INC16 0x00000600 // INCR16, INCR8, INCR4 or +#define USB_DMACTL7_BRSTM_INC16 0x0600 // INCR16, INCR8, INCR4 or // unspecified length -#define USB_DMACTL7_ERR 0x00000100 // Bus Error Bit -#define USB_DMACTL7_EP_M 0x000000F0 // Endpoint number -#define USB_DMACTL7_IE 0x00000008 // DMA Interrupt Enable -#define USB_DMACTL7_MODE 0x00000004 // DMA Transfer Mode -#define USB_DMACTL7_DIR 0x00000002 // DMA Direction -#define USB_DMACTL7_ENABLE 0x00000001 // DMA Transfer Enable +#define USB_DMACTL7_ERR 0x0100 // Bus Error Bit +#define USB_DMACTL7_EP_M 0x00F0 // Endpoint number +#define USB_DMACTL7_IE 0x0008 // DMA Interrupt Enable +#define USB_DMACTL7_MODE 0x0004 // DMA Transfer Mode +#define USB_DMACTL7_DIR 0x0002 // DMA Direction +#define USB_DMACTL7_ENABLE 0x0001 // DMA Transfer Enable #define USB_DMACTL7_EP_S 4 //***************************************************************************** @@ -2422,7 +1929,7 @@ TU_ATTR_ALWAYS_INLINE static inline musb_ep_csr_t* get_ep_csr(musb_regs_t* musb_ // register. // //***************************************************************************** -#define USB_RQPKTCOUNT1_M 0x0000FFFF // Block Transfer Packet Count +#define USB_RQPKTCOUNT1_M 0xFFFF // Block Transfer Packet Count #define USB_RQPKTCOUNT1_S 0 //***************************************************************************** @@ -2431,7 +1938,7 @@ TU_ATTR_ALWAYS_INLINE static inline musb_ep_csr_t* get_ep_csr(musb_regs_t* musb_ // register. // //***************************************************************************** -#define USB_RQPKTCOUNT2_M 0x0000FFFF // Block Transfer Packet Count +#define USB_RQPKTCOUNT2_M 0xFFFF // Block Transfer Packet Count #define USB_RQPKTCOUNT2_S 0 //***************************************************************************** @@ -2440,7 +1947,7 @@ TU_ATTR_ALWAYS_INLINE static inline musb_ep_csr_t* get_ep_csr(musb_regs_t* musb_ // register. // //***************************************************************************** -#define USB_RQPKTCOUNT3_M 0x0000FFFF // Block Transfer Packet Count +#define USB_RQPKTCOUNT3_M 0xFFFF // Block Transfer Packet Count #define USB_RQPKTCOUNT3_S 0 //***************************************************************************** @@ -2449,7 +1956,7 @@ TU_ATTR_ALWAYS_INLINE static inline musb_ep_csr_t* get_ep_csr(musb_regs_t* musb_ // register. // //***************************************************************************** -#define USB_RQPKTCOUNT4_COUNT_M 0x0000FFFF // Block Transfer Packet Count +#define USB_RQPKTCOUNT4_COUNT_M 0xFFFF // Block Transfer Packet Count #define USB_RQPKTCOUNT4_COUNT_S 0 //***************************************************************************** @@ -2458,7 +1965,7 @@ TU_ATTR_ALWAYS_INLINE static inline musb_ep_csr_t* get_ep_csr(musb_regs_t* musb_ // register. // //***************************************************************************** -#define USB_RQPKTCOUNT5_COUNT_M 0x0000FFFF // Block Transfer Packet Count +#define USB_RQPKTCOUNT5_COUNT_M 0xFFFF // Block Transfer Packet Count #define USB_RQPKTCOUNT5_COUNT_S 0 //***************************************************************************** @@ -2467,7 +1974,7 @@ TU_ATTR_ALWAYS_INLINE static inline musb_ep_csr_t* get_ep_csr(musb_regs_t* musb_ // register. // //***************************************************************************** -#define USB_RQPKTCOUNT6_COUNT_M 0x0000FFFF // Block Transfer Packet Count +#define USB_RQPKTCOUNT6_COUNT_M 0xFFFF // Block Transfer Packet Count #define USB_RQPKTCOUNT6_COUNT_S 0 //***************************************************************************** @@ -2476,7 +1983,7 @@ TU_ATTR_ALWAYS_INLINE static inline musb_ep_csr_t* get_ep_csr(musb_regs_t* musb_ // register. // //***************************************************************************** -#define USB_RQPKTCOUNT7_COUNT_M 0x0000FFFF // Block Transfer Packet Count +#define USB_RQPKTCOUNT7_COUNT_M 0xFFFF // Block Transfer Packet Count #define USB_RQPKTCOUNT7_COUNT_S 0 //***************************************************************************** @@ -2485,19 +1992,19 @@ TU_ATTR_ALWAYS_INLINE static inline musb_ep_csr_t* get_ep_csr(musb_regs_t* musb_ // register. // //***************************************************************************** -#define USB_RXDPKTBUFDIS_EP7 0x00000080 // EP7 RX Double-Packet Buffer +#define USB_RXDPKTBUFDIS_EP7 0x0080 // EP7 RX Double-Packet Buffer // Disable -#define USB_RXDPKTBUFDIS_EP6 0x00000040 // EP6 RX Double-Packet Buffer +#define USB_RXDPKTBUFDIS_EP6 0x0040 // EP6 RX Double-Packet Buffer // Disable -#define USB_RXDPKTBUFDIS_EP5 0x00000020 // EP5 RX Double-Packet Buffer +#define USB_RXDPKTBUFDIS_EP5 0x0020 // EP5 RX Double-Packet Buffer // Disable -#define USB_RXDPKTBUFDIS_EP4 0x00000010 // EP4 RX Double-Packet Buffer +#define USB_RXDPKTBUFDIS_EP4 0x0010 // EP4 RX Double-Packet Buffer // Disable -#define USB_RXDPKTBUFDIS_EP3 0x00000008 // EP3 RX Double-Packet Buffer +#define USB_RXDPKTBUFDIS_EP3 0x0008 // EP3 RX Double-Packet Buffer // Disable -#define USB_RXDPKTBUFDIS_EP2 0x00000004 // EP2 RX Double-Packet Buffer +#define USB_RXDPKTBUFDIS_EP2 0x0004 // EP2 RX Double-Packet Buffer // Disable -#define USB_RXDPKTBUFDIS_EP1 0x00000002 // EP1 RX Double-Packet Buffer +#define USB_RXDPKTBUFDIS_EP1 0x0002 // EP1 RX Double-Packet Buffer // Disable //***************************************************************************** @@ -2506,19 +2013,19 @@ TU_ATTR_ALWAYS_INLINE static inline musb_ep_csr_t* get_ep_csr(musb_regs_t* musb_ // register. // //***************************************************************************** -#define USB_TXDPKTBUFDIS_EP7 0x00000080 // EP7 TX Double-Packet Buffer +#define USB_TXDPKTBUFDIS_EP7 0x0080 // EP7 TX Double-Packet Buffer // Disable -#define USB_TXDPKTBUFDIS_EP6 0x00000040 // EP6 TX Double-Packet Buffer +#define USB_TXDPKTBUFDIS_EP6 0x0040 // EP6 TX Double-Packet Buffer // Disable -#define USB_TXDPKTBUFDIS_EP5 0x00000020 // EP5 TX Double-Packet Buffer +#define USB_TXDPKTBUFDIS_EP5 0x0020 // EP5 TX Double-Packet Buffer // Disable -#define USB_TXDPKTBUFDIS_EP4 0x00000010 // EP4 TX Double-Packet Buffer +#define USB_TXDPKTBUFDIS_EP4 0x0010 // EP4 TX Double-Packet Buffer // Disable -#define USB_TXDPKTBUFDIS_EP3 0x00000008 // EP3 TX Double-Packet Buffer +#define USB_TXDPKTBUFDIS_EP3 0x0008 // EP3 TX Double-Packet Buffer // Disable -#define USB_TXDPKTBUFDIS_EP2 0x00000004 // EP2 TX Double-Packet Buffer +#define USB_TXDPKTBUFDIS_EP2 0x0004 // EP2 TX Double-Packet Buffer // Disable -#define USB_TXDPKTBUFDIS_EP1 0x00000002 // EP1 TX Double-Packet Buffer +#define USB_TXDPKTBUFDIS_EP1 0x0002 // EP1 TX Double-Packet Buffer // Disable //***************************************************************************** @@ -2526,7 +2033,7 @@ TU_ATTR_ALWAYS_INLINE static inline musb_ep_csr_t* get_ep_csr(musb_regs_t* musb_ // The following are defines for the bit fields in the USB_O_CTO register. // //***************************************************************************** -#define USB_CTO_CCTV_M 0x0000FFFF // Configurable Chirp Timeout Value +#define USB_CTO_CCTV_M 0xFFFF // Configurable Chirp Timeout Value #define USB_CTO_CCTV_S 0 //***************************************************************************** @@ -2534,7 +2041,7 @@ TU_ATTR_ALWAYS_INLINE static inline musb_ep_csr_t* get_ep_csr(musb_regs_t* musb_ // The following are defines for the bit fields in the USB_O_HHSRTN register. // //***************************************************************************** -#define USB_HHSRTN_HHSRTN_M 0x0000FFFF // HIgh Speed to UTM Operating +#define USB_HHSRTN_HHSRTN_M 0xFFFF // HIgh Speed to UTM Operating // Delay #define USB_HHSRTN_HHSRTN_S 0 @@ -2543,7 +2050,7 @@ TU_ATTR_ALWAYS_INLINE static inline musb_ep_csr_t* get_ep_csr(musb_regs_t* musb_ // The following are defines for the bit fields in the USB_O_HSBT register. // //***************************************************************************** -#define USB_HSBT_HSBT_M 0x0000000F // High Speed Timeout Adder +#define USB_HSBT_HSBT_M 0x000F // High Speed Timeout Adder #define USB_HSBT_HSBT_S 0 //***************************************************************************** @@ -2551,11 +2058,11 @@ TU_ATTR_ALWAYS_INLINE static inline musb_ep_csr_t* get_ep_csr(musb_regs_t* musb_ // The following are defines for the bit fields in the USB_O_LPMATTR register. // //***************************************************************************** -#define USB_LPMATTR_ENDPT_M 0x0000F000 // Endpoint -#define USB_LPMATTR_RMTWAK 0x00000100 // Remote Wake -#define USB_LPMATTR_HIRD_M 0x000000F0 // Host Initiated Resume Duration -#define USB_LPMATTR_LS_M 0x0000000F // Link State -#define USB_LPMATTR_LS_L1 0x00000001 // Sleep State (L1) +#define USB_LPMATTR_ENDPT_M 0xF000 // Endpoint +#define USB_LPMATTR_RMTWAK 0x0100 // Remote Wake +#define USB_LPMATTR_HIRD_M 0x00F0 // Host Initiated Resume Duration +#define USB_LPMATTR_LS_M 0x000F // Link State +#define USB_LPMATTR_LS_L1 0x0001 // Sleep State (L1) #define USB_LPMATTR_ENDPT_S 12 #define USB_LPMATTR_HIRD_S 4 @@ -2564,56 +2071,56 @@ TU_ATTR_ALWAYS_INLINE static inline musb_ep_csr_t* get_ep_csr(musb_regs_t* musb_ // The following are defines for the bit fields in the USB_O_LPMCNTRL register. // //***************************************************************************** -#define USB_LPMCNTRL_NAK 0x00000010 // LPM NAK -#define USB_LPMCNTRL_EN_M 0x0000000C // LPM Enable -#define USB_LPMCNTRL_EN_NONE 0x00000000 // LPM and Extended transactions +#define USB_LPMCNTRL_NAK 0x0010 // LPM NAK +#define USB_LPMCNTRL_EN_M 0x000C // LPM Enable +#define USB_LPMCNTRL_EN_NONE 0x0000 // LPM and Extended transactions // are not supported. In this case, // the USB does not respond to LPM // transactions and LPM // transactions cause a timeout -#define USB_LPMCNTRL_EN_EXT 0x00000004 // LPM is not supported but +#define USB_LPMCNTRL_EN_EXT 0x0004 // LPM is not supported but // extended transactions are // supported. In this case, the USB // does respond to an LPM // transaction with a STALL -#define USB_LPMCNTRL_EN_LPMEXT 0x0000000C // The USB supports LPM extended +#define USB_LPMCNTRL_EN_LPMEXT 0x000C // The USB supports LPM extended // transactions. In this case, the // USB responds with a NYET or an // ACK as determined by the value // of TXLPM and other conditions -#define USB_LPMCNTRL_RES 0x00000002 // LPM Resume -#define USB_LPMCNTRL_TXLPM 0x00000001 // Transmit LPM Transaction Enable +#define USB_LPMCNTRL_RES 0x0002 // LPM Resume +#define USB_LPMCNTRL_TXLPM 0x0001 // Transmit LPM Transaction Enable //***************************************************************************** // // The following are defines for the bit fields in the USB_O_LPMIM register. // //***************************************************************************** -#define USB_LPMIM_ERR 0x00000020 // LPM Error Interrupt Mask -#define USB_LPMIM_RES 0x00000010 // LPM Resume Interrupt Mask -#define USB_LPMIM_NC 0x00000008 // LPM NC Interrupt Mask -#define USB_LPMIM_ACK 0x00000004 // LPM ACK Interrupt Mask -#define USB_LPMIM_NY 0x00000002 // LPM NY Interrupt Mask -#define USB_LPMIM_STALL 0x00000001 // LPM STALL Interrupt Mask +#define USB_LPMIM_ERR 0x0020 // LPM Error Interrupt Mask +#define USB_LPMIM_RES 0x0010 // LPM Resume Interrupt Mask +#define USB_LPMIM_NC 0x0008 // LPM NC Interrupt Mask +#define USB_LPMIM_ACK 0x0004 // LPM ACK Interrupt Mask +#define USB_LPMIM_NY 0x0002 // LPM NY Interrupt Mask +#define USB_LPMIM_STALL 0x0001 // LPM STALL Interrupt Mask //***************************************************************************** // // The following are defines for the bit fields in the USB_O_LPMRIS register. // //***************************************************************************** -#define USB_LPMRIS_ERR 0x00000020 // LPM Interrupt Status -#define USB_LPMRIS_RES 0x00000010 // LPM Resume Interrupt Status -#define USB_LPMRIS_NC 0x00000008 // LPM NC Interrupt Status -#define USB_LPMRIS_ACK 0x00000004 // LPM ACK Interrupt Status -#define USB_LPMRIS_NY 0x00000002 // LPM NY Interrupt Status -#define USB_LPMRIS_LPMST 0x00000001 // LPM STALL Interrupt Status +#define USB_LPMRIS_ERR 0x0020 // LPM Interrupt Status +#define USB_LPMRIS_RES 0x0010 // LPM Resume Interrupt Status +#define USB_LPMRIS_NC 0x0008 // LPM NC Interrupt Status +#define USB_LPMRIS_ACK 0x0004 // LPM ACK Interrupt Status +#define USB_LPMRIS_NY 0x0002 // LPM NY Interrupt Status +#define USB_LPMRIS_LPMST 0x0001 // LPM STALL Interrupt Status //***************************************************************************** // // The following are defines for the bit fields in the USB_O_LPMFADDR register. // //***************************************************************************** -#define USB_LPMFADDR_ADDR_M 0x0000007F // LPM Function Address +#define USB_LPMFADDR_ADDR_M 0x007F // LPM Function Address #define USB_LPMFADDR_ADDR_S 0 //***************************************************************************** @@ -2621,22 +2128,22 @@ TU_ATTR_ALWAYS_INLINE static inline musb_ep_csr_t* get_ep_csr(musb_regs_t* musb_ // The following are defines for the bit fields in the USB_O_EPC register. // //***************************************************************************** -#define USB_EPC_PFLTACT_M 0x00000300 // Power Fault Action -#define USB_EPC_PFLTACT_UNCHG 0x00000000 // Unchanged -#define USB_EPC_PFLTACT_TRIS 0x00000100 // Tristate -#define USB_EPC_PFLTACT_LOW 0x00000200 // Low -#define USB_EPC_PFLTACT_HIGH 0x00000300 // High -#define USB_EPC_PFLTAEN 0x00000040 // Power Fault Action Enable -#define USB_EPC_PFLTSEN_HIGH 0x00000020 // Power Fault Sense -#define USB_EPC_PFLTEN 0x00000010 // Power Fault Input Enable -#define USB_EPC_EPENDE 0x00000004 // EPEN Drive Enable -#define USB_EPC_EPEN_M 0x00000003 // External Power Supply Enable +#define USB_EPC_PFLTACT_M 0x0300 // Power Fault Action +#define USB_EPC_PFLTACT_UNCHG 0x0000 // Unchanged +#define USB_EPC_PFLTACT_TRIS 0x0100 // Tristate +#define USB_EPC_PFLTACT_LOW 0x0200 // Low +#define USB_EPC_PFLTACT_HIGH 0x0300 // High +#define USB_EPC_PFLTAEN 0x0040 // Power Fault Action Enable +#define USB_EPC_PFLTSEN_HIGH 0x0020 // Power Fault Sense +#define USB_EPC_PFLTEN 0x0010 // Power Fault Input Enable +#define USB_EPC_EPENDE 0x0004 // EPEN Drive Enable +#define USB_EPC_EPEN_M 0x0003 // External Power Supply Enable // Configuration -#define USB_EPC_EPEN_LOW 0x00000000 // Power Enable Active Low -#define USB_EPC_EPEN_HIGH 0x00000001 // Power Enable Active High -#define USB_EPC_EPEN_VBLOW 0x00000002 // Power Enable High if VBUS Low +#define USB_EPC_EPEN_LOW 0x0000 // Power Enable Active Low +#define USB_EPC_EPEN_HIGH 0x0001 // Power Enable Active High +#define USB_EPC_EPEN_VBLOW 0x0002 // Power Enable High if VBUS Low // (OTG only) -#define USB_EPC_EPEN_VBHIGH 0x00000003 // Power Enable High if VBUS High +#define USB_EPC_EPEN_VBHIGH 0x0003 // Power Enable High if VBUS High // (OTG only) //***************************************************************************** @@ -2644,21 +2151,21 @@ TU_ATTR_ALWAYS_INLINE static inline musb_ep_csr_t* get_ep_csr(musb_regs_t* musb_ // The following are defines for the bit fields in the USB_O_EPCRIS register. // //***************************************************************************** -#define USB_EPCRIS_PF 0x00000001 // USB Power Fault Interrupt Status +#define USB_EPCRIS_PF 0x0001 // USB Power Fault Interrupt Status //***************************************************************************** // // The following are defines for the bit fields in the USB_O_EPCIM register. // //***************************************************************************** -#define USB_EPCIM_PF 0x00000001 // USB Power Fault Interrupt Mask +#define USB_EPCIM_PF 0x0001 // USB Power Fault Interrupt Mask //***************************************************************************** // // The following are defines for the bit fields in the USB_O_EPCISC register. // //***************************************************************************** -#define USB_EPCISC_PF 0x00000001 // USB Power Fault Interrupt Status +#define USB_EPCISC_PF 0x0001 // USB Power Fault Interrupt Status // and Clear //***************************************************************************** @@ -2666,21 +2173,21 @@ TU_ATTR_ALWAYS_INLINE static inline musb_ep_csr_t* get_ep_csr(musb_regs_t* musb_ // The following are defines for the bit fields in the USB_O_DRRIS register. // //***************************************************************************** -#define USB_DRRIS_RESUME 0x00000001 // RESUME Interrupt Status +#define USB_DRRIS_RESUME 0x0001 // RESUME Interrupt Status //***************************************************************************** // // The following are defines for the bit fields in the USB_O_DRIM register. // //***************************************************************************** -#define USB_DRIM_RESUME 0x00000001 // RESUME Interrupt Mask +#define USB_DRIM_RESUME 0x0001 // RESUME Interrupt Mask //***************************************************************************** // // The following are defines for the bit fields in the USB_O_DRISC register. // //***************************************************************************** -#define USB_DRISC_RESUME 0x00000001 // RESUME Interrupt Status and +#define USB_DRISC_RESUME 0x0001 // RESUME Interrupt Status and // Clear //***************************************************************************** @@ -2688,14 +2195,14 @@ TU_ATTR_ALWAYS_INLINE static inline musb_ep_csr_t* get_ep_csr(musb_regs_t* musb_ // The following are defines for the bit fields in the USB_O_GPCS register. // //***************************************************************************** -#define USB_GPCS_DEVMOD_M 0x00000007 // Device Mode -#define USB_GPCS_DEVMOD_OTG 0x00000000 // Use USB0VBUS and USB0ID pin -#define USB_GPCS_DEVMOD_HOST 0x00000002 // Force USB0VBUS and USB0ID low -#define USB_GPCS_DEVMOD_DEV 0x00000003 // Force USB0VBUS and USB0ID high +#define USB_GPCS_DEVMOD_M 0x0007 // Device Mode +#define USB_GPCS_DEVMOD_OTG 0x0000 // Use USB0VBUS and USB0ID pin +#define USB_GPCS_DEVMOD_HOST 0x0002 // Force USB0VBUS and USB0ID low +#define USB_GPCS_DEVMOD_DEV 0x0003 // Force USB0VBUS and USB0ID high #define USB_GPCS_DEVMOD_HOSTVBUS \ - 0x00000004 // Use USB0VBUS and force USB0ID + 0x0004 // Use USB0VBUS and force USB0ID // low -#define USB_GPCS_DEVMOD_DEVVBUS 0x00000005 // Use USB0VBUS and force USB0ID +#define USB_GPCS_DEVMOD_DEVVBUS 0x0005 // Use USB0VBUS and force USB0ID // high //***************************************************************************** @@ -2703,28 +2210,28 @@ TU_ATTR_ALWAYS_INLINE static inline musb_ep_csr_t* get_ep_csr(musb_regs_t* musb_ // The following are defines for the bit fields in the USB_O_VDC register. // //***************************************************************************** -#define USB_VDC_VBDEN 0x00000001 // VBUS Droop Enable +#define USB_VDC_VBDEN 0x0001 // VBUS Droop Enable //***************************************************************************** // // The following are defines for the bit fields in the USB_O_VDCRIS register. // //***************************************************************************** -#define USB_VDCRIS_VD 0x00000001 // VBUS Droop Raw Interrupt Status +#define USB_VDCRIS_VD 0x0001 // VBUS Droop Raw Interrupt Status //***************************************************************************** // // The following are defines for the bit fields in the USB_O_VDCIM register. // //***************************************************************************** -#define USB_VDCIM_VD 0x00000001 // VBUS Droop Interrupt Mask +#define USB_VDCIM_VD 0x0001 // VBUS Droop Interrupt Mask //***************************************************************************** // // The following are defines for the bit fields in the USB_O_VDCISC register. // //***************************************************************************** -#define USB_VDCISC_VD 0x00000001 // VBUS Droop Interrupt Status and +#define USB_VDCISC_VD 0x0001 // VBUS Droop Interrupt Status and // Clear //***************************************************************************** @@ -2732,17 +2239,17 @@ TU_ATTR_ALWAYS_INLINE static inline musb_ep_csr_t* get_ep_csr(musb_regs_t* musb_ // The following are defines for the bit fields in the USB_O_PP register. // //***************************************************************************** -#define USB_PP_ECNT_M 0x0000FF00 // Endpoint Count -#define USB_PP_USB_M 0x000000C0 // USB Capability -#define USB_PP_USB_DEVICE 0x00000040 // DEVICE -#define USB_PP_USB_HOSTDEVICE 0x00000080 // HOST -#define USB_PP_USB_OTG 0x000000C0 // OTG -#define USB_PP_ULPI 0x00000020 // ULPI Present -#define USB_PP_PHY 0x00000010 // PHY Present -#define USB_PP_TYPE_M 0x0000000F // Controller Type -#define USB_PP_TYPE_0 0x00000000 // The first-generation USB +#define USB_PP_ECNT_M 0xFF00 // Endpoint Count +#define USB_PP_USB_M 0x00C0 // USB Capability +#define USB_PP_USB_DEVICE 0x0040 // DEVICE +#define USB_PP_USB_HOSTDEVICE 0x0080 // HOST +#define USB_PP_USB_OTG 0x00C0 // OTG +#define USB_PP_ULPI 0x0020 // ULPI Present +#define USB_PP_PHY 0x0010 // PHY Present +#define USB_PP_TYPE_M 0x000F // Controller Type +#define USB_PP_TYPE_0 0x0000 // The first-generation USB // controller -#define USB_PP_TYPE_1 0x00000001 // The second-generation USB +#define USB_PP_TYPE_1 0x0001 // The second-generation USB // controller revision #define USB_PP_ECNT_S 8 @@ -2758,9 +2265,9 @@ TU_ATTR_ALWAYS_INLINE static inline musb_ep_csr_t* get_ep_csr(musb_regs_t* musb_ // The following are defines for the bit fields in the USB_O_CC register. // //***************************************************************************** -#define USB_CC_CLKEN 0x00000200 // USB Clock Enable -#define USB_CC_CSD 0x00000100 // Clock Source/Direction -#define USB_CC_CLKDIV_M 0x0000000F // PLL Clock Divisor +#define USB_CC_CLKEN 0x0200 // USB Clock Enable +#define USB_CC_CSD 0x0100 // Clock Source/Direction +#define USB_CC_CLKDIV_M 0x000F // PLL Clock Divisor #define USB_CC_CLKDIV_S 0 #ifdef __cplusplus