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rename to ep_read/write(), drop USBx argument

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hathach
2024-07-31 16:53:16 +07:00
parent 3156f1c4a7
commit ee831d27ac
2 changed files with 54 additions and 56 deletions
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34
src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c
View File

@@ -227,7 +227,7 @@ void dcd_init(uint8_t rhport) {
// Reset endpoints to disabled // Reset endpoints to disabled
for (uint32_t i = 0; i < FSDEV_EP_COUNT; i++) { for (uint32_t i = 0; i < FSDEV_EP_COUNT; i++) {
// This doesn't clear all bits since some bits are "toggle", but does set the type to DISABLED. // This doesn't clear all bits since some bits are "toggle", but does set the type to DISABLED.
pcd_set_endpoint(USB, i, 0u); ep_write(i, 0u);
} }
USB->CNTR |= USB_CNTR_RESETM | USB_CNTR_ESOFM | USB_CNTR_CTRM | USB_CNTR_SUSPM | USB_CNTR_WKUPM; USB->CNTR |= USB_CNTR_RESETM | USB_CNTR_ESOFM | USB_CNTR_CTRM | USB_CNTR_SUSPM | USB_CNTR_WKUPM;
@@ -286,7 +286,7 @@ static void handle_bus_reset(uint8_t rhport) {
// Handle CTR interrupt for the TX/IN direction // Handle CTR interrupt for the TX/IN direction
static void dcd_ep_ctr_tx_handler(uint32_t ep_id) { static void dcd_ep_ctr_tx_handler(uint32_t ep_id) {
uint32_t ep_reg = pcd_get_endpoint(USB, ep_id) & USB_EPREG_MASK; uint32_t ep_reg = ep_read(ep_id) & USB_EPREG_MASK;
// Verify the CTR bit is set. This was in the ST Micro code, but I'm not sure it's actually necessary? // Verify the CTR bit is set. This was in the ST Micro code, but I'm not sure it's actually necessary?
TU_VERIFY(ep_reg & USB_EP_CTR_TX, ); TU_VERIFY(ep_reg & USB_EP_CTR_TX, );
@@ -314,7 +314,7 @@ static void dcd_ep_ctr_tx_handler(uint32_t ep_id) {
// Clear CTR TX and reserved CTR RX // Clear CTR TX and reserved CTR RX
ep_reg = (ep_reg & ~USB_EP_CTR_TX) | USB_EP_CTR_RX; ep_reg = (ep_reg & ~USB_EP_CTR_TX) | USB_EP_CTR_RX;
pcd_set_endpoint(USB, ep_id, ep_reg); ep_write(ep_id, ep_reg);
} }
} }
@@ -341,7 +341,7 @@ static void dcd_ep_ctr_rx_handler(uint32_t ep_id) {
} }
#endif #endif
uint32_t ep_reg = pcd_get_endpoint(USB, ep_id); uint32_t ep_reg = ep_read(ep_id);
// Verify the CTR bit is set. This was in the ST Micro code, but I'm not sure it's actually necessary? // Verify the CTR bit is set. This was in the ST Micro code, but I'm not sure it's actually necessary?
TU_VERIFY(ep_reg & USB_EP_CTR_RX, ); TU_VERIFY(ep_reg & USB_EP_CTR_RX, );
@@ -413,7 +413,7 @@ static void dcd_ep_ctr_rx_handler(uint32_t ep_id) {
} }
} }
pcd_set_endpoint(USB, ep_id, ep_reg); ep_write(ep_id, ep_reg);
} }
static void dcd_ep_ctr_handler(void) { static void dcd_ep_ctr_handler(void) {
@@ -599,7 +599,7 @@ void edpt0_open(uint8_t rhport) {
// prepare for setup packet // prepare for setup packet
btable_set_rx_bufsize(0, BTABLE_BUF_RX, CFG_TUD_ENDPOINT0_SIZE); btable_set_rx_bufsize(0, BTABLE_BUF_RX, CFG_TUD_ENDPOINT0_SIZE);
pcd_set_endpoint(USB, 0, ep_reg); ep_write(0, ep_reg);
} }
bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const *desc_ep) { bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const *desc_ep) {
@@ -644,7 +644,7 @@ bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const *desc_ep) {
ep_reg &= ~(USB_EPTX_STAT | USB_EP_DTOG_TX); ep_reg &= ~(USB_EPTX_STAT | USB_EP_DTOG_TX);
} }
pcd_set_endpoint(USB, ep_idx, ep_reg); ep_write(ep_idx, ep_reg);
return true; return true;
} }
@@ -655,7 +655,7 @@ void dcd_edpt_close_all(uint8_t rhport)
for (uint32_t i = 1; i < FSDEV_EP_COUNT; i++) { for (uint32_t i = 1; i < FSDEV_EP_COUNT; i++) {
// Reset endpoint // Reset endpoint
pcd_set_endpoint(USB, i, 0); ep_write(i, 0);
// Clear EP allocation status // Clear EP allocation status
ep_alloc_status[i].ep_num = 0xFF; ep_alloc_status[i].ep_num = 0xFF;
ep_alloc_status[i].ep_type = 0xFF; ep_alloc_status[i].ep_type = 0xFF;
@@ -703,7 +703,7 @@ bool dcd_edpt_iso_activate(uint8_t rhport, tusb_desc_endpoint_t const *desc_ep)
ep_reg = ep_add_dtog(ep_reg, dir, 0); ep_reg = ep_add_dtog(ep_reg, dir, 0);
ep_reg = ep_add_dtog(ep_reg, 1-dir, 1); ep_reg = ep_add_dtog(ep_reg, 1-dir, 1);
pcd_set_endpoint(USB, ep_idx, ep_reg); ep_write(ep_idx, ep_reg);
return true; return true;
} }
@@ -711,7 +711,7 @@ bool dcd_edpt_iso_activate(uint8_t rhport, tusb_desc_endpoint_t const *desc_ep)
// Currently, single-buffered, and only 64 bytes at a time (max) // Currently, single-buffered, and only 64 bytes at a time (max)
static void dcd_transmit_packet(xfer_ctl_t *xfer, uint16_t ep_ix) { static void dcd_transmit_packet(xfer_ctl_t *xfer, uint16_t ep_ix) {
uint16_t len = tu_min16(xfer->total_len - xfer->queued_len, xfer->max_packet_size); uint16_t len = tu_min16(xfer->total_len - xfer->queued_len, xfer->max_packet_size);
uint16_t ep_reg = pcd_get_endpoint(USB, ep_ix) | EP_CTR_TXRX; uint16_t ep_reg = ep_read(ep_ix) | EP_CTR_TXRX;
bool const is_iso = ep_is_iso(ep_reg); bool const is_iso = ep_is_iso(ep_reg);
uint8_t buf_id; uint8_t buf_id;
@@ -735,7 +735,7 @@ static void dcd_transmit_packet(xfer_ctl_t *xfer, uint16_t ep_ix) {
ep_reg = ep_clear_ctr(ep_reg, TUSB_DIR_IN); ep_reg = ep_clear_ctr(ep_reg, TUSB_DIR_IN);
dcd_int_disable(0); dcd_int_disable(0);
pcd_set_endpoint(USB, ep_ix, ep_reg); ep_write(ep_ix, ep_reg);
if (is_iso) { if (is_iso) {
xfer->iso_in_sending = true; xfer->iso_in_sending = true;
} }
@@ -753,7 +753,7 @@ static bool edpt_xfer(uint8_t rhport, uint8_t ep_addr) {
dcd_transmit_packet(xfer, ep_idx); dcd_transmit_packet(xfer, ep_idx);
} else { } else {
uint32_t cnt = (uint32_t) tu_min16(xfer->total_len, xfer->max_packet_size); uint32_t cnt = (uint32_t) tu_min16(xfer->total_len, xfer->max_packet_size);
uint16_t ep_reg = pcd_get_endpoint(USB, ep_idx) | USB_EP_CTR_TX; uint16_t ep_reg = ep_read(ep_idx) | USB_EP_CTR_TX;
ep_reg &= USB_EPREG_MASK | EP_STAT_MASK(dir); // keep CTR TX, clear CTR RX ep_reg &= USB_EPREG_MASK | EP_STAT_MASK(dir); // keep CTR TX, clear CTR RX
ep_reg = ep_add_status(ep_reg, dir, EP_STAT_VALID); ep_reg = ep_add_status(ep_reg, dir, EP_STAT_VALID);
@@ -764,7 +764,7 @@ static bool edpt_xfer(uint8_t rhport, uint8_t ep_addr) {
btable_set_rx_bufsize(ep_idx, BTABLE_BUF_RX, cnt); btable_set_rx_bufsize(ep_idx, BTABLE_BUF_RX, cnt);
} }
pcd_set_endpoint(USB, ep_idx, ep_reg); ep_write(ep_idx, ep_reg);
} }
return true; return true;
@@ -797,12 +797,12 @@ void dcd_edpt_stall(uint8_t rhport, uint8_t ep_addr) {
uint8_t const ep_idx = xfer->ep_idx; uint8_t const ep_idx = xfer->ep_idx;
uint8_t const dir = tu_edpt_dir(ep_addr); uint8_t const dir = tu_edpt_dir(ep_addr);
uint32_t ep_reg = pcd_get_endpoint(USB, ep_idx); uint32_t ep_reg = ep_read(ep_idx);
ep_reg |= USB_EP_CTR_RX | USB_EP_CTR_TX; // reserve CTR bits ep_reg |= USB_EP_CTR_RX | USB_EP_CTR_TX; // reserve CTR bits
ep_reg &= USB_EPREG_MASK | EP_STAT_MASK(dir); ep_reg &= USB_EPREG_MASK | EP_STAT_MASK(dir);
ep_reg = ep_add_status(ep_reg, dir, EP_STAT_STALL); ep_reg = ep_add_status(ep_reg, dir, EP_STAT_STALL);
pcd_set_endpoint(USB, ep_idx, ep_reg); ep_write(ep_idx, ep_reg);
} }
void dcd_edpt_clear_stall(uint8_t rhport, uint8_t ep_addr) { void dcd_edpt_clear_stall(uint8_t rhport, uint8_t ep_addr) {
@@ -811,7 +811,7 @@ void dcd_edpt_clear_stall(uint8_t rhport, uint8_t ep_addr) {
xfer_ctl_t *xfer = xfer_ctl_ptr(ep_addr); xfer_ctl_t *xfer = xfer_ctl_ptr(ep_addr);
uint8_t const ep_idx = xfer->ep_idx; uint8_t const ep_idx = xfer->ep_idx;
uint8_t const dir = tu_edpt_dir(ep_addr); uint8_t const dir = tu_edpt_dir(ep_addr);
uint32_t ep_reg = pcd_get_endpoint(USB, ep_idx); uint32_t ep_reg = ep_read(ep_idx);
ep_reg |= USB_EP_CTR_RX | USB_EP_CTR_TX; // reserve CTR bits ep_reg |= USB_EP_CTR_RX | USB_EP_CTR_TX; // reserve CTR bits
ep_reg &= USB_EPREG_MASK | EP_STAT_MASK(dir) | EP_DTOG_MASK(dir); ep_reg &= USB_EPREG_MASK | EP_STAT_MASK(dir) | EP_DTOG_MASK(dir);
@@ -820,7 +820,7 @@ void dcd_edpt_clear_stall(uint8_t rhport, uint8_t ep_addr) {
} }
ep_reg = ep_add_dtog(ep_reg, dir, 0); // Reset to DATA0 ep_reg = ep_add_dtog(ep_reg, dir, 0); // Reset to DATA0
pcd_set_endpoint(USB, ep_idx, ep_reg); ep_write(ep_idx, ep_reg);
} }
#ifdef FSDEV_BUS_32BIT #ifdef FSDEV_BUS_32BIT

76
src/portable/st/stm32_fsdev/fsdev_common.h
View File

@@ -165,6 +165,43 @@ typedef enum {
#define EP_STAT_MASK(_dir) (3u << (USB_EPTX_STAT_Pos + ((_dir) == TUSB_DIR_IN ? 0 : 8))) #define EP_STAT_MASK(_dir) (3u << (USB_EPTX_STAT_Pos + ((_dir) == TUSB_DIR_IN ? 0 : 8)))
#define EP_DTOG_MASK(_dir) (1u << (USB_EP_DTOG_TX_Pos + ((_dir) == TUSB_DIR_IN ? 0 : 8))) #define EP_DTOG_MASK(_dir) (1u << (USB_EP_DTOG_TX_Pos + ((_dir) == TUSB_DIR_IN ? 0 : 8)))
//--------------------------------------------------------------------+
// Endpoint
//--------------------------------------------------------------------+
TU_ATTR_ALWAYS_INLINE static inline void ep_write(uint32_t ep_id, uint32_t value) {
FSDEV_REG->ep[ep_id].reg = (fsdev_bus_t) value;
}
// write ep register with clear CTR_RX and CTR_TX mask (0 is no clear)
//TU_ATTR_ALWAYS_INLINE static inline void ep_write_with_clear_ctr(uint32_t ep_id, uint32_t value, uint32_t clear_ctr_mask) {
// value |= USB_EP_CTR_RX | USB_EP_CTR_TX;
// if (clear_ctr_mask) {
// value &= ~clear_ctr_mask;
// }
// FSDEV_REG->ep[ep_id].reg = (fsdev_bus_t) value;
//}
TU_ATTR_ALWAYS_INLINE static inline uint32_t ep_read(uint32_t ep_id) {
return FSDEV_REG->ep[ep_id].reg;
}
TU_ATTR_ALWAYS_INLINE static inline uint32_t ep_add_status(uint32_t reg, tusb_dir_t dir, ep_stat_t state) {
return reg ^ (state << (USB_EPTX_STAT_Pos + (dir == TUSB_DIR_IN ? 0 : 8)));
}
TU_ATTR_ALWAYS_INLINE static inline uint32_t ep_add_dtog(uint32_t reg, tusb_dir_t dir, uint8_t state) {
return reg ^ (state << (USB_EP_DTOG_TX_Pos + (dir == TUSB_DIR_IN ? 0 : 8)));
}
TU_ATTR_ALWAYS_INLINE static inline uint32_t ep_clear_ctr(uint32_t reg, tusb_dir_t dir) {
return reg & ~(1 << (USB_EP_CTR_TX_Pos + (dir == TUSB_DIR_IN ? 0 : 8)));
}
TU_ATTR_ALWAYS_INLINE static inline bool ep_is_iso(uint32_t reg) {
return (reg & USB_EP_TYPE_MASK) == USB_EP_ISOCHRONOUS;
}
//--------------------------------------------------------------------+ //--------------------------------------------------------------------+
// BTable // BTable
//--------------------------------------------------------------------+ //--------------------------------------------------------------------+
@@ -243,45 +280,6 @@ TU_ATTR_ALWAYS_INLINE static inline void btable_set_rx_bufsize(uint32_t ep_id, u
#endif #endif
} }
//--------------------------------------------------------------------+
// Endpoint
//--------------------------------------------------------------------+
TU_ATTR_ALWAYS_INLINE static inline void pcd_set_endpoint(USB_TypeDef * USBx, uint32_t ep_id, uint32_t value) {
(void) USBx;
FSDEV_REG->ep[ep_id].reg = (fsdev_bus_t) value;
}
// write ep register with clear CTR_RX and CTR_TX mask (0 is no clear)
//TU_ATTR_ALWAYS_INLINE static inline void ep_write_with_clear_ctr(uint32_t ep_id, uint32_t value, uint32_t clear_ctr_mask) {
// value |= USB_EP_CTR_RX | USB_EP_CTR_TX;
// if (clear_ctr_mask) {
// value &= ~clear_ctr_mask;
// }
// FSDEV_REG->ep[ep_id].reg = (fsdev_bus_t) value;
//}
TU_ATTR_ALWAYS_INLINE static inline uint32_t pcd_get_endpoint(USB_TypeDef * USBx, uint32_t ep_id) {
(void) USBx;
return FSDEV_REG->ep[ep_id].reg;
}
TU_ATTR_ALWAYS_INLINE static inline uint32_t ep_add_status(uint32_t reg, tusb_dir_t dir, ep_stat_t state) {
return reg ^ (state << (USB_EPTX_STAT_Pos + (dir == TUSB_DIR_IN ? 0 : 8)));
}
TU_ATTR_ALWAYS_INLINE static inline uint32_t ep_add_dtog(uint32_t reg, tusb_dir_t dir, uint8_t state) {
return reg ^ (state << (USB_EP_DTOG_TX_Pos + (dir == TUSB_DIR_IN ? 0 : 8)));
}
TU_ATTR_ALWAYS_INLINE static inline uint32_t ep_clear_ctr(uint32_t reg, tusb_dir_t dir) {
return reg & ~(1 << (USB_EP_CTR_TX_Pos + (dir == TUSB_DIR_IN ? 0 : 8)));
}
TU_ATTR_ALWAYS_INLINE static inline bool ep_is_iso(uint32_t reg) {
return (reg & USB_EP_TYPE_MASK) == USB_EP_ISOCHRONOUS;
}
#ifdef __cplusplus #ifdef __cplusplus
} }
#endif #endif