diff --git a/src/portable/chipidea/ci_hs/hcd_ci_hs.c b/src/portable/chipidea/ci_hs/hcd_ci_hs.c
index ecb1a621c..ab6a42e11 100644
--- a/src/portable/chipidea/ci_hs/hcd_ci_hs.c
+++ b/src/portable/chipidea/ci_hs/hcd_ci_hs.c
@@ -42,17 +42,28 @@
 #if CFG_TUSB_MCU == OPT_MCU_MIMXRT
   #include "ci_hs_imxrt.h"
 
+  // check if memory is cacheable i.e not in DTCM
+  TU_ATTR_ALWAYS_INLINE static inline bool is_cache_mem(uint32_t addr) {
+    return !(0x20000000 <= addr && addr < 0x20100000);
+  }
+
   void hcd_dcache_clean(void* addr, uint32_t data_size) {
-    SCB_CleanDCache_by_Addr((uint32_t*) addr, (int32_t) data_size);
+    if (is_cache_mem((uint32_t) addr)) {
+      SCB_CleanDCache_by_Addr((uint32_t *) addr, (int32_t) data_size);
+    }
   }
 
   void hcd_dcache_invalidate(void* addr, uint32_t data_size) {
-    SCB_InvalidateDCache_by_Addr(addr, (int32_t) data_size);
+    if (is_cache_mem((uint32_t) addr)) {
+      SCB_InvalidateDCache_by_Addr(addr, (int32_t) data_size);
+    }
   }
 
 void hcd_dcache_clean_invalidate(void* addr, uint32_t data_size) {
+  if (is_cache_mem((uint32_t) addr)) {
     SCB_CleanInvalidateDCache_by_Addr(addr, (int32_t) data_size);
   }
+}
 
 #elif TU_CHECK_MCU(OPT_MCU_LPC18XX, OPT_MCU_LPC43XX)
   #include "ci_hs_lpc18_43.h"