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only clean/invalidate dcache on imxrt if memory is not in DTCM

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hathach
2023-05-19 10:56:52 +07:00
parent f22d8ee3b9
commit f26a93908e
1 changed files with 13 additions and 2 deletions
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15
src/portable/chipidea/ci_hs/hcd_ci_hs.c
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@@ -42,17 +42,28 @@
#if CFG_TUSB_MCU == OPT_MCU_MIMXRT #if CFG_TUSB_MCU == OPT_MCU_MIMXRT
#include "ci_hs_imxrt.h" #include "ci_hs_imxrt.h"
// check if memory is cacheable i.e not in DTCM
TU_ATTR_ALWAYS_INLINE static inline bool is_cache_mem(uint32_t addr) {
return !(0x20000000 <= addr && addr < 0x20100000);
}
void hcd_dcache_clean(void* addr, uint32_t data_size) { void hcd_dcache_clean(void* addr, uint32_t data_size) {
SCB_CleanDCache_by_Addr((uint32_t*) addr, (int32_t) data_size); if (is_cache_mem((uint32_t) addr)) {
SCB_CleanDCache_by_Addr((uint32_t *) addr, (int32_t) data_size);
}
} }
void hcd_dcache_invalidate(void* addr, uint32_t data_size) { void hcd_dcache_invalidate(void* addr, uint32_t data_size) {
SCB_InvalidateDCache_by_Addr(addr, (int32_t) data_size); if (is_cache_mem((uint32_t) addr)) {
SCB_InvalidateDCache_by_Addr(addr, (int32_t) data_size);
}
} }
void hcd_dcache_clean_invalidate(void* addr, uint32_t data_size) { void hcd_dcache_clean_invalidate(void* addr, uint32_t data_size) {
if (is_cache_mem((uint32_t) addr)) {
SCB_CleanInvalidateDCache_by_Addr(addr, (int32_t) data_size); SCB_CleanInvalidateDCache_by_Addr(addr, (int32_t) data_size);
} }
}
#elif TU_CHECK_MCU(OPT_MCU_LPC18XX, OPT_MCU_LPC43XX) #elif TU_CHECK_MCU(OPT_MCU_LPC18XX, OPT_MCU_LPC43XX)
#include "ci_hs_lpc18_43.h" #include "ci_hs_lpc18_43.h"