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This commit is contained in:
2025-09-21 19:11:17 +08:00
parent 87406e1391
commit f553c0b100
7 changed files with 63 additions and 12 deletions

View File

@@ -35,9 +35,9 @@
//--------------------------------------------------------------------+
// RHPort number used for device can be defined by board.mk, default to port 0
#ifndef BOARD_TUD_RHPORT
#define BOARD_TUD_RHPORT 0
#endif
// #ifndef BOARD_TUD_RHPORT
// #define BOARD_TUD_RHPORT 0
// #endif
// RHPort max operational speed can defined by board.mk
#ifndef BOARD_TUD_MAX_SPEED
@@ -49,23 +49,43 @@
//--------------------------------------------------------------------
// defined by board.mk
#define CFG_TUSB_MCU OPT_MCU_STM32F4
#ifndef CFG_TUSB_MCU
#error CFG_TUSB_MCU must be defined
#endif
#ifndef CFG_TUSB_OS
#define CFG_TUSB_OS OPT_OS_NONE
#define CFG_TUSB_OS OPT_OS_RTTHREAD
#endif
#ifndef CFG_TUSB_DEBUG
#define CFG_TUSB_DEBUG 0
#define CFG_TUSB_DEBUG 3
#endif
#ifdef CFG_TUSB_DEBUG
#define CFG_TUSB_DEBUG_PRINTF rt_kprintf
#endif /* CFG_TUSB_DEBUG */
// Enable Device stack
#define CFG_TUD_ENABLED 1
// fs is 0; hs is 1
#ifndef BOARD_DEVICE_RHPORT_NUM
#define BOARD_DEVICE_RHPORT_NUM 1
#endif
// Default is max speed that hardware controller could support with on-chip PHY
#define CFG_TUD_MAX_SPEED BOARD_TUD_MAX_SPEED
#ifndef BOARD_DEVICE_RHPORT_SPEED
#define BOARD_DEVICE_RHPORT_SPEED OPT_MODE_FULL_SPEED
#endif
#if BOARD_DEVICE_RHPORT_NUM == 0
#define CFG_TUSB_RHPORT0_MODE (OPT_MODE_DEVICE | BOARD_DEVICE_RHPORT_SPEED)
#elif BOARD_DEVICE_RHPORT_NUM == 1
#define CFG_TUSB_RHPORT1_MODE (OPT_MODE_DEVICE | BOARD_DEVICE_RHPORT_SPEED)
#else
#error "Incorrect RHPort configuration"
#endif
/* USB DMA on some MCUs can only access a specific SRAM region with restriction on alignment.
* Tinyusb use follows macros to declare transferring memory so that they can be put

View File

@@ -58,6 +58,18 @@ int tusb_board_init(void) {
return 0;
}
void usb_irq_enable(){
NVIC_InitTypeDef NVIC_InitStructure;
NVIC_PriorityGroupConfig(NVIC_PriorityGroup_1);
NVIC_InitStructure.NVIC_IRQChannel = OTG_HS_IRQn;
NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 1;
NVIC_InitStructure.NVIC_IRQChannelSubPriority = 3;
NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
NVIC_Init(&NVIC_InitStructure);
}
static void tusb_thread_entry(void *parameter)
{
(void) parameter;
@@ -80,15 +92,16 @@ static int init_tinyusb(void)
//call tusb_rhport_init()
tusb_init();
dcd_int_enable(TUD_OPT_RHPORT);
// dcd_int_enable(TUD_OPT_RHPORT);
usb_irq_enable();
#ifdef RT_USING_HEAP
#ifdef RT_USING_HEAP
tid = rt_thread_create("tusb", tusb_thread_entry, RT_NULL,
2048,
5, 10);
if (tid == RT_NULL)
#else
#else
rt_err_t result;
tid = &tusb_thread;

View File

@@ -535,6 +535,7 @@ bool tud_rhport_init(uint8_t rhport, const tusb_rhport_init_t* rh_init) {
TU_ASSERT(dcd_init(rhport, rh_init));
// dcd_int_enable(rhport);
return true;
}

View File

@@ -440,6 +440,18 @@ bool dcd_init(uint8_t rhport, const tusb_rhport_init_t* rh_init) {
dwc2->gahbcfg = gahbcfg;
dcd_connect(rhport);
TU_LOG(2,"dwc2->gahbcfg=0x%08x\r\n", dwc2->gahbcfg);
TU_LOG(2,"dwc2->gusbcfg=0x%08x\r\n", dwc2->gusbcfg);
TU_LOG(2,"dwc2->gintsts=0x%08x\r\n", dwc2->gintsts);
TU_LOG(2,"dwc2->dcfg=0x%08x\r\n", dwc2->dcfg);
TU_LOG(2,"dwc2->dctl=0x%08x\r\n", dwc2->dctl);
TU_LOG(2,"dwc2->dsts=0x%08x\r\n", dwc2->dsts);
TU_LOG(2,"dwc2->diepmsk=0x%08x\r\n", dwc2->diepmsk);
TU_LOG(2,"dwc2->doepmsk=0x%08x\r\n", dwc2->doepmsk);
TU_LOG(2,"dwc2->daint=0x%08x\r\n", dwc2->daint);
TU_LOG(2,"dwc2->daintmsk=0x%08x\r\n", dwc2->daintmsk);
return true;
}

View File

@@ -84,7 +84,10 @@ static void phy_fs_init(dwc2_regs_t* dwc2) {
// these bits can be programmed to a larger value. Default is 5
gusbcfg &= ~GUSBCFG_TRDT_Msk;
gusbcfg |= 5u << GUSBCFG_TRDT_Pos;
// force to device mode
gusbcfg |= GUSBCFG_FDMOD;
dwc2->gusbcfg = gusbcfg;
osal_task_delay(50);
// MCU specific PHY update post reset
dwc2_phy_update(dwc2, GHWCFG2_HSPHY_NOT_SUPPORTED);
@@ -232,6 +235,7 @@ bool dwc2_core_init(uint8_t rhport, bool is_highspeed, bool is_dma) {
* can vary from one PHY to another. */
dwc2->gusbcfg |= (7ul << GUSBCFG_TOCAL_Pos);
// Enable PHY clock TODO stop/gate clock when suspended mode
dwc2->pcgcctl &= ~(PCGCCTL_STOPPCLK | PCGCCTL_GATEHCLK | PCGCCTL_PWRCLMP | PCGCCTL_RSTPDWNMODULE);

View File

@@ -175,7 +175,8 @@ TU_ATTR_ALWAYS_INLINE static inline void dwc2_remote_wakeup_delay(void) {
static inline void dwc2_phy_init(dwc2_regs_t* dwc2, uint8_t hs_phy_type) {
if (hs_phy_type == GHWCFG2_HSPHY_NOT_SUPPORTED) {
// Enable on-chip FS PHY
dwc2->stm32_gccfg |= STM32_GCCFG_PWRDWN;
dwc2->stm32_gccfg |= STM32_GCCFG_PWRDWN|STM32_GCCFG_VBDEN;
// https://community.st.com/t5/stm32cubemx-mcus/why-stm32h743-usb-fs-doesn-t-work-if-freertos-tickless-idle/m-p/349480#M18867
// H7 running on full-speed phy need to disable ULPI clock in sleep mode.
@@ -272,7 +273,7 @@ static inline void dwc2_phy_update(dwc2_regs_t* dwc2, uint8_t hs_phy_type) {
turnaround = 0xCu;
}
else if (SystemCoreClock >= 16000000u) {
turnaround = 0xDu;
turnaround = 0xfu;
}
else if (SystemCoreClock >= 15000000u) {
turnaround = 0xEu;

View File

@@ -414,7 +414,7 @@
// Level where CFG_TUSB_DEBUG must be at least for USBD is logged
#ifndef CFG_TUD_LOG_LEVEL
#define CFG_TUD_LOG_LEVEL 2
#define CFG_TUD_LOG_LEVEL 3
#endif
// Memory section for placing buffer used for usb transferring. If MEM_SECTION is different for