枚举失败

src/device/usbd.c

@@ -535,6 +535,7 @@ bool tud_rhport_init(uint8_t rhport, const tusb_rhport_init_t* rh_init) {
   TU_ASSERT(dcd_init(rhport, rh_init));
   // dcd_int_enable(rhport);
 
+
   return true;
 }
 

src/portable/synopsys/dwc2/dcd_dwc2.c

@@ -440,6 +440,18 @@ bool dcd_init(uint8_t rhport, const tusb_rhport_init_t* rh_init) {
   dwc2->gahbcfg = gahbcfg;
 
   dcd_connect(rhport);
+
+  TU_LOG(2,"dwc2->gahbcfg=0x%08x\r\n", dwc2->gahbcfg);
+  TU_LOG(2,"dwc2->gusbcfg=0x%08x\r\n", dwc2->gusbcfg);
+  TU_LOG(2,"dwc2->gintsts=0x%08x\r\n", dwc2->gintsts);
+
+  TU_LOG(2,"dwc2->dcfg=0x%08x\r\n", dwc2->dcfg);
+  TU_LOG(2,"dwc2->dctl=0x%08x\r\n", dwc2->dctl);
+  TU_LOG(2,"dwc2->dsts=0x%08x\r\n", dwc2->dsts);
+  TU_LOG(2,"dwc2->diepmsk=0x%08x\r\n", dwc2->diepmsk);
+  TU_LOG(2,"dwc2->doepmsk=0x%08x\r\n", dwc2->doepmsk);
+  TU_LOG(2,"dwc2->daint=0x%08x\r\n", dwc2->daint);
+  TU_LOG(2,"dwc2->daintmsk=0x%08x\r\n", dwc2->daintmsk);
   return true;
 }
 

src/portable/synopsys/dwc2/dwc2_common.c

@@ -84,7 +84,10 @@ static void phy_fs_init(dwc2_regs_t* dwc2) {
   // these bits can be programmed to a larger value. Default is 5
   gusbcfg &= ~GUSBCFG_TRDT_Msk;
   gusbcfg |= 5u << GUSBCFG_TRDT_Pos;
+  // force to device mode
+  gusbcfg |= GUSBCFG_FDMOD;
   dwc2->gusbcfg = gusbcfg;
+  osal_task_delay(50);
 
   // MCU specific PHY update post reset
   dwc2_phy_update(dwc2, GHWCFG2_HSPHY_NOT_SUPPORTED);
@@ -232,6 +235,7 @@ bool dwc2_core_init(uint8_t rhport, bool is_highspeed, bool is_dma) {
    * can vary from one PHY to another. */
   dwc2->gusbcfg |= (7ul << GUSBCFG_TOCAL_Pos);
 
+
   // Enable PHY clock TODO stop/gate clock when suspended mode
   dwc2->pcgcctl &= ~(PCGCCTL_STOPPCLK | PCGCCTL_GATEHCLK | PCGCCTL_PWRCLMP | PCGCCTL_RSTPDWNMODULE);
 

src/portable/synopsys/dwc2/dwc2_stm32.h

@@ -175,7 +175,8 @@ TU_ATTR_ALWAYS_INLINE static inline void dwc2_remote_wakeup_delay(void) {
 static inline void dwc2_phy_init(dwc2_regs_t* dwc2, uint8_t hs_phy_type) {
   if (hs_phy_type == GHWCFG2_HSPHY_NOT_SUPPORTED) {
     // Enable on-chip FS PHY
-    dwc2->stm32_gccfg |= STM32_GCCFG_PWRDWN;
+    dwc2->stm32_gccfg |= STM32_GCCFG_PWRDWN|STM32_GCCFG_VBDEN;
+
 
     // https://community.st.com/t5/stm32cubemx-mcus/why-stm32h743-usb-fs-doesn-t-work-if-freertos-tickless-idle/m-p/349480#M18867
     // H7 running on full-speed phy need to disable ULPI clock in sleep mode.
@@ -272,7 +273,7 @@ static inline void dwc2_phy_update(dwc2_regs_t* dwc2, uint8_t hs_phy_type) {
       turnaround = 0xCu;
     }
     else if (SystemCoreClock >= 16000000u) {
-      turnaround = 0xDu;
+      turnaround = 0xfu;
     }
     else if (SystemCoreClock >= 15000000u) {
       turnaround = 0xEu;

src/tusb_option.h

@@ -414,7 +414,7 @@
 
 // Level where CFG_TUSB_DEBUG must be at least for USBD is logged
 #ifndef CFG_TUD_LOG_LEVEL
-  #define CFG_TUD_LOG_LEVEL   2
+  #define CFG_TUD_LOG_LEVEL   3
 #endif
 
 // Memory section for placing buffer used for usb transferring. If MEM_SECTION is different for