From f5978876d2a5d8cdc6cfd3bf99f9b820c5a6ac8a Mon Sep 17 00:00:00 2001 From: hathach Date: Mon, 21 Oct 2024 11:43:37 +0700 Subject: [PATCH] get hprt interrupt triggered --- .../dual/host_info_to_device_cdc/only.txt | 1 + examples/host/device_info/only.txt | 1 + src/portable/synopsys/dwc2/dcd_dwc2.c | 4 +- src/portable/synopsys/dwc2/dwc2_common.c | 95 +++++++------- src/portable/synopsys/dwc2/dwc2_common.h | 6 +- src/portable/synopsys/dwc2/dwc2_type.h | 27 ++-- src/portable/synopsys/dwc2/hcd_dwc2.c | 117 +++++++----------- 7 files changed, 120 insertions(+), 131 deletions(-) diff --git a/examples/dual/host_info_to_device_cdc/only.txt b/examples/dual/host_info_to_device_cdc/only.txt index 149ece856..f9db1db85 100644 --- a/examples/dual/host_info_to_device_cdc/only.txt +++ b/examples/dual/host_info_to_device_cdc/only.txt @@ -5,3 +5,4 @@ mcu:RP2040 mcu:ra6m5 mcu:MAX3421 mcu:STM32H7 +mcu:STM32F7 diff --git a/examples/host/device_info/only.txt b/examples/host/device_info/only.txt index a38fc251b..aed9583b4 100644 --- a/examples/host/device_info/only.txt +++ b/examples/host/device_info/only.txt @@ -13,3 +13,4 @@ mcu:RP2040 mcu:RX65X mcu:RAXXX mcu:STM32H7 +mcu:STM32F7 diff --git a/src/portable/synopsys/dwc2/dcd_dwc2.c b/src/portable/synopsys/dwc2/dcd_dwc2.c index 55d8f5766..e7440529a 100644 --- a/src/portable/synopsys/dwc2/dcd_dwc2.c +++ b/src/portable/synopsys/dwc2/dcd_dwc2.c @@ -454,7 +454,9 @@ bool dcd_init(uint8_t rhport, const tusb_rhport_init_t* rh_init) { dwc2_regs_t* dwc2 = DWC2_REG(rhport); // Core Initialization - TU_ASSERT(dwc2_core_init(rhport, rh_init)); + const bool is_highspeed = dwc2_core_is_highspeed(dwc2, rh_init); + const bool is_dma = dwc2_dma_enabled(dwc2, TUSB_ROLE_DEVICE); + TU_ASSERT(dwc2_core_init(rhport, is_highspeed, is_dma)); // Device Initialization dcd_disconnect(rhport); diff --git a/src/portable/synopsys/dwc2/dwc2_common.c b/src/portable/synopsys/dwc2/dwc2_common.c index 12dcdb7c6..a5f1c2b08 100644 --- a/src/portable/synopsys/dwc2/dwc2_common.c +++ b/src/portable/synopsys/dwc2/dwc2_common.c @@ -40,6 +40,9 @@ #include "dwc2_common.h" +//-------------------------------------------------------------------- +// +//-------------------------------------------------------------------- static void reset_core(dwc2_regs_t* dwc2) { // reset core dwc2->grstctl |= GRSTCTL_CSRST; @@ -57,24 +60,7 @@ static void reset_core(dwc2_regs_t* dwc2) { while (!(dwc2->grstctl & GRSTCTL_AHBIDL)) {} // wait for AHB master IDLE } -bool dwc2_core_is_highspeed(dwc2_regs_t* dwc2, const tusb_rhport_init_t* rh_init) { - (void)dwc2; - -#if CFG_TUD_ENABLED - if (rh_init->role == TUSB_ROLE_DEVICE && !TUD_OPT_HIGH_SPEED) { - return false; - } -#endif -#if CFG_TUH_ENABLED - if (rh_init->role == TUSB_ROLE_HOST && !TUH_OPT_HIGH_SPEED) { - return false; - } -#endif - - return dwc2->ghwcfg2_bm.hs_phy_type != GHWCFG2_HSPHY_NOT_SUPPORTED; -} - -static void phy_fs_init(dwc2_regs_t* dwc2, tusb_role_t role) { +static void phy_fs_init(dwc2_regs_t* dwc2) { TU_LOG(DWC2_COMMON_DEBUG, "Fullspeed PHY init\r\n"); uint32_t gusbcfg = dwc2->gusbcfg; @@ -96,29 +82,11 @@ static void phy_fs_init(dwc2_regs_t* dwc2, tusb_role_t role) { gusbcfg |= 5u << GUSBCFG_TRDT_Pos; dwc2->gusbcfg = gusbcfg; - // FS/LS PHY Clock Select - if (role == TUSB_ROLE_HOST) { - uint32_t hcfg = dwc2->hcfg; - hcfg |= HCFG_FSLS_ONLY; - hcfg &= ~HCFG_FSLS_PHYCLK_SEL; - - if (dwc2->ghwcfg2_bm.hs_phy_type == GHWCFG2_HSPHY_ULPI && - dwc2->ghwcfg2_bm.fs_phy_type == GHWCFG2_FSPHY_DEDICATED) { - // dedicated FS PHY with 48 mhz - hcfg |= HCFG_FSLS_PHYCLK_SEL_48MHZ; - } else { - // shared HS PHY running at full speed - hcfg |= HCFG_FSLS_PHYCLK_SEL_30_60MHZ; - } - dwc2->hcfg = hcfg; - } - // MCU specific PHY update post reset dwc2_phy_update(dwc2, GHWCFG2_HSPHY_NOT_SUPPORTED); } -static void phy_hs_init(dwc2_regs_t* dwc2, tusb_role_t role) { - (void) role; +static void phy_hs_init(dwc2_regs_t* dwc2) { uint32_t gusbcfg = dwc2->gusbcfg; // De-select FS PHY @@ -164,10 +132,6 @@ static void phy_hs_init(dwc2_regs_t* dwc2, tusb_role_t role) { // Reset core after selecting PHY reset_core(dwc2); - if (role == TUSB_ROLE_HOST) { - dwc2->hcfg &= ~HCFG_FSLS_ONLY; - } - // Set turn-around, must after core reset otherwise it will be clear // - 9 if using 8-bit PHY interface // - 5 if using 16-bit PHY interface @@ -204,17 +168,36 @@ static bool check_dwc2(dwc2_regs_t* dwc2) { //-------------------------------------------------------------------- // //-------------------------------------------------------------------- -bool dwc2_core_init(uint8_t rhport, const tusb_rhport_init_t* rh_init) { - (void)rh_init; +bool dwc2_core_is_highspeed(dwc2_regs_t* dwc2, const tusb_rhport_init_t* rh_init) { + (void)dwc2; + +#if CFG_TUD_ENABLED + if (rh_init->role == TUSB_ROLE_DEVICE && !TUD_OPT_HIGH_SPEED) { + return false; + } +#endif +#if CFG_TUH_ENABLED + if (rh_init->role == TUSB_ROLE_HOST && !TUH_OPT_HIGH_SPEED) { + return false; + } +#endif + + return dwc2->ghwcfg2_bm.hs_phy_type != GHWCFG2_HSPHY_NOT_SUPPORTED; +} + +bool dwc2_core_init(uint8_t rhport, bool is_highspeed, bool is_dma) { dwc2_regs_t* dwc2 = DWC2_REG(rhport); // Check Synopsys ID register, failed if controller clock/power is not enabled TU_ASSERT(check_dwc2(dwc2)); - if (dwc2_core_is_highspeed(dwc2, rh_init)) { - phy_hs_init(dwc2, rh_init->role); + // disable global interrupt + // dwc2->gahbcfg &= ~GAHBCFG_GINT; + + if (is_highspeed) { + phy_hs_init(dwc2); } else { - phy_fs_init(dwc2, rh_init->role); + phy_fs_init(dwc2); } /* Set HS/FS Timeout Calibration to 7 (max available value). @@ -243,7 +226,12 @@ bool dwc2_core_init(uint8_t rhport, const tusb_rhport_init_t* rh_init) { dwc2->gintmsk = 0; - if (dwc2_dma_enabled(dwc2, rh_init->role)) { + // TODO can be enabled with device as well but tested with host for now + // if (rh_init->role == TUSB_ROLE_HOST) { + // dwc2->gintmsk |= OTG_INT_COMMON; + // } + + if (is_dma) { const uint16_t epinfo_base = dma_cal_epfifo_base(rhport); dwc2->gdfifocfg = (epinfo_base << GDFIFOCFG_EPINFOBASE_SHIFT) | epinfo_base; @@ -259,4 +247,17 @@ bool dwc2_core_init(uint8_t rhport, const tusb_rhport_init_t* rh_init) { return true; } +// void dwc2_core_handle_common_irq(uint8_t rhport, bool in_isr) { +// (void) in_isr; +// dwc2_regs_t * const dwc2 = DWC2_REG(rhport); +// const uint32_t int_mask = dwc2->gintmsk; +// const uint32_t int_status = dwc2->gintsts & int_mask; +// +// // Device disconnect +// if (int_status & GINTSTS_DISCINT) { +// dwc2->gintsts = GINTSTS_DISCINT; +// } +// +// } + #endif diff --git a/src/portable/synopsys/dwc2/dwc2_common.h b/src/portable/synopsys/dwc2/dwc2_common.h index 538fcd179..7088ff3c3 100644 --- a/src/portable/synopsys/dwc2/dwc2_common.h +++ b/src/portable/synopsys/dwc2/dwc2_common.h @@ -57,6 +57,9 @@ enum { DWC2_CONTROLLER_COUNT = TU_ARRAY_SIZE(_dwc2_controller) }; +enum { + OTG_INT_COMMON = 0 // GINTSTS_DISCINT | GINTSTS_CONIDSTSCHNG +}; //------------- Core -------------// TU_ATTR_ALWAYS_INLINE static inline dwc2_regs_t* DWC2_REG(uint8_t rhport) { @@ -68,7 +71,8 @@ TU_ATTR_ALWAYS_INLINE static inline dwc2_regs_t* DWC2_REG(uint8_t rhport) { } bool dwc2_core_is_highspeed(dwc2_regs_t* dwc2, const tusb_rhport_init_t* rh_init); -bool dwc2_core_init(uint8_t rhport, const tusb_rhport_init_t* rh_init); +bool dwc2_core_init(uint8_t rhport, bool is_highspeed, bool is_dma); +void dwc2_core_handle_common_irq(uint8_t rhport, bool in_isr); //------------- DFIFO -------------// TU_ATTR_ALWAYS_INLINE static inline void dfifo_flush_tx(dwc2_regs_t* dwc2, uint8_t fnum) { diff --git a/src/portable/synopsys/dwc2/dwc2_type.h b/src/portable/synopsys/dwc2/dwc2_type.h index f99bf3e85..8fb926a21 100644 --- a/src/portable/synopsys/dwc2/dwc2_type.h +++ b/src/portable/synopsys/dwc2/dwc2_type.h @@ -86,6 +86,11 @@ typedef struct } HS_PHYC_GlobalTypeDef; #endif +enum { + GOTGCTL_OTG_VERSION_1_3 = 0, + GOTGCTL_OTG_VERSION_2_0 = 1, +}; + enum { GHWCFG2_OPMODE_HNP_SRP = 0, GHWCFG2_OPMODE_SRP = 1, @@ -128,6 +133,11 @@ enum { HPRT_SPEED_LOW = 2 }; +enum { + GINTSTS_CMODE_DEVICE = 0, + GINTSTS_CMODE_HOST = 1, +}; + //-------------------------------------------------------------------- // Register bitfield definitions //-------------------------------------------------------------------- @@ -152,7 +162,7 @@ typedef struct TU_ATTR_PACKED { uint32_t ases_valid : 1; // 18 A-session valid uint32_t bses_valid : 1; // 19 B-session valid uint32_t otg_ver : 1; // 20 OTG version 0: v1.3, 1: v2.0 - uint32_t current_mode : 1; // 21 Current mode of operation 0: device, 1: host + uint32_t current_mode : 1; // 21 Current mode of operation. Only from v3.00a uint32_t mult_val_id_bc : 5; // 22..26 Multi-valued input pin ID battery charger uint32_t chirp_en : 1; // 27 Chirp detection enable uint32_t rsv28_30 : 3; // 28.30: Reserved @@ -391,7 +401,10 @@ TU_VERIFY_STATIC(sizeof(dwc2_dep_t) == 0x20, "incorrect size"); //-------------------------------------------------------------------- typedef struct { //------------- Core Global -------------// + union { volatile uint32_t gotgctl; // 000 OTG Control and Status + volatile dwc2_gotgctl_t gotgctl_bm; + }; volatile uint32_t gotgint; // 004 OTG Interrupt volatile uint32_t gahbcfg; // 008 AHB Configuration volatile uint32_t gusbcfg; // 00c USB Configuration @@ -1008,9 +1021,9 @@ TU_VERIFY_STATIC(offsetof(dwc2_regs_t, fifo ) == 0x1000, "incorrect size"); #define GINTSTS_LPMINT_Pos (27U) #define GINTSTS_LPMINT_Msk (0x1UL << GINTSTS_LPMINT_Pos) // 0x08000000 #define GINTSTS_LPMINT GINTSTS_LPMINT_Msk // LPM interrupt -#define GINTSTS_CIDSCHG_Pos (28U) -#define GINTSTS_CIDSCHG_Msk (0x1UL << GINTSTS_CIDSCHG_Pos) // 0x10000000 -#define GINTSTS_CIDSCHG GINTSTS_CIDSCHG_Msk // Connector ID status change +#define GINTSTS_CONIDSTSCHNG_Pos (28U) +#define GINTSTS_CONIDSTSCHNG_Msk (0x1UL << GINTSTS_CONIDSTSCHNG_Pos) // 0x10000000 +#define GINTSTS_CONIDSTSCHNG GINTSTS_CONIDSTSCHNG_Msk // Connector ID status change #define GINTSTS_DISCINT_Pos (29U) #define GINTSTS_DISCINT_Msk (0x1UL << GINTSTS_DISCINT_Pos) // 0x20000000 #define GINTSTS_DISCINT GINTSTS_DISCINT_Msk // Disconnect detected interrupt @@ -1094,9 +1107,9 @@ TU_VERIFY_STATIC(offsetof(dwc2_regs_t, fifo ) == 0x1000, "incorrect size"); #define GINTMSK_LPMINTM_Pos (27U) #define GINTMSK_LPMINTM_Msk (0x1UL << GINTMSK_LPMINTM_Pos) // 0x08000000 #define GINTMSK_LPMINTM GINTMSK_LPMINTM_Msk // LPM interrupt Mask -#define GINTMSK_CIDSCHGM_Pos (28U) -#define GINTMSK_CIDSCHGM_Msk (0x1UL << GINTMSK_CIDSCHGM_Pos) // 0x10000000 -#define GINTMSK_CIDSCHGM GINTMSK_CIDSCHGM_Msk // Connector ID status change mask +#define GINTMSK_CONIDSTSCHNGM_Pos (28U) +#define GINTMSK_CONIDSTSCHNGM_Msk (0x1UL << GINTMSK_CONIDSTSCHNGM_Pos) // 0x10000000 +#define GINTMSK_CONIDSTSCHNGM GINTMSK_CONIDSTSCHNGM_Msk // Connector ID status change mask #define GINTMSK_DISCINT_Pos (29U) #define GINTMSK_DISCINT_Msk (0x1UL << GINTMSK_DISCINT_Pos) // 0x20000000 #define GINTMSK_DISCINT GINTMSK_DISCINT_Msk // Disconnect detected interrupt mask diff --git a/src/portable/synopsys/dwc2/hcd_dwc2.c b/src/portable/synopsys/dwc2/hcd_dwc2.c index 97068d4c5..2d4368e94 100644 --- a/src/portable/synopsys/dwc2/hcd_dwc2.c +++ b/src/portable/synopsys/dwc2/hcd_dwc2.c @@ -56,25 +56,40 @@ bool hcd_init(uint8_t rhport, const tusb_rhport_init_t* rh_init) { dwc2_regs_t* dwc2 = DWC2_REG(rhport); // Core Initialization - TU_ASSERT(dwc2_core_init(rhport, rh_init)); + const bool is_highspeed = dwc2_core_is_highspeed(dwc2, rh_init); + const bool is_dma = dwc2_dma_enabled(dwc2, TUSB_ROLE_HOST); + TU_ASSERT(dwc2_core_init(rhport, is_highspeed, is_dma)); //------------- 3.1 Host Initialization -------------// - // max speed - // if (dwc2_core_is_highspeed(dwc2, rh_init)) { - // dwc2->hcfg &= ~HCFG_FSLS_ONLY; - // } else { - // dwc2->hcfg |= HCFG_FSLS_ONLY; - // } + // FS/LS PHY Clock Select + uint32_t hcfg = dwc2->hcfg; + if (is_highspeed) { + hcfg &= ~HCFG_FSLS_ONLY; + } else { + hcfg &= ~HCFG_FSLS_ONLY; // since we are using FS PHY + hcfg &= ~HCFG_FSLS_PHYCLK_SEL; - // force host mode + if (dwc2->ghwcfg2_bm.hs_phy_type == GHWCFG2_HSPHY_ULPI && + dwc2->ghwcfg2_bm.fs_phy_type == GHWCFG2_FSPHY_DEDICATED) { + // dedicated FS PHY with 48 mhz + hcfg |= HCFG_FSLS_PHYCLK_SEL_48MHZ; + } else { + // shared HS PHY running at full speed + hcfg |= HCFG_FSLS_PHYCLK_SEL_30_60MHZ; + } + } + dwc2->hcfg = hcfg; + + // force host mode and wait for mode switch dwc2->gusbcfg = (dwc2->gusbcfg & ~GUSBCFG_FDMOD) | GUSBCFG_FHMOD; + while( (dwc2->gintsts & GINTSTS_CMOD) != GINTSTS_CMODE_HOST) {} dwc2->hprt = HPRT_W1C_MASK; // clear all write-1-clear bits - dwc2->hprt = HPRT_POWER; // port power on -> drive VBUS + dwc2->hprt = HPRT_POWER; // turn on VBUS // Enable required interrupts - dwc2->gintmsk |= GINTMSK_OTGINT | GINTMSK_PRTIM | GINTMSK_WUIM; + dwc2->gintmsk |= GINTMSK_OTGINT | GINTSTS_CONIDSTSCHNG | GINTMSK_PRTIM; // | GINTMSK_WUIM; dwc2->gahbcfg |= GAHBCFG_GINT; // Enable global interrupt return true; @@ -193,74 +208,15 @@ bool hcd_edpt_clear_stall(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr) { #if 1 static void handle_rxflvl_irq(uint8_t rhport) { dwc2_regs_t* dwc2 = DWC2_REG(rhport); - volatile uint32_t const* rx_fifo = dwc2->fifo[0]; + // volatile uint32_t const* rx_fifo = dwc2->fifo[0]; // Pop control word off FIFO uint32_t const grxstsp = dwc2->grxstsp; - uint8_t const pktsts = (grxstsp & GRXSTSP_PKTSTS_Msk) >> GRXSTSP_PKTSTS_Pos; - uint8_t const epnum = (grxstsp & GRXSTSP_EPNUM_Msk) >> GRXSTSP_EPNUM_Pos; - uint16_t const bcnt = (grxstsp & GRXSTSP_BCNT_Msk) >> GRXSTSP_BCNT_Pos; + (void) grxstsp; + // uint8_t const pktsts = (grxstsp & GRXSTSP_PKTSTS_Msk) >> GRXSTSP_PKTSTS_Pos; + // uint8_t const epnum = (grxstsp & GRXSTSP_EPNUM_Msk) >> GRXSTSP_EPNUM_Pos; + // uint16_t const bcnt = (grxstsp & GRXSTSP_BCNT_Msk) >> GRXSTSP_BCNT_Pos; // dwc2_epout_t* epout = &dwc2->epout[epnum]; - - (void) epnum; (void) bcnt; (void) rx_fifo; - - TU_LOG1_INT(pktsts); - - // switch (pktsts) { - // // Global OUT NAK: do nothing - // case GRXSTS_PKTSTS_GLOBALOUTNAK: - // break; - // - // case GRXSTS_PKTSTS_SETUPRX: - // // Setup packet received - // // We can receive up to three setup packets in succession, but only the last one is valid. - // _setup_packet[0] = (*rx_fifo); - // _setup_packet[1] = (*rx_fifo); - // break; - // - // case GRXSTS_PKTSTS_SETUPDONE: - // // Setup packet done: - // // After popping this out, dwc2 asserts a DOEPINT_SETUP interrupt which is handled by handle_epout_irq() - // epout->doeptsiz |= (3 << DOEPTSIZ_STUPCNT_Pos); - // break; - // - // case GRXSTS_PKTSTS_OUTRX: { - // // Out packet received - // xfer_ctl_t* xfer = XFER_CTL_BASE(epnum, TUSB_DIR_OUT); - // - // // Read packet off RxFIFO - // if (xfer->ff) { - // // Ring buffer - // tu_fifo_write_n_const_addr_full_words(xfer->ff, (const void*) (uintptr_t) rx_fifo, bcnt); - // } else { - // // Linear buffer - // dfifo_read_packet(rhport, xfer->buffer, bcnt); - // - // // Increment pointer to xfer data - // xfer->buffer += bcnt; - // } - // - // // Truncate transfer length in case of short packet - // if (bcnt < xfer->max_size) { - // xfer->total_len -= (epout->doeptsiz & DOEPTSIZ_XFRSIZ_Msk) >> DOEPTSIZ_XFRSIZ_Pos; - // if (epnum == 0) { - // xfer->total_len -= ep0_pending[TUSB_DIR_OUT]; - // ep0_pending[TUSB_DIR_OUT] = 0; - // } - // } - // break; - // } - // - // case GRXSTS_PKTSTS_OUTDONE: - // /* Out packet done - // After this entry is popped from the receive FIFO, dwc2 asserts a Transfer Completed interrupt on - // the specified OUT endpoint which will be handled by handle_epout_irq() */ - // break; - // - // default: - // TU_BREAKPOINT(); - // break; - // } } #endif @@ -305,10 +261,21 @@ TU_ATTR_ALWAYS_INLINE static inline void handle_hprt_irq(uint8_t rhport, bool in */ void hcd_int_handler(uint8_t rhport, bool in_isr) { dwc2_regs_t* dwc2 = DWC2_REG(rhport); - const uint32_t int_mask = dwc2->gintmsk; const uint32_t int_status = dwc2->gintsts & int_mask; + TU_LOG1_HEX(int_status); + + if (int_status & GINTSTS_CONIDSTSCHNG) { + // Connector ID status change + dwc2->gintsts = GINTSTS_CONIDSTSCHNG; + + //if (dwc2->gotgctl) + // dwc2->hprt = HPRT_POWER; // power on port to turn on VBUS + //dwc2->gintmsk |= GINTMSK_PRTIM; + // TODO wait for SRP if OTG + } + if (int_status & GINTSTS_HPRTINT) { TU_LOG1_HEX(dwc2->hprt); handle_hprt_irq(rhport, in_isr);