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Merge pull request #123 from pigrew/stm32_fsdev

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STM32 FS Device Driver
This commit is contained in:
hathach
2019-09-11 00:06:34 +07:00
committed by GitHub
parent 4fe34c8f9b 4f6bedeac9
commit f5e58a09ad
18 changed files with 1884 additions and 107 deletions
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4
.gitignore vendored
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@@ -1,6 +1,5 @@
html
latex
test/_build
*.d
*.o
*.P
@@ -14,4 +13,5 @@ test/_build
.env
/examples/*/*/build-*
test_old/
tests_obsolete/
tests_obsolete/
_build

2
README.md
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@@ -55,7 +55,7 @@ The stack supports the following MCUs
- **Nordic:** nRF52840
- **NXP:** LPC11Uxx, LPC13xx, LPC175x_6x, LPC177x_8x, LPC18xx, LPC40xx, LPC43xx, LPC51Uxx
- **MicroChip:** SAMD21, SAMD51 (device only)
- **ST:** STM32F4, STM32H7 (device only)
- **ST:** STM32F070xB, STM32F4, STM32H7 (device only)
[Here is the list of supported Boards](docs/boards.md)

2
docs/boards.md
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@@ -39,7 +39,7 @@ This code base already had supported for a handful of following boards
- [Adafruit Metro M4 Express](https://www.adafruit.com/product/3382)
### ST STM32
- [STM32F070RB Nucleo](https://www.st.com/en/evaluation-tools/nucleo-f070rb.html)
- [STM32F407g Discovery](https://www.st.com/en/evaluation-tools/stm32f4discovery.html)
- [STM32F411e Discovery](https://www.st.com/en/evaluation-tools/32f411ediscovery.html)
- [STM32F412g Discovery](https://www.st.com/en/evaluation-tools/32f412gdiscovery.html)

2
examples/device/msc_dual_lun/src/msc_disk_dual.c
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@@ -31,7 +31,7 @@
// Some MCU doesn't have enough 8KB SRAM to store the whole disk
// We will use Flash as read-only disk
// - LPC1347, LPC11uxx
#if (CFG_TUSB_MCU == OPT_MCU_LPC13XX) || (CFG_TUSB_MCU == OPT_MCU_LPC11UXX)
#if (CFG_TUSB_MCU == OPT_MCU_LPC13XX) || (CFG_TUSB_MCU == OPT_MCU_LPC11UXX) || defined(STM32F070xB)
#define DISK_READONLY
#endif

50
hw/bsp/stm32f070rbnucleo/board.mk Normal file
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@@ -0,0 +1,50 @@
CFLAGS += \
-DHSE_VALUE=8000000 \
-DSTM32F070xB \
-mthumb \
-mabi=aapcs-linux \
-mcpu=cortex-m0 \
-mfloat-abi=soft \
-nostdlib -nostartfiles \
-DCFG_TUSB_MCU=OPT_MCU_STM32F0
ST_HAL_DRIVER = hw/mcu/st/st_driver/STM32F0xx_HAL_Driver
ST_CMSIS = hw/mcu/st/st_driver/CMSIS/Device/ST/STM32F0xx
# All source paths should be relative to the top level.
LD_FILE = hw/bsp/stm32f070rbnucleo/stm32F070rbtx_flash.ld
SRC_C += \
$(ST_CMSIS)/Source/Templates/system_stm32f0xx.c \
$(ST_HAL_DRIVER)/Src/stm32f0xx_hal.c \
$(ST_HAL_DRIVER)/Src/stm32f0xx_hal_cortex.c \
$(ST_HAL_DRIVER)/Src/stm32f0xx_hal_rcc.c \
$(ST_HAL_DRIVER)/Src/stm32f0xx_hal_rcc_ex.c \
$(ST_HAL_DRIVER)/Src/stm32f0xx_hal_gpio.c
SRC_S += \
$(ST_CMSIS)/Source/Templates/gcc/startup_stm32f070xb.s
INC += \
$(TOP)/hw/mcu/st/st_driver/CMSIS/Include \
$(TOP)/$(ST_CMSIS)/Include \
$(TOP)/$(ST_HAL_DRIVER)/Inc \
$(TOP)/hw/bsp/$(BOARD)
# For TinyUSB port source
VENDOR = st
CHIP_FAMILY = stm32_fsdev
# For freeRTOS port source
FREERTOS_PORT = ARM_CM0
# For flash-jlink target
JLINK_DEVICE = stm32f070rb
JLINK_IF = swd
# Path to STM32 Cube Programmer CLI, should be added into system path
STM32Prog = STM32_Programmer_CLI
# flash target using on-board stlink
flash: $(BUILD)/$(BOARD)-firmware.elf
$(STM32Prog) --connect port=swd --write $< --go

200
hw/bsp/stm32f070rbnucleo/stm32F070rbtx_flash.ld Normal file
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@@ -0,0 +1,200 @@
/*
******************************************************************************
**
** File : LinkerScript.ld
**
** Author : Auto-generated by STM32CubeIDE
**
** Abstract : Linker script for STM32F070RBTx Device from STM32F0 series
** 128Kbytes FLASH
** 16Kbytes RAM
**
** Set heap size, stack size and stack location according
** to application requirements.
**
** Set memory bank area and size if external memory is used.
**
** Target : STMicroelectronics STM32
**
** Distribution: The file is distributed as is without any warranty
** of any kind.
**
*****************************************************************************
** @attention
**
** <h2><center>&copy; COPYRIGHT(c) 2019 STMicroelectronics</center></h2>
**
** Redistribution and use in source and binary forms, with or without modification,
** are permitted provided that the following conditions are met:
** 1. Redistributions of source code must retain the above copyright notice,
** this list of conditions and the following disclaimer.
** 2. Redistributions in binary form must reproduce the above copyright notice,
** this list of conditions and the following disclaimer in the documentation
** and/or other materials provided with the distribution.
** 3. Neither the name of STMicroelectronics nor the names of its contributors
** may be used to endorse or promote products derived from this software
** without specific prior written permission.
**
** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
** AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
** IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
** FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
** DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
** CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
** OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
** OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
**
*****************************************************************************
*/
/* Entry Point */
ENTRY(Reset_Handler)
/* Highest address of the user mode stack */
_estack = 0x20004000; /* end of "RAM" Ram type memory */
_Min_Heap_Size = 0x400; /* required amount of heap */
_Min_Stack_Size = 0x600; /* required amount of stack */
/* Memories definition */
MEMORY
{
RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 16K
FLASH (rx) : ORIGIN = 0x8000000, LENGTH = 128K
}
/* Sections */
SECTIONS
{
/* The startup code into "FLASH" Rom type memory */
.isr_vector :
{
. = ALIGN(4);
KEEP(*(.isr_vector)) /* Startup code */
. = ALIGN(4);
} >FLASH
/* The program code and other data into "FLASH" Rom type memory */
.text :
{
. = ALIGN(4);
*(.text) /* .text sections (code) */
*(.text*) /* .text* sections (code) */
*(.glue_7) /* glue arm to thumb code */
*(.glue_7t) /* glue thumb to arm code */
*(.eh_frame)
KEEP (*(.init))
KEEP (*(.fini))
. = ALIGN(4);
_etext = .; /* define a global symbols at end of code */
} >FLASH
/* Constant data into "FLASH" Rom type memory */
.rodata :
{
. = ALIGN(4);
*(.rodata) /* .rodata sections (constants, strings, etc.) */
*(.rodata*) /* .rodata* sections (constants, strings, etc.) */
. = ALIGN(4);
} >FLASH
.ARM.extab : {
. = ALIGN(4);
*(.ARM.extab* .gnu.linkonce.armextab.*)
. = ALIGN(4);
} >FLASH
.ARM : {
. = ALIGN(4);
__exidx_start = .;
*(.ARM.exidx*)
__exidx_end = .;
. = ALIGN(4);
} >FLASH
.preinit_array :
{
. = ALIGN(4);
PROVIDE_HIDDEN (__preinit_array_start = .);
KEEP (*(.preinit_array*))
PROVIDE_HIDDEN (__preinit_array_end = .);
. = ALIGN(4);
} >FLASH
.init_array :
{
. = ALIGN(4);
PROVIDE_HIDDEN (__init_array_start = .);
KEEP (*(SORT(.init_array.*)))
KEEP (*(.init_array*))
PROVIDE_HIDDEN (__init_array_end = .);
. = ALIGN(4);
} >FLASH
.fini_array :
{
. = ALIGN(4);
PROVIDE_HIDDEN (__fini_array_start = .);
KEEP (*(SORT(.fini_array.*)))
KEEP (*(.fini_array*))
PROVIDE_HIDDEN (__fini_array_end = .);
. = ALIGN(4);
} >FLASH
/* Used by the startup to initialize data */
_sidata = LOADADDR(.data);
/* Initialized data sections into "RAM" Ram type memory */
.data :
{
. = ALIGN(4);
_sdata = .; /* create a global symbol at data start */
*(.data) /* .data sections */
*(.data*) /* .data* sections */
. = ALIGN(4);
_edata = .; /* define a global symbol at data end */
} >RAM AT> FLASH
/* Uninitialized data section into "RAM" Ram type memory */
. = ALIGN(4);
.bss :
{
/* This is used by the startup in order to initialize the .bss secion */
_sbss = .; /* define a global symbol at bss start */
__bss_start__ = _sbss;
*(.bss)
*(.bss*)
*(COMMON)
. = ALIGN(4);
_ebss = .; /* define a global symbol at bss end */
__bss_end__ = _ebss;
} >RAM
/* User_heap_stack section, used to check that there is enough "RAM" Ram type memory left */
._user_heap_stack :
{
. = ALIGN(8);
PROVIDE ( end = . );
PROVIDE ( _end = . );
. = . + _Min_Heap_Size;
. = . + _Min_Stack_Size;
. = ALIGN(8);
} >RAM
/* Remove information from the compiler libraries */
/DISCARD/ :
{
libc.a ( * )
libm.a ( * )
libgcc.a ( * )
}
.ARM.attributes 0 : { *(.ARM.attributes) }
}

152
hw/bsp/stm32f070rbnucleo/stm32f070rbnucleo.c Normal file
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@@ -0,0 +1,152 @@
/*
* The MIT License (MIT)
*
* Copyright (c) 2019 Ha Thach (tinyusb.org)
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*
* This file is part of the TinyUSB stack.
*/
#include "../board.h"
#include "stm32f0xx.h"
#include "stm32f0xx_hal_conf.h"
#define LED_PORT GPIOC
#define LED_PIN GPIO_PIN_13
#define LED_STATE_ON 1
#define BUTTON_PORT GPIOA
#define BUTTON_PIN GPIO_PIN_5
#define BUTTON_STATE_ACTIVE 1
void board_init(void)
{
#if CFG_TUSB_OS == OPT_OS_NONE
// 1ms tick timer
SysTick_Config(SystemCoreClock / 1000);
#endif
/* Configure the system clock to 48 MHz */
RCC_ClkInitTypeDef RCC_ClkInitStruct;
RCC_OscInitTypeDef RCC_OscInitStruct;
RCC_PeriphCLKInitTypeDef PeriphClkInit = {0};
/* Enable HSE Oscillator and activate PLL with 8 MHz HSE as source */
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
RCC_OscInitStruct.HSEState = RCC_HSE_BYPASS;
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
RCC_OscInitStruct.PLL.PLLMUL = RCC_PLL_MUL6;
RCC_OscInitStruct.PLL.PREDIV = RCC_PREDIV_DIV1;
HAL_RCC_OscConfig(&RCC_OscInitStruct);
/* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2
clocks dividers */
RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_PCLK1;
RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
(void) HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1);
PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_USB;
PeriphClkInit.UsbClockSelection = RCC_USBCLKSOURCE_PLL;
(void)HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) ;
// Notify runtime of frequency change.
SystemCoreClockUpdate();
// LED
__HAL_RCC_GPIOC_CLK_ENABLE();
GPIO_InitTypeDef GPIO_InitStruct;
GPIO_InitStruct.Pin = LED_PIN;
GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
GPIO_InitStruct.Pull = GPIO_PULLUP;
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;
HAL_GPIO_Init(LED_PORT, &GPIO_InitStruct);
// Button
__HAL_RCC_GPIOA_CLK_ENABLE();
GPIO_InitStruct.Pin = BUTTON_PIN;
GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
GPIO_InitStruct.Pull = GPIO_PULLDOWN;
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;
HAL_GPIO_Init(BUTTON_PORT, &GPIO_InitStruct);
// Start USB clock
__HAL_RCC_USB_CLK_ENABLE();
}
//--------------------------------------------------------------------+
// Board porting API
//--------------------------------------------------------------------+
void board_led_write(bool state)
{
HAL_GPIO_WritePin(LED_PORT, LED_PIN, state ? LED_STATE_ON : (1-LED_STATE_ON));
}
uint32_t board_button_read(void)
{
return BUTTON_STATE_ACTIVE == HAL_GPIO_ReadPin(BUTTON_PORT, BUTTON_PIN);
}
#if CFG_TUSB_OS == OPT_OS_NONE
volatile uint32_t system_ticks = 0;
void SysTick_Handler (void)
{
system_ticks++;
}
uint32_t board_millis(void)
{
return system_ticks;
}
#endif
void HardFault_Handler (void)
{
asm("bkpt");
}
#ifdef USE_FULL_ASSERT
/**
* @brief Reports the name of the source file and the source line number
* where the assert_param error has occurred.
* @param file: pointer to the source file name
* @param line: assert_param error line source number
* @retval None
*/
void assert_failed(char *file, uint32_t line)
{
/* USER CODE BEGIN 6 */
/* User can add his own implementation to report the file name and line number,
tex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */
/* USER CODE END 6 */
}
#endif /* USE_FULL_ASSERT */
// Required by __libc_init_array in startup code if we are compiling using
// -nostdlib/-nostartfiles.
void _init(void)
{
}

324
hw/bsp/stm32f070rbnucleo/stm32f0xx_hal_conf.h Normal file
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@@ -0,0 +1,324 @@
/**
******************************************************************************
* @file GPIO/GPIO_IOToggle/Inc/stm32f3xx_hal_conf.h
* @author MCD Application Team
* @brief HAL configuration file.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of STMicroelectronics nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32F0xx_HAL_CONF_H
#define __STM32F0xx_HAL_CONF_H
#ifdef __cplusplus
extern "C" {
#endif
/* Exported types ------------------------------------------------------------*/
/* Exported constants --------------------------------------------------------*/
/* ########################## Module Selection ############################## */
/**
* @brief This is the list of modules to be used in the HAL driver
*/
#define HAL_MODULE_ENABLED
/*#define HAL_ADC_MODULE_ENABLED */
/*#define HAL_CRYP_MODULE_ENABLED */
/*#define HAL_CAN_MODULE_ENABLED */
/*#define HAL_CEC_MODULE_ENABLED */
/*#define HAL_COMP_MODULE_ENABLED */
/*#define HAL_CRC_MODULE_ENABLED */
/*#define HAL_CRYP_MODULE_ENABLED */
/*#define HAL_TSC_MODULE_ENABLED */
/*#define HAL_DAC_MODULE_ENABLED */
/*#define HAL_I2S_MODULE_ENABLED */
/*#define HAL_IWDG_MODULE_ENABLED */
/*#define HAL_LCD_MODULE_ENABLED */
/*#define HAL_LPTIM_MODULE_ENABLED */
/*#define HAL_RNG_MODULE_ENABLED */
/*#define HAL_RTC_MODULE_ENABLED */
/*#define HAL_SPI_MODULE_ENABLED */
/*#define HAL_TIM_MODULE_ENABLED */
/*#define HAL_UART_MODULE_ENABLED */
#define HAL_USART_MODULE_ENABLED
/*#define HAL_IRDA_MODULE_ENABLED */
/*#define HAL_SMARTCARD_MODULE_ENABLED */
/*#define HAL_SMBUS_MODULE_ENABLED */
/*#define HAL_WWDG_MODULE_ENABLED */
#define HAL_PCD_MODULE_ENABLED
/*#define HAL_EXTI_MODULE_ENABLED */
#define HAL_CORTEX_MODULE_ENABLED
#define HAL_DMA_MODULE_ENABLED
#define HAL_FLASH_MODULE_ENABLED
#define HAL_GPIO_MODULE_ENABLED
#define HAL_PWR_MODULE_ENABLED
#define HAL_RCC_MODULE_ENABLED
#define HAL_I2C_MODULE_ENABLED
/* ########################## HSE/HSI Values adaptation ##################### */
/**
* @brief Adjust the value of External High Speed oscillator (HSE) used in your application.
* This value is used by the RCC HAL module to compute the system frequency
* (when HSE is used as system clock source, directly or through the PLL).
*/
#if !defined (HSE_VALUE)
#define HSE_VALUE ((uint32_t)8000000) /*!< Value of the External oscillator in Hz */
#endif /* HSE_VALUE */
/**
* @brief In the following line adjust the External High Speed oscillator (HSE) Startup
* Timeout value
*/
#if !defined (HSE_STARTUP_TIMEOUT)
#define HSE_STARTUP_TIMEOUT ((uint32_t)100) /*!< Time out for HSE start up, in ms */
#endif /* HSE_STARTUP_TIMEOUT */
/**
* @brief Internal High Speed oscillator (HSI) value.
* This value is used by the RCC HAL module to compute the system frequency
* (when HSI is used as system clock source, directly or through the PLL).
*/
#if !defined (HSI_VALUE)
#define HSI_VALUE ((uint32_t)8000000) /*!< Value of the Internal oscillator in Hz*/
#endif /* HSI_VALUE */
/**
* @brief In the following line adjust the Internal High Speed oscillator (HSI) Startup
* Timeout value
*/
#if !defined (HSI_STARTUP_TIMEOUT)
#define HSI_STARTUP_TIMEOUT ((uint32_t)5000) /*!< Time out for HSI start up */
#endif /* HSI_STARTUP_TIMEOUT */
/**
* @brief Internal High Speed oscillator for ADC (HSI14) value.
*/
#if !defined (HSI14_VALUE)
#define HSI14_VALUE ((uint32_t)14000000) /*!< Value of the Internal High Speed oscillator for ADC in Hz.
The real value may vary depending on the variations
in voltage and temperature. */
#endif /* HSI14_VALUE */
/**
* @brief Internal High Speed oscillator for USB (HSI48) value.
*/
#if !defined (HSI48_VALUE)
#define HSI48_VALUE ((uint32_t)48000000) /*!< Value of the Internal High Speed oscillator for USB in Hz.
The real value may vary depending on the variations
in voltage and temperature. */
#endif /* HSI48_VALUE */
/**
* @brief Internal Low Speed oscillator (LSI) value.
*/
#if !defined (LSI_VALUE)
#define LSI_VALUE ((uint32_t)40000)
#endif /* LSI_VALUE */ /*!< Value of the Internal Low Speed oscillator in Hz
The real value may vary depending on the variations
in voltage and temperature. */
/**
* @brief External Low Speed oscillator (LSI) value.
*/
#if !defined (LSE_VALUE)
#define LSE_VALUE ((uint32_t)32768) /*!< Value of the External Low Speed oscillator in Hz */
#endif /* LSE_VALUE */
#if !defined (LSE_STARTUP_TIMEOUT)
#define LSE_STARTUP_TIMEOUT ((uint32_t)5000) /*!< Time out for LSE start up, in ms */
#endif /* LSE_STARTUP_TIMEOUT */
/* Tip: To avoid modifying this file each time you need to use different HSE,
=== you can define the HSE value in your toolchain compiler preprocessor. */
/* ########################### System Configuration ######################### */
/**
* @brief This is the HAL system configuration section
*/
#define VDD_VALUE ((uint32_t)3300) /*!< Value of VDD in mv */
#define TICK_INT_PRIORITY ((uint32_t)0) /*!< tick interrupt priority (lowest by default) */
/* Warning: Must be set to higher priority for HAL_Delay() */
/* and HAL_GetTick() usage under interrupt context */
#define USE_RTOS 0
#define PREFETCH_ENABLE 1
#define INSTRUCTION_CACHE_ENABLE 0
#define DATA_CACHE_ENABLE 0
/* ########################## Assert Selection ############################## */
/**
* @brief Uncomment the line below to expanse the "assert_param" macro in the
* HAL drivers code
*/
#define USE_FULL_ASSERT 1U
/* ################## SPI peripheral configuration ########################## */
/* CRC FEATURE: Use to activate CRC feature inside HAL SPI Driver
* Activated: CRC code is present inside driver
* Deactivated: CRC code cleaned from driver
*/
#define USE_SPI_CRC 0U
/* Includes ------------------------------------------------------------------*/
/**
* @brief Include module's header file
*/
#ifdef HAL_RCC_MODULE_ENABLED
#include "stm32f0xx_hal_rcc.h"
#endif /* HAL_RCC_MODULE_ENABLED */
#ifdef HAL_EXTI_MODULE_ENABLED
#include "stm32f0xx_hal_exti.h"
#endif /* HAL_EXTI_MODULE_ENABLED */
#ifdef HAL_GPIO_MODULE_ENABLED
#include "stm32f0xx_hal_gpio.h"
#endif /* HAL_GPIO_MODULE_ENABLED */
#ifdef HAL_DMA_MODULE_ENABLED
#include "stm32f0xx_hal_dma.h"
#endif /* HAL_DMA_MODULE_ENABLED */
#ifdef HAL_CORTEX_MODULE_ENABLED
#include "stm32f0xx_hal_cortex.h"
#endif /* HAL_CORTEX_MODULE_ENABLED */
#ifdef HAL_ADC_MODULE_ENABLED
#include "stm32f0xx_hal_adc.h"
#endif /* HAL_ADC_MODULE_ENABLED */
#ifdef HAL_CAN_MODULE_ENABLED
#include "stm32f0xx_hal_can.h"
#endif /* HAL_CAN_MODULE_ENABLED */
#ifdef HAL_CEC_MODULE_ENABLED
#include "stm32f0xx_hal_cec.h"
#endif /* HAL_CEC_MODULE_ENABLED */
#ifdef HAL_COMP_MODULE_ENABLED
#include "stm32f0xx_hal_comp.h"
#endif /* HAL_COMP_MODULE_ENABLED */
#ifdef HAL_CRC_MODULE_ENABLED
#include "stm32f0xx_hal_crc.h"
#endif /* HAL_CRC_MODULE_ENABLED */
#ifdef HAL_DAC_MODULE_ENABLED
#include "stm32f0xx_hal_dac.h"
#endif /* HAL_DAC_MODULE_ENABLED */
#ifdef HAL_FLASH_MODULE_ENABLED
#include "stm32f0xx_hal_flash.h"
#endif /* HAL_FLASH_MODULE_ENABLED */
#ifdef HAL_I2C_MODULE_ENABLED
#include "stm32f0xx_hal_i2c.h"
#endif /* HAL_I2C_MODULE_ENABLED */
#ifdef HAL_I2S_MODULE_ENABLED
#include "stm32f0xx_hal_i2s.h"
#endif /* HAL_I2S_MODULE_ENABLED */
#ifdef HAL_IRDA_MODULE_ENABLED
#include "stm32f0xx_hal_irda.h"
#endif /* HAL_IRDA_MODULE_ENABLED */
#ifdef HAL_IWDG_MODULE_ENABLED
#include "stm32f0xx_hal_iwdg.h"
#endif /* HAL_IWDG_MODULE_ENABLED */
#ifdef HAL_PCD_MODULE_ENABLED
#include "stm32f0xx_hal_pcd.h"
#endif /* HAL_PCD_MODULE_ENABLED */
#ifdef HAL_PWR_MODULE_ENABLED
#include "stm32f0xx_hal_pwr.h"
#endif /* HAL_PWR_MODULE_ENABLED */
#ifdef HAL_RTC_MODULE_ENABLED
#include "stm32f0xx_hal_rtc.h"
#endif /* HAL_RTC_MODULE_ENABLED */
#ifdef HAL_SMARTCARD_MODULE_ENABLED
#include "stm32f0xx_hal_smartcard.h"
#endif /* HAL_SMARTCARD_MODULE_ENABLED */
#ifdef HAL_SMBUS_MODULE_ENABLED
#include "stm32f0xx_hal_smbus.h"
#endif /* HAL_SMBUS_MODULE_ENABLED */
#ifdef HAL_SPI_MODULE_ENABLED
#include "stm32f0xx_hal_spi.h"
#endif /* HAL_SPI_MODULE_ENABLED */
#ifdef HAL_TIM_MODULE_ENABLED
#include "stm32f0xx_hal_tim.h"
#endif /* HAL_TIM_MODULE_ENABLED */
#ifdef HAL_TSC_MODULE_ENABLED
#include "stm32f0xx_hal_tsc.h"
#endif /* HAL_TSC_MODULE_ENABLED */
#ifdef HAL_UART_MODULE_ENABLED
#include "stm32f0xx_hal_uart.h"
#endif /* HAL_UART_MODULE_ENABLED */
#ifdef HAL_USART_MODULE_ENABLED
#include "stm32f0xx_hal_usart.h"
#endif /* HAL_USART_MODULE_ENABLED */
#ifdef HAL_WWDG_MODULE_ENABLED
#include "stm32f0xx_hal_wwdg.h"
#endif /* HAL_WWDG_MODULE_ENABLED */
/* Exported macro ------------------------------------------------------------*/
#ifdef USE_FULL_ASSERT
/**
* @brief The assert_param macro is used for function's parameters check.
* @param expr: If expr is false, it calls assert_failed function
* which reports the name of the source file and the source
* line number of the call that failed.
* If expr is true, it returns no value.
* @retval None
*/
#define assert_param(expr) ((expr) ? (void)0U : assert_failed((char *)__FILE__, __LINE__))
/* Exported functions ------------------------------------------------------- */
void assert_failed(char* file, uint32_t line);
#else
#define assert_param(expr) ((void)0U)
#endif /* USE_FULL_ASSERT */
#ifdef __cplusplus
}
#endif
#endif /* __STM32F0xx_HAL_CONF_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

2
hw/bsp/stm32f303disco/board.mk
View File

@@ -33,7 +33,7 @@ INC += \
# For TinyUSB port source
VENDOR = st
CHIP_FAMILY = stm32f3
CHIP_FAMILY = stm32_fsdev
# For freeRTOS port source
FREERTOS_PORT = ARM_CM4F

4
hw/bsp/stm32f303disco/stm32f303disco.c
View File

@@ -86,6 +86,10 @@ void board_init(void)
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;
HAL_GPIO_Init(BUTTON_PORT, &GPIO_InitStruct);
// Start USB clock
__HAL_RCC_USB_CLK_ENABLE();
#if 0
RCC->AHB2ENR |= RCC_AHB2ENR_OTGFSEN;

4
src/common/tusb_common.h
View File

@@ -89,7 +89,7 @@ static inline uint32_t tu_u32(uint8_t b1, uint8_t b2, uint8_t b3, uint8_t b4)
static inline uint16_t tu_u16(uint8_t high, uint8_t low)
{
return (((uint16_t) high) << 8) + low;
return (uint16_t)((((uint16_t) high) << 8) + low);
}
static inline uint8_t tu_u16_high(uint16_t u16) { return (uint8_t) (((uint16_t) (u16 >> 8)) & 0x00ff); }
@@ -117,7 +117,7 @@ static inline uint32_t tu_align4k (uint32_t value) { return (value & 0xFFFFF000U
static inline uint32_t tu_offset4k(uint32_t value) { return (value & 0xFFFUL); }
//------------- Mathematics -------------//
static inline uint32_t tu_abs(int32_t value) { return (value < 0) ? (-value) : value; }
static inline uint32_t tu_abs(int32_t value) { return (uint32_t)((value < 0) ? (-value) : value); }
/// inclusive range checking
static inline bool tu_within(uint32_t lower, uint32_t value, uint32_t upper)

4
src/common/tusb_types.h
View File

@@ -442,12 +442,12 @@ static inline tusb_dir_t tu_edpt_dir(uint8_t addr)
// Get Endpoint number from address
static inline uint8_t tu_edpt_number(uint8_t addr)
{
return addr & (~TUSB_DIR_IN_MASK);
return (uint8_t)(addr & (~TUSB_DIR_IN_MASK));
}
static inline uint8_t tu_edpt_addr(uint8_t num, uint8_t dir)
{
return num | (dir ? TUSB_DIR_IN_MASK : 0);
return (uint8_t)(num | (dir ? TUSB_DIR_IN_MASK : 0));
}
//--------------------------------------------------------------------+

12
src/common/tusb_verify.h
View File

@@ -105,7 +105,7 @@
#define TU_VERIFY_1ARGS(_cond) TU_VERIFY_DEFINE(_cond, , false)
#define TU_VERIFY_2ARGS(_cond, _ret) TU_VERIFY_DEFINE(_cond, , _ret)
#define TU_VERIFY(...) GET_3RD_ARG(__VA_ARGS__, TU_VERIFY_2ARGS, TU_VERIFY_1ARGS)(__VA_ARGS__)
#define TU_VERIFY(...) GET_3RD_ARG(__VA_ARGS__, TU_VERIFY_2ARGS, TU_VERIFY_1ARGS, UNUSED)(__VA_ARGS__)
/*------------------------------------------------------------------*/
@@ -116,7 +116,7 @@
#define TU_VERIFY_HDLR_2ARGS(_cond, _handler) TU_VERIFY_DEFINE(_cond, _handler, false)
#define TU_VERIFY_HDLR_3ARGS(_cond, _handler, _ret) TU_VERIFY_DEFINE(_cond, _handler, _ret)
#define TU_VERIFY_HDLR(...) GET_4TH_ARG(__VA_ARGS__, TU_VERIFY_HDLR_3ARGS, TU_VERIFY_HDLR_2ARGS)(__VA_ARGS__)
#define TU_VERIFY_HDLR(...) GET_4TH_ARG(__VA_ARGS__, TU_VERIFY_HDLR_3ARGS, TU_VERIFY_HDLR_2ARGS,UNUSED)(__VA_ARGS__)
/*------------------------------------------------------------------*/
@@ -127,7 +127,7 @@
#define TU_VERIFY_ERR_1ARGS(_error) TU_VERIFY_ERR_DEF2(_error, )
#define TU_VERIFY_ERR_2ARGS(_error, _ret) TU_VERIFY_ERR_DEF3(_error, ,_ret)
#define TU_VERIFY_ERR(...) GET_3RD_ARG(__VA_ARGS__, TU_VERIFY_ERR_2ARGS, TU_VERIFY_ERR_1ARGS)(__VA_ARGS__)
#define TU_VERIFY_ERR(...) GET_3RD_ARG(__VA_ARGS__, TU_VERIFY_ERR_2ARGS, TU_VERIFY_ERR_1ARGS,UNUSED)(__VA_ARGS__)
/*------------------------------------------------------------------*/
/* TU_VERIFY STATUS WITH HANDLER
@@ -137,7 +137,7 @@
#define TU_VERIFY_ERR_HDLR_2ARGS(_error, _handler) TU_VERIFY_ERR_DEF2(_error, _handler)
#define TU_VERIFY_ERR_HDLR_3ARGS(_error, _handler, _ret) TU_VERIFY_ERR_DEF3(_error, _handler, _ret)
#define TU_VERIFY_ERR_HDLR(...) GET_4TH_ARG(__VA_ARGS__, TU_VERIFY_ERR_HDLR_3ARGS, TU_VERIFY_ERR_HDLR_2ARGS)(__VA_ARGS__)
#define TU_VERIFY_ERR_HDLR(...) GET_4TH_ARG(__VA_ARGS__, TU_VERIFY_ERR_HDLR_3ARGS, TU_VERIFY_ERR_HDLR_2ARGS,UNUSED)(__VA_ARGS__)
/*------------------------------------------------------------------*/
@@ -149,7 +149,7 @@
#define ASSERT_1ARGS(_cond) TU_VERIFY_DEFINE(_cond, _MESS_FAILED(); TU_BREAKPOINT(), false)
#define ASSERT_2ARGS(_cond, _ret) TU_VERIFY_DEFINE(_cond, _MESS_FAILED(); TU_BREAKPOINT(), _ret)
#define TU_ASSERT(...) GET_3RD_ARG(__VA_ARGS__, ASSERT_2ARGS, ASSERT_1ARGS)(__VA_ARGS__)
#define TU_ASSERT(...) GET_3RD_ARG(__VA_ARGS__, ASSERT_2ARGS, ASSERT_1ARGS,UNUSED)(__VA_ARGS__)
/*------------------------------------------------------------------*/
/* ASSERT Error
@@ -158,7 +158,7 @@
#define ASERT_ERR_1ARGS(_error) TU_VERIFY_ERR_DEF2(_error, TU_BREAKPOINT())
#define ASERT_ERR_2ARGS(_error, _ret) TU_VERIFY_ERR_DEF3(_error, TU_BREAKPOINT(), _ret)
#define TU_ASSERT_ERR(...) GET_3RD_ARG(__VA_ARGS__, ASERT_ERR_2ARGS, ASERT_ERR_1ARGS)(__VA_ARGS__)
#define TU_ASSERT_ERR(...) GET_3RD_ARG(__VA_ARGS__, ASERT_ERR_2ARGS, ASERT_ERR_1ARGS,UNUSED)(__VA_ARGS__)
/*------------------------------------------------------------------*/
/* ASSERT HDLR

4
src/device/usbd_control.c
View File

@@ -51,7 +51,7 @@ typedef struct
static usbd_control_xfer_t _control_state;
CFG_TUSB_MEM_SECTION CFG_TUSB_MEM_ALIGN uint8_t _usbd_ctrl_buf[CFG_TUD_ENDOINT0_SIZE];
CFG_TUSB_MEM_SECTION CFG_TUSB_MEM_ALIGN uint8_t _usbd_ctrl_buf[CFG_TUD_ENDPOINT0_SIZE];
void usbd_control_reset (uint8_t rhport)
{
@@ -68,7 +68,7 @@ bool tud_control_status(uint8_t rhport, tusb_control_request_t const * request)
// Each transaction is up to endpoint0's max packet size
static bool start_control_data_xact(uint8_t rhport)
{
uint16_t const xact_len = tu_min16(_control_state.total_len - _control_state.total_transferred, CFG_TUD_ENDOINT0_SIZE);
uint16_t const xact_len = tu_min16(_control_state.total_len - _control_state.total_transferred, CFG_TUD_ENDPOINT0_SIZE);
uint8_t ep_addr = EDPT_CTRL_OUT;

840
src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c Normal file
View File

@@ -0,0 +1,840 @@
/*
* The MIT License (MIT)
*
* Copyright (c) 2019 Nathan Conrad
*
* Portions:
* Copyright (c) 2016 STMicroelectronics
* Copyright (c) 2019 Ha Thach (tinyusb.org)
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*
* This file is part of the TinyUSB stack.
*/
/**********************************************
* This driver has been tested with the following MCUs:
*
*
* STM32F070RB
*
*
* It also should work with minimal changes for any ST MCU with an "USB A"/"PCD"/"HCD" peripheral. This
* covers:
*
* F04x, F072, F078, 070x6/B 1024 byte buffer
* F102, F103 512 byte buffer; no internal D+ pull-up (maybe many more changes?)
* F302xB/C, F303xB/C, F373 512 byte buffer; no internal D+ pull-up
* F302x6/8, F302xD/E2, F303xD/E 1024 byte buffer; no internal D+ pull-up
* L0x2, L0x3 1024 byte buffer
* L1 512 byte buffer
* L4x2, L4x3 1024 byte buffer
*
* Assumptions of the driver:
* - dcd_fs_irqHandler() is called by the USB interrupt handler
* - USB clock enabled before usb_init() is called; Perhaps use __HAL_RCC_USB_CLK_ENABLE();
* - You are not using CAN (it must share the packet buffer)
* - APB clock is >= 10 MHz
* - On some boards, series resistors are required, but not on others.
* - On some boards, D+ pull up resistor (1.5kohm) is required, but not on others.
* - You don't have long-running interrupts; some USB packets must be quickly responded to.
* - You have the ST CMSIS library linked into the project. HAL is not used.
*
* Current driver limitations (i.e., a list of features for you to add):
* - STALL handled, but not tested.
* - Does it work? No clue.
* - Only tested on F070RB; other models will have an #error during compilation
* - All EP BTABLE buffers are created as max 64 bytes.
* - Smaller can be requested, but it has to be an even number.
* - No isochronous endpoints
* - Endpoint index is the ID of the endpoint
* - This means that priority is given to endpoints with lower ID numbers
* - Code is mixing up EP IX with EP ID. Everywhere.
* - No way to close endpoints; Can a device be reconfigured without a reset?
* - Packet buffer memory is copied in the interrupt.
* - This is better for performance, but means interrupts are disabled for longer
* - DMA may be the best choice, but it could also be pushed to the USBD task.
* - No double-buffering
* - No DMA
* - No provision to control the D+ pull-up using GPIO on devices without an internal pull-up.
* - Minimal error handling
* - Perhaps error interrupts sholud be reported to the stack, or cause a device reset?
* - Assumes a single USB peripheral; I think that no hardware has multiple so this is fine.
* - Add a callback for enabling/disabling the D+ PU on devices without an internal PU.
* - F3 models use three separate interrupts. I think we could only use the LP interrupt for
* everything? However, the interrupts are configurable so the DisableInt and EnableInt
* below functions could be adjusting the wrong interrupts (if they had been reconfigured)
* - LPM is not used correctly, or at all?
*
* USB documentation and Reference implementations
* - STM32 Reference manuals
* - STM32 USB Hardware Guidelines AN4879
*
* - STM32 HAL (much of this driver is based on this)
* - libopencm3/lib/stm32/common/st_usbfs_core.c
* - Keil USB Device http://www.keil.com/pack/doc/mw/USB/html/group__usbd.html
*
* - YouTube OpenTechLab 011; https://www.youtube.com/watch?v=4FOkJLp_PUw
*
* Advantages over HAL driver:
* - Tiny (saves RAM, assumes a single USB peripheral)
*
* Notes:
* - The buffer table is allocated as endpoints are opened. The allocation is only
* cleared when the device is reset. This may be bad if the USB device needs
* to be reconfigured.
*/
#include "tusb_option.h"
#if (TUSB_OPT_DEVICE_ENABLED) && ( \
((CFG_TUSB_MCU) == OPT_MCU_STM32F0) || \
(((CFG_TUSB_MCU) == OPT_MCU_STM32F1) && ( \
defined(stm32f102x6) || defined(stm32f102xb) || \
defined(stm32f103x6) || defined(stm32f103xb) || \
defined(stm32f103xe) || defined(stm32f103xg) \
)) || \
((CFG_TUSB_MCU) == OPT_MCU_STM32F3) \
)
// In order to reduce the dependance on HAL, we undefine this.
// Some definitions are copied to our private include file.
#undef USE_HAL_DRIVER
#include "device/dcd.h"
#include "portable/st/stm32_fsdev/dcd_stm32_fsdev_pvt_st.h"
/*****************************************************
* Configuration
*****************************************************/
// HW supports max of 8 endpoints, but this can be reduced to save RAM
#ifndef MAX_EP_COUNT
# define MAX_EP_COUNT 8u
#endif
// If sharing with CAN, one can set this to be non-zero to give CAN space where it wants it
// Both of these MUST be a multiple of 2, and are in byte units.
#ifndef DCD_STM32_BTABLE_BASE
# define DCD_STM32_BTABLE_BASE 0u
#endif
#ifndef DCD_STM32_BTABLE_LENGTH
# define DCD_STM32_BTABLE_LENGTH (PMA_LENGTH - DCD_STM32_BTABLE_BASE)
#endif
/***************************************************
* Checks, structs, defines, function definitions, etc.
*/
#if ((MAX_EP_COUNT) > 8)
# error Only 8 endpoints supported on the hardware
#endif
#if (((DCD_STM32_BTABLE_BASE) + (DCD_STM32_BTABLE_LENGTH))>(PMA_LENGTH))
# error BTABLE does not fit in PMA RAM
#endif
#if (((DCD_STM32_BTABLE_BASE) % 8) != 0)
// per STM32F3 reference manual
#error BTABLE must be aligned to 8 bytes
#endif
// Max size of a USB FS packet is 64...
#define MAX_PACKET_SIZE 64
// One of these for every EP IN & OUT, uses a bit of RAM....
typedef struct
{
uint8_t * buffer;
uint16_t total_len;
uint16_t queued_len;
} xfer_ctl_t;
static xfer_ctl_t xfer_status[MAX_EP_COUNT][2];
#define XFER_CTL_BASE(_epnum, _dir) &xfer_status[_epnum][_dir]
static TU_ATTR_ALIGNED(4) uint32_t _setup_packet[6];
static uint8_t newDADDR; // Used to set the new device address during the CTR IRQ handler
// EP Buffers assigned from end of memory location, to minimize their chance of crashing
// into the stack.
static uint16_t ep_buf_ptr;
static void dcd_handle_bus_reset(void);
static void dcd_write_packet_memory(uint16_t dst, const void *__restrict src, size_t wNBytes);
static void dcd_read_packet_memory(void *__restrict dst, uint16_t src, size_t wNBytes);
static void dcd_transmit_packet(xfer_ctl_t * xfer, uint16_t ep_ix);
static uint16_t dcd_ep_ctr_handler(void);
void dcd_init (uint8_t rhport)
{
(void)rhport;
/* Clocks should already be enabled */
/* Use __HAL_RCC_USB_CLK_ENABLE(); to enable the clocks before calling this function */
/* The RM mentions to use a special ordering of PDWN and FRES, but this isn't done in HAL.
* Here, the RM is followed. */
for(uint32_t i = 0; i<200; i++) // should be a few us
{
asm("NOP");
}
// Perform USB peripheral reset
USB->CNTR = USB_CNTR_FRES | USB_CNTR_PDWN;
for(uint32_t i = 0; i<200; i++) // should be a few us
{
asm("NOP");
}
USB->CNTR &= ~(USB_CNTR_PDWN);// Remove powerdown
// Wait startup time, for F042 and F070, this is <= 1 us.
for(uint32_t i = 0; i<200; i++) // should be a few us
{
asm("NOP");
}
USB->CNTR = 0; // Enable USB
USB->BTABLE = DCD_STM32_BTABLE_BASE;
USB->ISTR &= ~(USB_ISTR_ALL_EVENTS); // Clear pending interrupts
// Clear all EPREG
for(uint16_t i=0; i<8; i++)
{
EPREG(0) = 0u;
}
// Initialize the BTABLE for EP0 at this point (though setting up the EP0R is unneeded)
// This is actually not necessary, but helps debugging to start with a blank RAM area
for(uint16_t i=0;i<(DCD_STM32_BTABLE_LENGTH>>1); i++)
{
pma[PMA_STRIDE*(DCD_STM32_BTABLE_BASE + i)] = 0u;
}
USB->CNTR |= USB_CNTR_RESETM | USB_CNTR_SOFM | USB_CNTR_CTRM | USB_CNTR_SUSPM | USB_CNTR_WKUPM;
dcd_handle_bus_reset();
// And finally enable pull-up, which may trigger the RESET IRQ if the host is connected.
// (if this MCU has an internal pullup)
#if defined(USB_BCDR_DPPU)
USB->BCDR |= USB_BCDR_DPPU;
#else
// FIXME: callback to the user to ask them to twiddle a GPIO to disable/enable D+???
#endif
}
// Enable device interrupt
void dcd_int_enable (uint8_t rhport)
{
(void)rhport;
#if defined(STM32F0)
NVIC_SetPriority(USB_IRQn, 0);
NVIC_EnableIRQ(USB_IRQn);
#elif defined(STM32F3)
NVIC_SetPriority(USB_HP_CAN_TX_IRQn, 0);
NVIC_SetPriority(USB_LP_CAN_RX0_IRQn, 0);
NVIC_SetPriority(USBWakeUp_IRQn, 0);
NVIC_EnableIRQ(USB_HP_CAN_TX_IRQn);
NVIC_EnableIRQ(USB_LP_CAN_RX0_IRQn);
NVIC_EnableIRQ(USBWakeUp_IRQn);
#endif
}
// Disable device interrupt
void dcd_int_disable(uint8_t rhport)
{
(void)rhport;
#if defined(STM32F0)
NVIC_DisableIRQ(USB_IRQn);
#elif defined(STM32F3)
NVIC_DisableIRQ(USB_HP_CAN_TX_IRQn);
NVIC_DisableIRQ(USB_LP_CAN_RX0_IRQn);
NVIC_DisableIRQ(USBWakeUp_IRQn);
#else
#error Unknown arch in USB driver
#endif
}
// Receive Set Address request, mcu port must also include status IN response
void dcd_set_address(uint8_t rhport, uint8_t dev_addr)
{
(void)rhport;
// We cannot immediatly change it; it must be queued to change after the STATUS packet is sent.
// (CTR handler will actually change the address once it sees that the transmission is complete)
newDADDR = dev_addr;
// Respond with status
dcd_edpt_xfer(rhport, tu_edpt_addr(0, TUSB_DIR_IN), NULL, 0);
}
// Receive Set Config request
void dcd_set_config (uint8_t rhport, uint8_t config_num)
{
(void) rhport;
(void) config_num;
// Nothing to do? Handled by stack.
}
void dcd_remote_wakeup(uint8_t rhport)
{
(void) rhport;
}
// I'm getting a weird warning about missing braces here that I don't
// know how to fix.
#if defined(__GNUC__) && (__GNUC__ >= 7)
# pragma GCC diagnostic push
# pragma GCC diagnostic ignored "-Wmissing-braces"
#endif
static const tusb_desc_endpoint_t ep0OUT_desc =
{
.wMaxPacketSize = CFG_TUD_ENDPOINT0_SIZE,
.bDescriptorType = TUSB_XFER_CONTROL,
.bEndpointAddress = 0x00
};
static const tusb_desc_endpoint_t ep0IN_desc =
{
.wMaxPacketSize = CFG_TUD_ENDPOINT0_SIZE,
.bDescriptorType = TUSB_XFER_CONTROL,
.bEndpointAddress = 0x80
};
#pragma GCC diagnostic pop
static void dcd_handle_bus_reset(void)
{
//__IO uint16_t * const epreg = &(EPREG(0));
USB->DADDR = 0u; // disable USB peripheral by clearing the EF flag
// Clear all EPREG (or maybe this is automatic? I'm not sure)
for(uint16_t i=0; i<8; i++)
{
EPREG(0) = 0u;
}
ep_buf_ptr = DCD_STM32_BTABLE_BASE + 8*MAX_EP_COUNT; // 8 bytes per endpoint (two TX and two RX words, each)
dcd_edpt_open (0, &ep0OUT_desc);
dcd_edpt_open (0, &ep0IN_desc);
newDADDR = 0;
USB->DADDR = USB_DADDR_EF; // Set enable flag, and leaving the device address as zero.
PCD_SET_EP_RX_STATUS(USB, 0, USB_EP_RX_VALID); // And start accepting SETUP on EP0
}
// FIXME: Defined to return uint16 so that ASSERT can be used, even though a return value is not needed.
static uint16_t dcd_ep_ctr_handler(void)
{
uint16_t count=0U;
uint8_t EPindex;
__IO uint16_t wIstr;
__IO uint16_t wEPVal = 0U;
// stack variables to pass to USBD
/* stay in loop while pending interrupts */
while (((wIstr = USB->ISTR) & USB_ISTR_CTR) != 0U)
{
/* extract highest priority endpoint index */
EPindex = (uint8_t)(wIstr & USB_ISTR_EP_ID);
if (EPindex == 0U)
{
/* Decode and service control endpoint interrupt */
/* DIR bit = origin of the interrupt */
if ((wIstr & USB_ISTR_DIR) == 0U)
{
/* DIR = 0 => IN int */
/* DIR = 0 implies that (EP_CTR_TX = 1) always */
PCD_CLEAR_TX_EP_CTR(USB, 0);
xfer_ctl_t * xfer = XFER_CTL_BASE(EPindex,TUSB_DIR_IN);
if((xfer->total_len == xfer->queued_len))
{
dcd_event_xfer_complete(0u, (uint8_t)(0x80 + EPindex), xfer->total_len, XFER_RESULT_SUCCESS, true);
if((newDADDR != 0) && ( xfer->total_len == 0U))
{
// Delayed setting of the DADDR after the 0-len DATA packet acking the request is sent.
USB->DADDR &= ~USB_DADDR_ADD;
USB->DADDR |= newDADDR;
newDADDR = 0;
}
if(xfer->total_len == 0) // Probably a status message?
{
PCD_CLEAR_RX_DTOG(USB,EPindex);
}
}
else
{
dcd_transmit_packet(xfer,EPindex);
}
}
else
{
/* DIR = 1 & CTR_RX => SETUP or OUT int */
/* DIR = 1 & (CTR_TX | CTR_RX) => 2 int pending */
xfer_ctl_t *xfer = XFER_CTL_BASE(EPindex,TUSB_DIR_OUT);
//ep = &hpcd->OUT_ep[0];
wEPVal = PCD_GET_ENDPOINT(USB, EPindex);
if ((wEPVal & USB_EP_SETUP) != 0U) // SETUP
{
// The setup_received function uses memcpy, so this must first copy the setup data into
// user memory, to allow for the 32-bit access that memcpy performs.
uint8_t userMemBuf[8];
/* Get SETUP Packet*/
count = PCD_GET_EP_RX_CNT(USB, EPindex);
//TU_ASSERT_ERR(count == 8);
dcd_read_packet_memory(userMemBuf, *PCD_EP_RX_ADDRESS_PTR(USB,EPindex), 8);
/* SETUP bit kept frozen while CTR_RX = 1*/
dcd_event_setup_received(0, (uint8_t*)userMemBuf, true);
PCD_CLEAR_RX_EP_CTR(USB, EPindex);
}
else if ((wEPVal & USB_EP_CTR_RX) != 0U) // OUT
{
PCD_CLEAR_RX_EP_CTR(USB, EPindex);
/* Get Control Data OUT Packet */
count = PCD_GET_EP_RX_CNT(USB,EPindex);
if (count != 0U)
{
dcd_read_packet_memory(xfer->buffer, *PCD_EP_RX_ADDRESS_PTR(USB,EPindex), count);
xfer->queued_len = (uint16_t)(xfer->queued_len + count);
}
/* Process Control Data OUT status Packet*/
if(EPindex == 0 && xfer->total_len == 0)
{
PCD_CLEAR_EP_KIND(USB,0); // Good, so allow non-zero length packets now.
}
dcd_event_xfer_complete(0, EPindex, xfer->total_len, XFER_RESULT_SUCCESS, true);
PCD_SET_EP_RX_CNT(USB, EPindex, CFG_TUD_ENDPOINT0_SIZE);
if(EPindex == 0 && xfer->total_len == 0)
{
PCD_SET_EP_RX_STATUS(USB, EPindex, USB_EP_RX_VALID);// Await next SETUP
}
}
}
}
else /* Decode and service non control endpoints interrupt */
{
/* process related endpoint register */
wEPVal = PCD_GET_ENDPOINT(USB, EPindex);
if ((wEPVal & USB_EP_CTR_RX) != 0U) // OUT
{
/* clear int flag */
PCD_CLEAR_RX_EP_CTR(USB, EPindex);
xfer_ctl_t * xfer = XFER_CTL_BASE(EPindex,TUSB_DIR_OUT);
//ep = &hpcd->OUT_ep[EPindex];
count = PCD_GET_EP_RX_CNT(USB, EPindex);
if (count != 0U)
{
dcd_read_packet_memory(&(xfer->buffer[xfer->queued_len]),
*PCD_EP_RX_ADDRESS_PTR(USB,EPindex), count);
}
/*multi-packet on the NON control OUT endpoint */
xfer->queued_len = (uint16_t)(xfer->queued_len + count);
if ((count < 64) || (xfer->queued_len == xfer->total_len))
{
/* RX COMPLETE */
dcd_event_xfer_complete(0, EPindex, xfer->queued_len, XFER_RESULT_SUCCESS, true);
// Though the host could still send, we don't know.
// Does the bulk pipe need to be reset to valid to allow for a ZLP?
}
else
{
uint16_t remaining = (uint16_t)(xfer->total_len - xfer->queued_len);
if(remaining >=64) {
PCD_SET_EP_RX_CNT(USB, EPindex,64);
} else {
PCD_SET_EP_RX_CNT(USB, EPindex,remaining);
}
PCD_SET_EP_RX_STATUS(USB, EPindex, USB_EP_RX_VALID);
}
} /* if((wEPVal & EP_CTR_RX) */
if ((wEPVal & USB_EP_CTR_TX) != 0U) // IN
{
/* clear int flag */
PCD_CLEAR_TX_EP_CTR(USB, EPindex);
xfer_ctl_t * xfer = XFER_CTL_BASE(EPindex,TUSB_DIR_IN);
if (xfer->queued_len != xfer->total_len) // data remaining in transfer?
{
dcd_transmit_packet(xfer, EPindex);
} else {
dcd_event_xfer_complete(0, (uint8_t)(0x80 + EPindex), xfer->total_len, XFER_RESULT_SUCCESS, true);
}
}
}
}
return 0;
}
void dcd_fs_irqHandler(void) {
uint16_t int_status = USB->ISTR;
// unused IRQs: (USB_ISTR_PMAOVR | USB_ISTR_ERR | USB_ISTR_WKUP | USB_ISTR_SUSP | USB_ISTR_ESOF | USB_ISTR_L1REQ )
if (int_status & USB_ISTR_CTR)
{
/* servicing of the endpoint correct transfer interrupt */
/* clear of the CTR flag into the sub */
dcd_ep_ctr_handler();
USB->ISTR &= ~USB_ISTR_CTR;
}
if(int_status & USB_ISTR_RESET) {
// USBRST is start of reset.
USB->ISTR &= ~USB_ISTR_RESET;
dcd_handle_bus_reset();
dcd_event_bus_signal(0, DCD_EVENT_BUS_RESET, true);
}
if (int_status & USB_ISTR_WKUP)
{
USB->CNTR &= ~USB_CNTR_LPMODE;
USB->CNTR &= ~USB_CNTR_FSUSP;
USB->ISTR &= ~USB_ISTR_WKUP;
}
if (int_status & USB_ISTR_SUSP)
{
/* Force low-power mode in the macrocell */
USB->CNTR |= USB_CNTR_FSUSP;
USB->CNTR |= USB_CNTR_LPMODE;
/* clear of the ISTR bit must be done after setting of CNTR_FSUSP */
USB->ISTR &= ~USB_ISTR_SUSP;
}
if(int_status & USB_ISTR_SOF) {
USB->ISTR &= ~USB_ISTR_SOF;
dcd_event_bus_signal(0, DCD_EVENT_SOF, true);
}
}
//--------------------------------------------------------------------+
// Endpoint API
//--------------------------------------------------------------------+
// The STM32F0 doesn't seem to like |= or &= to manipulate the EP#R registers,
// so I'm using the #define from HAL here, instead.
bool dcd_edpt_open (uint8_t rhport, tusb_desc_endpoint_t const * p_endpoint_desc)
{
(void)rhport;
uint8_t const epnum = tu_edpt_number(p_endpoint_desc->bEndpointAddress);
uint8_t const dir = tu_edpt_dir(p_endpoint_desc->bEndpointAddress);
// Isochronous not supported (yet), and some other driver assumptions.
TU_ASSERT(p_endpoint_desc->bmAttributes.xfer != TUSB_XFER_ISOCHRONOUS);
TU_ASSERT(p_endpoint_desc->wMaxPacketSize.size <= MAX_PACKET_SIZE);
TU_ASSERT(epnum < MAX_EP_COUNT);
TU_ASSERT((p_endpoint_desc->wMaxPacketSize.size %2) == 0);
// __IO uint16_t * const epreg = &(EPREG(epnum));
// Set type
switch(p_endpoint_desc->bmAttributes.xfer) {
case TUSB_XFER_CONTROL:
PCD_SET_EPTYPE(USB, epnum, USB_EP_CONTROL); break;
case TUSB_XFER_ISOCHRONOUS:
PCD_SET_EPTYPE(USB, epnum, USB_EP_ISOCHRONOUS); break;
case TUSB_XFER_BULK:
PCD_SET_EPTYPE(USB, epnum, USB_EP_BULK); break;
case TUSB_XFER_INTERRUPT:
PCD_SET_EPTYPE(USB, epnum, USB_EP_INTERRUPT); break;
default:
TU_ASSERT(false);
}
PCD_SET_EP_ADDRESS(USB, epnum, epnum);
PCD_CLEAR_EP_KIND(USB,0); // Be normal, for now, instead of only accepting zero-byte packets
if(dir == TUSB_DIR_IN)
{
*PCD_EP_TX_ADDRESS_PTR(USB, epnum) = ep_buf_ptr;
PCD_SET_EP_RX_CNT(USB, epnum, p_endpoint_desc->wMaxPacketSize.size);
PCD_CLEAR_TX_DTOG(USB, epnum);
PCD_SET_EP_TX_STATUS(USB,epnum,USB_EP_TX_NAK);
}
else
{
*PCD_EP_RX_ADDRESS_PTR(USB, epnum) = ep_buf_ptr;
PCD_SET_EP_RX_CNT(USB, epnum, p_endpoint_desc->wMaxPacketSize.size);
PCD_CLEAR_RX_DTOG(USB, epnum);
PCD_SET_EP_RX_STATUS(USB, epnum, USB_EP_RX_NAK);
}
ep_buf_ptr = (uint16_t)(ep_buf_ptr + p_endpoint_desc->wMaxPacketSize.size); // increment buffer pointer
return true;
}
// Currently, single-buffered, and only 64 bytes at a time (max)
static void dcd_transmit_packet(xfer_ctl_t * xfer, uint16_t ep_ix)
{
uint16_t len = (uint16_t)(xfer->total_len - xfer->queued_len);
if(len > 64u) // max packet size for FS transfer
{
len = 64u;
}
dcd_write_packet_memory(*PCD_EP_TX_ADDRESS_PTR(USB,ep_ix), &(xfer->buffer[xfer->queued_len]), len);
xfer->queued_len = (uint16_t)(xfer->queued_len + len);
PCD_SET_EP_TX_CNT(USB,ep_ix,len);
PCD_SET_EP_TX_STATUS(USB, ep_ix, USB_EP_TX_VALID);
}
bool dcd_edpt_xfer (uint8_t rhport, uint8_t ep_addr, uint8_t * buffer, uint16_t total_bytes)
{
(void) rhport;
uint8_t const epnum = tu_edpt_number(ep_addr);
uint8_t const dir = tu_edpt_dir(ep_addr);
xfer_ctl_t * xfer = XFER_CTL_BASE(epnum,dir);
xfer->buffer = buffer;
xfer->total_len = total_bytes;
xfer->queued_len = 0;
if ( dir == TUSB_DIR_OUT )
{
// A setup token can occur immediately after an OUT STATUS packet so make sure we have a valid
// buffer for the control endpoint.
if (epnum == 0 && buffer == NULL)
{
xfer->buffer = (uint8_t*)_setup_packet;
PCD_SET_EP_KIND(USB,0); // Expect a zero-byte INPUT
}
if(total_bytes > 64)
{
PCD_SET_EP_RX_CNT(USB,epnum,64);
} else {
PCD_SET_EP_RX_CNT(USB,epnum,total_bytes);
}
PCD_SET_EP_RX_STATUS(USB, epnum, USB_EP_RX_VALID);
}
else // IN
{
dcd_transmit_packet(xfer,epnum);
}
return true;
}
void dcd_edpt_stall (uint8_t rhport, uint8_t ep_addr)
{
(void)rhport;
if (ep_addr == 0) { // CTRL EP0 (OUT for setup)
PCD_SET_EP_TX_STATUS(USB,ep_addr, USB_EP_TX_STALL);
}
if (ep_addr & 0x80) { // IN
ep_addr &= 0x7F;
PCD_SET_EP_TX_STATUS(USB,ep_addr, USB_EP_TX_STALL);
} else { // OUT
PCD_SET_EP_RX_STATUS(USB,ep_addr, USB_EP_RX_STALL);
}
}
void dcd_edpt_clear_stall (uint8_t rhport, uint8_t ep_addr)
{
(void)rhport;
if (ep_addr == 0)
{
PCD_SET_EP_TX_STATUS(USB,ep_addr, USB_EP_TX_NAK);
}
if (ep_addr & 0x80)
{ // IN
ep_addr &= 0x7F;
PCD_SET_EP_TX_STATUS(USB,ep_addr, USB_EP_TX_NAK);
/* Reset to DATA0 if clearing stall condition. */
PCD_CLEAR_TX_DTOG(USB,ep_addr);
}
else
{ // OUT
/* Reset to DATA0 if clearing stall condition. */
PCD_CLEAR_RX_DTOG(USB,ep_addr);
PCD_SET_EP_RX_STATUS(USB,ep_addr, USB_EP_RX_VALID);
}
}
// Packet buffer access can only be 8- or 16-bit.
/**
* @brief Copy a buffer from user memory area to packet memory area (PMA).
* This uses byte-access for user memory (so support non-aligned buffers)
* and 16-bit access for packet memory.
* @param dst, byte address in PMA; must be 16-bit aligned
* @param src pointer to user memory area.
* @param wPMABufAddr address into PMA.
* @param wNBytes no. of bytes to be copied.
* @retval None
*/
static void dcd_write_packet_memory(uint16_t dst, const void *__restrict src, size_t wNBytes)
{
uint32_t n = ((uint32_t)((uint32_t)wNBytes + 1U)) >> 1U;
uint32_t i;
uint16_t temp1, temp2;
const uint8_t * srcVal;
#ifdef DEBUG
if(((dst%2) != 0) ||
(dst < DCD_STM32_BTABLE_BASE) ||
dst >= (DCD_STM32_BTABLE_BASE + DCD_STM32_BTABLE_LENGTH))
while(1) TU_BREAKPOINT();
#endif
// The GCC optimizer will combine access to 32-bit sizes if we let it. Force
// it volatile so that it won't do that.
__IO uint16_t *pdwVal;
srcVal = src;
pdwVal = &pma[PMA_STRIDE*(dst>>1)];
for (i = n; i != 0; i--)
{
temp1 = (uint16_t) *srcVal;
srcVal++;
temp2 = temp1 | ((uint16_t)((uint16_t) ((*srcVal) << 8U))) ;
*pdwVal = temp2;
pdwVal += PMA_STRIDE;
srcVal++;
}
}
/**
* @brief Copy a buffer from user memory area to packet memory area (PMA).
* Uses byte-access of system memory and 16-bit access of packet memory
* @param wNBytes no. of bytes to be copied.
* @retval None
*/
static void dcd_read_packet_memory(void *__restrict dst, uint16_t src, size_t wNBytes)
{
uint32_t n = (uint32_t)wNBytes >> 1U;
uint32_t i;
// The GCC optimizer will combine access to 32-bit sizes if we let it. Force
// it volatile so that it won't do that.
__IO const uint16_t *pdwVal;
uint32_t temp;
#ifdef DEBUG
if((src%2) != 0 ||
(src < DCD_STM32_BTABLE_BASE) ||
src >= (DCD_STM32_BTABLE_BASE + DCD_STM32_BTABLE_LENGTH))
while(1) TU_BREAKPOINT();
#endif
pdwVal = &pma[PMA_STRIDE*(src>>1)];
uint8_t *dstVal = (uint8_t*)dst;
for (i = n; i != 0U; i--)
{
temp = *pdwVal;
pdwVal += PMA_STRIDE;
*dstVal++ = ((temp >> 0) & 0xFF);
*dstVal++ = ((temp >> 8) & 0xFF);
}
if (wNBytes % 2)
{
temp = *pdwVal;
pdwVal += PMA_STRIDE;
*dstVal++ = ((temp >> 0) & 0xFF);
}
}
// Interrupt handlers
#if (CFG_TUSB_MCU) == (OPT_MCU_STM32F0)
void USB_IRQHandler(void)
{
dcd_fs_irqHandler();
}
#elif (CFG_TUSB_MCU) == (OPT_MCU_STM32F1)
void USB_HP_IRQHandler(void)
{
dcd_fs_irqHandler();
}
void USB_LP_IRQHandler(void)
{
dcd_fs_irqHandler();
}
void USBWakeUp_IRQHandler(void)
{
dcd_fs_irqHandler();
}
#elif (CFG_TUSB_MCU) == (OPT_MCU_STM32F3)
// USB defaults to using interrupts 19, 20, and 42 (based on SYSCFG_CFGR1.USB_IT_RMP)
// FIXME: Do all three need to be handled, or just the LP one?
// USB high-priority interrupt (Channel 19): Triggered only by a correct
// transfer event for isochronous and double-buffer bulk transfer to reach
// the highest possible transfer rate.
void USB_HP_CAN_TX_IRQHandler(void)
{
dcd_fs_irqHandler();
}
// USB low-priority interrupt (Channel 20): Triggered by all USB events
// (Correct transfer, USB reset, etc.). The firmware has to check the
// interrupt source before serving the interrupt.
void USB_LP_CAN_RX0_IRQHandler(void)
{
dcd_fs_irqHandler();
}
// USB wakeup interrupt (Channel 42): Triggered by the wakeup event from the USB
// Suspend mode.
void USBWakeUp_IRQHandler(void)
{
dcd_fs_irqHandler();
}
#else
#error Which IRQ handler do you need?
#endif
#endif

288
src/portable/st/stm32_fsdev/dcd_stm32_fsdev_pvt_st.h Normal file
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@@ -0,0 +1,288 @@
/**
******************************************************************************
* @file dcd_stm32f0_pvt_st.h
* @brief DCD utilities from ST code
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
* <h2><center>&copy; parts COPYRIGHT(c) N Conrad</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of STMicroelectronics nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
**********/
// This file contains source copied from ST's HAL, and thus should have their copyright statement.
// PMA_LENGTH is PMA buffer size in bytes.
// On 512-byte devices, access with a stride of two words (use every other 16-bit address)
// On 1024-byte devices, access with a stride of one word (use every 16-bit address)
#ifndef PORTABLE_ST_STM32F0_DCD_STM32F0_FSDEV_PVT_ST_H_
#define PORTABLE_ST_STM32F0_DCD_STM32F0_FSDEV_PVT_ST_H_
#if defined(STM32F042x6) | \
defined(STM32F070x6) | defined(STM32F070xB) | \
defined(STM32F072xB) | \
defined(STM32F078xx)
#include "stm32f0xx.h"
#define PMA_LENGTH 1024
// F0x2 models are crystal-less
// All have internal D+ pull-up
// 070RB: 2 x 16 bits/word memory LPM Support, BCD Support
// PMA dedicated to USB (no sharing with CAN)
#elif defined(STM32F102x6) | defined(STM32F102x6) | \
defined(STM32F103x6) | defined(STM32F103xB) | \
defined(STM32F103xE) | defined(STM32F103xB)
#include "stm32f1xx.h"
#define PMA_LENGTH 512u
// NO internal Pull-ups
// *B, and *C: 2 x 16 bits/word
#error The F102/F103 driver is expected not to work, but it might? Try it?
#elif defined(STM32F302xB) | defined(STM32F302xC) | \
defined(STM32F303xB) | defined(STM32F303xC) | \
defined(STM32F373xC)
#include "stm32f3xx.h"
#define PMA_LENGTH 512u
// NO internal Pull-ups
// *B, and *C: 1 x 16 bits/word
// PMA dedicated to USB (no sharing with CAN)
#elif defined(STM32F302x6) | defined(STM32F302x8) | \
defined(STM32F302xD) | defined(STM32F302xE) | \
defined(STM32F303xD) | defined(STM32F303xE) | \
#include "stm32f3xx.h"
#define PMA_LENGTH 1024u
// NO internal Pull-ups
// *6, *8, *D, and *E: 2 x 16 bits/word LPM Support
// When CAN clock is enabled, USB can use first 768 bytes ONLY.
#else
#error You are using an untested or unimplemented STM32 variant. Please update the driver.
// This includes L0x2, L0x3, L1x0, L1x1, L1x2, L4x2 and L4x3, G1x1, G1x3, and G1x4
#endif
// For purposes of accessing the packet
#if ((PMA_LENGTH) == 512u)
# define PMA_STRIDE (2u)
#elif ((PMA_LENGTH) == 1024u)
# define PMA_STRIDE (1u)
#endif
// And for type-safety create a new macro for the volatile address of PMAADDR
// The compiler should warn us if we cast it to a non-volatile type?
// Volatile is also needed to prevent the optimizer from changing access to 32-bit (as 32-bit access is forbidden)
static __IO uint16_t * const pma = (__IO uint16_t*)USB_PMAADDR;
/* SetENDPOINT */
#define PCD_SET_ENDPOINT(USBx, bEpNum,wRegValue) (*((__IO uint16_t *)(((uint32_t)(&(USBx)->EP0R + (bEpNum) * 2U))))= (uint16_t)(wRegValue))
/* GetENDPOINT */
#define PCD_GET_ENDPOINT(USBx, bEpNum) (*((__IO uint16_t *)(((uint32_t)(&(USBx)->EP0R + (bEpNum) * 2U)))))
#define PCD_SET_EPTYPE(USBx, bEpNum,wType) (PCD_SET_ENDPOINT((USBx), (bEpNum),\
(((((uint32_t)(PCD_GET_ENDPOINT((USBx), (bEpNum)))) & ((uint32_t)(USB_EP_T_MASK))) | ((uint32_t)(wType))) | USB_EP_CTR_RX | USB_EP_CTR_TX)))
#define PCD_GET_EPTYPE(USBx, bEpNum) (((uint16_t)(PCD_GET_ENDPOINT((USBx), (bEpNum)))) & USB_EP_T_FIELD)
/**
* @brief Clears bit CTR_RX / CTR_TX in the endpoint register.
* @param USBx USB peripheral instance register address.
* @param bEpNum Endpoint Number.
* @retval None
*/
#define PCD_CLEAR_RX_EP_CTR(USBx, bEpNum) (PCD_SET_ENDPOINT((USBx), (bEpNum),\
PCD_GET_ENDPOINT((USBx), (bEpNum)) & 0x7FFFU & USB_EPREG_MASK))
#define PCD_CLEAR_TX_EP_CTR(USBx, bEpNum) (PCD_SET_ENDPOINT((USBx), (bEpNum),\
PCD_GET_ENDPOINT((USBx), (bEpNum)) & 0xFF7FU & USB_EPREG_MASK))
/**
* @brief gets counter of the tx buffer.
* @param USBx USB peripheral instance register address.
* @param bEpNum Endpoint Number.
* @retval Counter value
*/
#define PCD_GET_EP_TX_CNT(USBx, bEpNum)((uint16_t)(*PCD_EP_TX_CNT_PTR((USBx), (bEpNum))) & 0x3ffU)
#define PCD_GET_EP_RX_CNT(USBx, bEpNum)((uint16_t)(*PCD_EP_RX_CNT_PTR((USBx), (bEpNum))) & 0x3ffU)
/**
* @brief Sets counter of rx buffer with no. of blocks.
* @param dwReg Register
* @param wCount Counter.
* @param wNBlocks no. of Blocks.
* @retval None
*/
#define PCD_CALC_BLK32(dwReg,wCount,wNBlocks) {\
(wNBlocks) = (uint32_t)((wCount) >> 5U);\
if(((wCount) & 0x1fU) == 0U)\
{ \
(wNBlocks)--;\
} \
*pdwReg = (uint16_t)((uint16_t)((wNBlocks) << 10U) | (uint16_t)0x8000U); \
}/* PCD_CALC_BLK32 */
#define PCD_CALC_BLK2(dwReg,wCount,wNBlocks) {\
(wNBlocks) = (uint32_t)((wCount) >> 1U); \
if(((wCount) & 0x1U) != 0U)\
{ \
(wNBlocks)++;\
} \
*pdwReg = (uint16_t)((wNBlocks) << 10U);\
}/* PCD_CALC_BLK2 */
#define PCD_SET_EP_CNT_RX_REG(dwReg,wCount) {\
uint32_t wNBlocks;\
if((wCount) > 62U) \
{ \
PCD_CALC_BLK32((dwReg),(wCount),wNBlocks) \
} \
else \
{ \
PCD_CALC_BLK2((dwReg),(wCount),wNBlocks) \
} \
}/* PCD_SET_EP_CNT_RX_REG */
/**
* @brief Sets address in an endpoint register.
* @param USBx USB peripheral instance register address.
* @param bEpNum Endpoint Number.
* @param bAddr Address.
* @retval None
*/
#define PCD_SET_EP_ADDRESS(USBx, bEpNum,bAddr) PCD_SET_ENDPOINT((USBx), (bEpNum),\
USB_EP_CTR_RX|USB_EP_CTR_TX|(((uint32_t)(PCD_GET_ENDPOINT((USBx), (bEpNum)))) & USB_EPREG_MASK) | (bAddr))
#define PCD_BTABLE_WORD_PTR(USBx,x) (&(pma[PMA_STRIDE*((((USBx)->BTABLE)>>1) + x)]))
// Pointers to the PMA table entries (using the ARM address space)
#define PCD_EP_TX_ADDRESS_PTR(USBx, bEpNum) (PCD_BTABLE_WORD_PTR(USBx,(bEpNum)*4u + 0u))
#define PCD_EP_TX_CNT_PTR(USBx, bEpNum) (PCD_BTABLE_WORD_PTR(USBx,(bEpNum)*4u + 1u))
#define PCD_EP_RX_ADDRESS_PTR(USBx, bEpNum) (PCD_BTABLE_WORD_PTR(USBx,(bEpNum)*4u + 2u))
#define PCD_EP_RX_CNT_PTR(USBx, bEpNum) (PCD_BTABLE_WORD_PTR(USBx,(bEpNum)*4u + 3u))
#define PCD_SET_EP_TX_CNT(USBx, bEpNum,wCount) (*PCD_EP_TX_CNT_PTR((USBx), (bEpNum)) = (wCount))
#define PCD_SET_EP_RX_CNT(USBx, bEpNum,wCount) do {\
__IO uint16_t *pdwReg =PCD_EP_RX_CNT_PTR((USBx),(bEpNum)); \
PCD_SET_EP_CNT_RX_REG((pdwReg), (wCount))\
} while(0)
/**
* @brief sets the status for tx transfer (bits STAT_TX[1:0]).
* @param USBx USB peripheral instance register address.
* @param bEpNum Endpoint Number.
* @param wState new state
* @retval None
*/
#define PCD_SET_EP_TX_STATUS(USBx, bEpNum, wState) { register uint16_t _wRegVal;\
\
_wRegVal = (uint32_t) (((uint32_t)(PCD_GET_ENDPOINT((USBx), (bEpNum)))) & USB_EPTX_DTOGMASK);\
/* toggle first bit ? */ \
if((USB_EPTX_DTOG1 & (wState))!= 0U)\
{ \
_wRegVal ^=(uint16_t) USB_EPTX_DTOG1; \
} \
/* toggle second bit ? */ \
if((USB_EPTX_DTOG2 & ((uint32_t)(wState)))!= 0U) \
{ \
_wRegVal ^=(uint16_t) USB_EPTX_DTOG2; \
} \
PCD_SET_ENDPOINT((USBx), (bEpNum), (((uint32_t)(_wRegVal)) | USB_EP_CTR_RX|USB_EP_CTR_TX));\
} /* PCD_SET_EP_TX_STATUS */
/**
* @brief sets the status for rx transfer (bits STAT_TX[1:0])
* @param USBx USB peripheral instance register address.
* @param bEpNum Endpoint Number.
* @param wState new state
* @retval None
*/
#define PCD_SET_EP_RX_STATUS(USBx, bEpNum,wState) {\
register uint16_t _wRegVal; \
\
_wRegVal = (uint32_t) (((uint32_t)(PCD_GET_ENDPOINT((USBx), (bEpNum)))) & USB_EPRX_DTOGMASK);\
/* toggle first bit ? */ \
if((USB_EPRX_DTOG1 & (wState))!= 0U) \
{ \
_wRegVal ^= (uint16_t) USB_EPRX_DTOG1; \
} \
/* toggle second bit ? */ \
if((USB_EPRX_DTOG2 & ((uint32_t)(wState)))!= 0U) \
{ \
_wRegVal ^= (uint16_t) USB_EPRX_DTOG2; \
} \
PCD_SET_ENDPOINT((USBx), (bEpNum), (((uint32_t)(_wRegVal)) | USB_EP_CTR_RX|USB_EP_CTR_TX)); \
} /* PCD_SET_EP_RX_STATUS */
/**
* @brief Toggles DTOG_RX / DTOG_TX bit in the endpoint register.
* @param USBx USB peripheral instance register address.
* @param bEpNum Endpoint Number.
* @retval None
*/
#define PCD_RX_DTOG(USBx, bEpNum) (PCD_SET_ENDPOINT((USBx), (bEpNum), \
USB_EP_CTR_RX|USB_EP_CTR_TX|USB_EP_DTOG_RX | (((uint32_t)(PCD_GET_ENDPOINT((USBx), (bEpNum)))) & USB_EPREG_MASK)))
#define PCD_TX_DTOG(USBx, bEpNum) (PCD_SET_ENDPOINT((USBx), (bEpNum), \
USB_EP_CTR_RX|USB_EP_CTR_TX|USB_EP_DTOG_TX | (((uint32_t)(PCD_GET_ENDPOINT((USBx), (bEpNum)))) & USB_EPREG_MASK)))
/**
* @brief Clears DTOG_RX / DTOG_TX bit in the endpoint register.
* @param USBx USB peripheral instance register address.
* @param bEpNum Endpoint Number.
* @retval None
*/
#define PCD_CLEAR_RX_DTOG(USBx, bEpNum) if((((uint32_t)(PCD_GET_ENDPOINT((USBx), (bEpNum)))) & USB_EP_DTOG_RX) != 0)\
{ \
PCD_RX_DTOG((USBx),(bEpNum));\
}
#define PCD_CLEAR_TX_DTOG(USBx, bEpNum) if((((uint32_t)(PCD_GET_ENDPOINT((USBx), (bEpNum)))) & USB_EP_DTOG_TX) != 0)\
{\
PCD_TX_DTOG((USBx),(bEpNum));\
}
/**
* @brief set & clear EP_KIND bit.
* @param USBx USB peripheral instance register address.
* @param bEpNum Endpoint Number.
* @retval None
*/
#define PCD_SET_EP_KIND(USBx, bEpNum) (PCD_SET_ENDPOINT((USBx), (bEpNum), \
(USB_EP_CTR_RX|USB_EP_CTR_TX|((((uint32_t)(PCD_GET_ENDPOINT((USBx), (bEpNum)))) | USB_EP_KIND) & USB_EPREG_MASK))))
#define PCD_CLEAR_EP_KIND(USBx, bEpNum) (PCD_SET_ENDPOINT((USBx), (bEpNum), \
(USB_EP_CTR_RX|USB_EP_CTR_TX|((((uint32_t)(PCD_GET_ENDPOINT((USBx), (bEpNum)))) & USB_EPKIND_MASK)))))
#define EPREG(n) (((__IO uint16_t*)USB_BASE)[n*2])
// This checks if the device has "LPM"
#if defined(USB_ISTR_L1REQ)
#define USB_ISTR_L1REQ_FORCED (USB_ISTR_L1REQ)
#else
#define USB_ISTR_L1REQ_FORCED ((uint16_t)0x0000U)
#endif
#define USB_ISTR_ALL_EVENTS (USB_ISTR_PMAOVR | USB_ISTR_ERR | USB_ISTR_WKUP | USB_ISTR_SUSP | \
USB_ISTR_RESET | USB_ISTR_SOF | USB_ISTR_ESOF | USB_ISTR_L1REQ_FORCED )
#endif /* PORTABLE_ST_STM32F0_DCD_STM32F0_FSDEV_PVT_ST_H_ */

85
src/portable/st/stm32f3/dcd_stm32f3.c
View File

@@ -1,85 +0,0 @@
/*
* The MIT License (MIT)
*
* Copyright (c) 2019 Ha Thach (tinyusb.org)
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*
* This file is part of the TinyUSB stack.
*/
#include "tusb_option.h"
#if TUSB_OPT_DEVICE_ENABLED && CFG_TUSB_MCU == OPT_MCU_STM32F3
#include "device/dcd.h"
#include "stm32f3xx.h"
//--------------------------------------------------------------------+
// MACRO TYPEDEF CONSTANT ENUM DECLARATION
//--------------------------------------------------------------------+
void dcd_init (uint8_t rhport)
{
}
// Enable device interrupt
void dcd_int_enable (uint8_t rhport)
{}
// Disable device interrupt
void dcd_int_disable(uint8_t rhport)
{}
// Receive Set Address request, mcu port must also include status IN response
void dcd_set_address(uint8_t rhport, uint8_t dev_addr)
{}
// Receive Set Config request
void dcd_set_config (uint8_t rhport, uint8_t config_num)
{}
void dcd_remote_wakeup(uint8_t rhport)
{
(void) rhport;
}
//--------------------------------------------------------------------+
// Endpoint API
//--------------------------------------------------------------------+
bool dcd_edpt_open (uint8_t rhport, tusb_desc_endpoint_t const * p_endpoint_desc)
{
return false;
}
bool dcd_edpt_xfer (uint8_t rhport, uint8_t ep_addr, uint8_t * buffer, uint16_t total_bytes)
{
return false;
}
void dcd_edpt_stall (uint8_t rhport, uint8_t ep_addr)
{
}
void dcd_edpt_clear_stall (uint8_t rhport, uint8_t ep_addr)
{
}
#endif

12
src/tusb_option.h
View File

@@ -51,9 +51,13 @@
#define OPT_MCU_SAMD21 200 ///< MicroChip SAMD21
#define OPT_MCU_SAMD51 201 ///< MicroChip SAMD51
// ST Synopsis OTG devices
#define OPT_MCU_STM32F4 300 ///< ST STM32F4
#define OPT_MCU_STM32F3 301 ///< ST STM32F3
#define OPT_MCU_STM32F3 301 ///< ST STM32F0x0
#define OPT_MCU_STM32H7 302 ///< ST STM32H7
#define OPT_MCU_STM32F0 303 ///< ST STM32F0
#define OPT_MCU_STM32F1 304 ///< ST STM32F1
/** @} */
@@ -145,8 +149,8 @@
// DEVICE OPTIONS
//--------------------------------------------------------------------
#ifndef CFG_TUD_ENDOINT0_SIZE
#define CFG_TUD_ENDOINT0_SIZE 64
#ifndef CFG_TUD_ENDPOINT0_SIZE
#define CFG_TUD_ENDPOINT0_SIZE 64
#endif
#ifndef CFG_TUD_CDC
@@ -198,7 +202,7 @@
//------------------------------------------------------------------
// Configuration Validation
//------------------------------------------------------------------
#if CFG_TUD_ENDOINT0_SIZE > 64
#if CFG_TUD_ENDPOINT0_SIZE > 64
#error Control Endpoint Max Packet Size cannot be larger than 64
#endif