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fix warning with lpcopen

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This commit is contained in:
hathach
2018-12-07 13:22:12 +07:00
parent 89820a36a1
commit f769ecddaf
35 changed files with 58 additions and 28 deletions
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1
hw/mcu/nxp/lpc_chip_18xx/inc/ccan_18xx_43xx.h
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@@ -451,6 +451,7 @@ STATIC INLINE void Chip_CCAN_ClearMsgIntPend(LPC_CCAN_T *pCCAN,
uint8_t msgNum,
CCAN_TRANSFER_DIR_T dir)
{
(void) dir;
Chip_CCAN_TransferMsgObject(pCCAN, IFSel, CCAN_IF_CMDMSK_RD | CCAN_IF_CMDMSK_R_CLRINTPND, msgNum);
}

2
hw/mcu/nxp/lpc_chip_18xx/inc/enet_18xx_43xx.h
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@@ -582,6 +582,7 @@ STATIC INLINE void Chip_ENET_RXDisable(LPC_ENET_T *pENET)
*/
STATIC INLINE void Chip_ENET_RMIIEnable(LPC_ENET_T *pENET)
{
(void) pENET;
LPC_CREG->CREG6 |= 0x4;
}
@@ -595,6 +596,7 @@ STATIC INLINE void Chip_ENET_RMIIEnable(LPC_ENET_T *pENET)
*/
STATIC INLINE void Chip_ENET_MIIEnable(LPC_ENET_T *pENET)
{
(void) pENET;
LPC_CREG->CREG6 &= ~0x7;
}

4
hw/mcu/nxp/lpc_chip_18xx/inc/lpc_types.h
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@@ -88,10 +88,10 @@ typedef enum {
} TRANSFER_BLOCK_T;
/** Pointer to Function returning Void (any number of parameters) */
typedef void (*PFV)();
// typedef void (*PFV)();
/** Pointer to Function returning int32_t (any number of parameters) */
typedef int32_t (*PFI)();
// typedef int32_t (*PFI)();
/**
* @}

4
hw/mcu/nxp/lpc_chip_18xx/inc/pinint_18xx_43xx.h
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@@ -77,14 +77,14 @@ typedef struct { /*!< PIN_INT Structure */
* @return Nothing
* @note This function should be used after the Chip_GPIO_Init() function.
*/
STATIC INLINE void Chip_PININT_Init(LPC_PIN_INT_T *pPININT) {}
STATIC INLINE void Chip_PININT_Init(LPC_PIN_INT_T *pPININT) { (void) pPININT; }
/**
* @brief De-Initialize Pin interrupt block
* @param pPININT : The base address of Pin interrupt block
* @return Nothing
*/
STATIC INLINE void Chip_PININT_DeInit(LPC_PIN_INT_T *pPININT) {}
STATIC INLINE void Chip_PININT_DeInit(LPC_PIN_INT_T *pPININT) { (void) pPININT; }
/**
* @brief Configure the pins as edge sensitive in Pin interrupt block

1
hw/mcu/nxp/lpc_chip_18xx/src/clock_18xx_43xx.c
View File

@@ -194,6 +194,7 @@ static uint32_t Chip_Clock_TestMainPLLMultiplier(uint32_t InputHz, uint32_t Test
/* Returns clock rate out of a divider */
static uint32_t Chip_Clock_GetDivRate(CHIP_CGU_CLKIN_T clock, CHIP_CGU_IDIV_T divider)
{
(void) clock;
CHIP_CGU_CLKIN_T input;
uint32_t div;

2
hw/mcu/nxp/lpc_chip_18xx/src/gpio_18xx_43xx.c
View File

@@ -50,11 +50,13 @@
/* Initialize GPIO block */
void Chip_GPIO_Init(LPC_GPIO_T *pGPIO)
{
(void) pGPIO;
}
/* De-Initialize GPIO block */
void Chip_GPIO_DeInit(LPC_GPIO_T *pGPIO)
{
(void) pGPIO;
}

2
hw/mcu/nxp/lpc_chip_18xx/src/sysinit_18xx_43xx.c
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@@ -133,7 +133,7 @@ void Chip_SetupCoreClock(CHIP_CGU_CLKIN_T clkin, uint32_t core_freq, bool setbas
/* Setup system base clocks and initial states. This won't enable and
disable individual clocks, but sets up the base clock sources for
each individual peripheral clock. */
for (i = 0; i < (sizeof(InitClkStates) / sizeof(InitClkStates[0])); i++) {
for (i = 0; i < (int) (sizeof(InitClkStates) / sizeof(InitClkStates[0])); i++) {
Chip_Clock_SetBaseClock(InitClkStates[i].clk, InitClkStates[i].clkin,
InitClkStates[i].autoblock_enab, InitClkStates[i].powerdn);
}

2
hw/mcu/nxp/lpc_chip_18xx/src/uart_18xx_43xx.c
View File

@@ -132,6 +132,8 @@ void Chip_UART_Init(LPC_USART_T *pUART)
/* Disable fractional divider */
pUART->FDR = 0x10;
(void) tmp;
}
/* De-initializes the pUART peripheral */