move lpc_chip_13xx files
This commit is contained in:
hathach
496
hw/mcu/nxp/lpc_chip_13xx/src/ssp_13xx.c
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496
hw/mcu/nxp/lpc_chip_13xx/src/ssp_13xx.c
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@@ -0,0 +1,496 @@
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/*
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* @brief LPC13xx SSP Registers and control functions
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*
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* @note
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* Copyright(C) NXP Semiconductors, 2012
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* All rights reserved.
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*
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* @par
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* Software that is described herein is for illustrative purposes only
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* which provides customers with programming information regarding the
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* LPC products. This software is supplied "AS IS" without any warranties of
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* any kind, and NXP Semiconductors and its licensor disclaim any and
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* all warranties, express or implied, including all implied warranties of
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* merchantability, fitness for a particular purpose and non-infringement of
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* intellectual property rights. NXP Semiconductors assumes no responsibility
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* or liability for the use of the software, conveys no license or rights under any
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* patent, copyright, mask work right, or any other intellectual property rights in
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* or to any products. NXP Semiconductors reserves the right to make changes
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* in the software without notification. NXP Semiconductors also makes no
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* representation or warranty that such application will be suitable for the
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* specified use without further testing or modification.
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*
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* @par
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* Permission to use, copy, modify, and distribute this software and its
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* documentation is hereby granted, under NXP Semiconductors' and its
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* licensor's relevant copyrights in the software, without fee, provided that it
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* is used in conjunction with NXP Semiconductors microcontrollers. This
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* copyright, permission, and disclaimer notice must appear in all copies of
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* this code.
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*/
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#include "chip.h"
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/*****************************************************************************
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* Private types/enumerations/variables
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****************************************************************************/
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/*****************************************************************************
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* Public types/enumerations/variables
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****************************************************************************/
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/*****************************************************************************
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* Private functions
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****************************************************************************/
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STATIC void SSP_Write2BFifo(LPC_SSP_T *pSSP, Chip_SSP_DATA_SETUP_T *xf_setup)
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{
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if (xf_setup->tx_data) {
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Chip_SSP_SendFrame(pSSP, (*(uint16_t *) ((uint32_t) xf_setup->tx_data +
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xf_setup->tx_cnt)));
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}
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else {
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Chip_SSP_SendFrame(pSSP, 0xFFFF);
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}
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xf_setup->tx_cnt += 2;
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}
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/** SSP macro: write 1 bytes to FIFO buffer */
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STATIC void SSP_Write1BFifo(LPC_SSP_T *pSSP, Chip_SSP_DATA_SETUP_T *xf_setup)
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{
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if (xf_setup->tx_data) {
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Chip_SSP_SendFrame(pSSP, (*(uint8_t *) ((uint32_t) xf_setup->tx_data + xf_setup->tx_cnt)));
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}
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else {
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Chip_SSP_SendFrame(pSSP, 0xFF);
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}
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xf_setup->tx_cnt++;
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}
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/** SSP macro: read 1 bytes from FIFO buffer */
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STATIC void SSP_Read2BFifo(LPC_SSP_T *pSSP, Chip_SSP_DATA_SETUP_T *xf_setup)
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{
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uint16_t rDat;
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while ((Chip_SSP_GetStatus(pSSP, SSP_STAT_RNE) == SET) &&
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(xf_setup->rx_cnt < xf_setup->length)) {
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rDat = Chip_SSP_ReceiveFrame(pSSP);
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if (xf_setup->rx_data) {
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*(uint16_t *) ((uint32_t) xf_setup->rx_data + xf_setup->rx_cnt) = rDat;
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}
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xf_setup->rx_cnt += 2;
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}
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}
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/** SSP macro: read 2 bytes from FIFO buffer */
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STATIC void SSP_Read1BFifo(LPC_SSP_T *pSSP, Chip_SSP_DATA_SETUP_T *xf_setup)
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{
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uint16_t rDat;
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while ((Chip_SSP_GetStatus(pSSP, SSP_STAT_RNE) == SET) &&
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(xf_setup->rx_cnt < xf_setup->length)) {
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rDat = Chip_SSP_ReceiveFrame(pSSP);
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if (xf_setup->rx_data) {
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*(uint8_t *) ((uint32_t) xf_setup->rx_data + xf_setup->rx_cnt) = rDat;
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}
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xf_setup->rx_cnt++;
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}
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}
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/* Returns clock for the peripheral block */
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STATIC CHIP_SYSCTL_CLOCK_T Chip_SSP_GetClockIndex(LPC_SSP_T *pSSP)
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{
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CHIP_SYSCTL_CLOCK_T clkSSP;
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if (pSSP == LPC_SSP0) {
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clkSSP = SYSCTL_CLOCK_SSP0;
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}
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else {
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clkSSP = SYSCTL_CLOCK_SSP1;
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}
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return clkSSP;
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}
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/* Returns reset ID for the peripheral block */
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STATIC CHIP_SYSCTL_PERIPH_RESET_T Chip_SSP_GetResetIndex(LPC_SSP_T *pSSP)
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{
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CHIP_SYSCTL_PERIPH_RESET_T resetSSP;
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if (pSSP == LPC_SSP0) {
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resetSSP = RESET_SSP0;
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}
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else {
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resetSSP = RESET_SSP1;
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}
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return resetSSP;
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}
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/* Returns reset ID for the peripheral block */
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STATIC void Chip_SSP_SetSSPClkDivider(LPC_SSP_T *pSSP, uint32_t div)
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{
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if (pSSP == LPC_SSP0) {
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Chip_Clock_SetSSP0ClockDiv(div);
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}
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else {
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Chip_Clock_SetSSP1ClockDiv(div);
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}
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}
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/* Returns SSP peripheral clock for the peripheral block */
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STATIC uint32_t Chip_SSP_GetPCLKkRate(LPC_SSP_T *pSSP)
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{
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uint32_t sspCLK = Chip_Clock_GetMainClockRate();
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if (pSSP == LPC_SSP0) {
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sspCLK /= Chip_Clock_GetSSP0ClockDiv();
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}
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else {
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sspCLK /= Chip_Clock_GetSSP1ClockDiv();
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}
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return sspCLK;
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}
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/*****************************************************************************
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* Public functions
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****************************************************************************/
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/*Set up output clocks per bit for SSP bus*/
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void Chip_SSP_SetClockRate(LPC_SSP_T *pSSP, uint32_t clk_rate, uint32_t prescale)
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{
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uint32_t temp;
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temp = pSSP->CR0 & (~(SSP_CR0_SCR(0xFF)));
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pSSP->CR0 = temp | (SSP_CR0_SCR(clk_rate));
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pSSP->CPSR = prescale;
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}
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/* SSP Polling Read/Write in blocking mode */
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uint32_t Chip_SSP_RWFrames_Blocking(LPC_SSP_T *pSSP, Chip_SSP_DATA_SETUP_T *xf_setup)
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{
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/* Clear all remaining frames in RX FIFO */
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while (Chip_SSP_GetStatus(pSSP, SSP_STAT_RNE)) {
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Chip_SSP_ReceiveFrame(pSSP);
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}
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/* Clear status */
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Chip_SSP_ClearIntPending(pSSP, SSP_INT_CLEAR_BITMASK);
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if (Chip_SSP_GetDataSize(pSSP) > SSP_BITS_8) {
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while (xf_setup->rx_cnt < xf_setup->length || xf_setup->tx_cnt < xf_setup->length) {
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/* write data to buffer */
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if (( Chip_SSP_GetStatus(pSSP, SSP_STAT_TNF) == SET) && ( xf_setup->tx_cnt < xf_setup->length) ) {
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SSP_Write2BFifo(pSSP, xf_setup);
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}
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/* Check overrun error */
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if (Chip_SSP_GetRawIntStatus(pSSP, SSP_RORRIS) == SET) {
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return ERROR;
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}
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/* Check for any data available in RX FIFO */
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SSP_Read2BFifo(pSSP, xf_setup);
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}
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}
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else {
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while (xf_setup->rx_cnt < xf_setup->length || xf_setup->tx_cnt < xf_setup->length) {
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/* write data to buffer */
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if (( Chip_SSP_GetStatus(pSSP, SSP_STAT_TNF) == SET) && ( xf_setup->tx_cnt < xf_setup->length) ) {
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SSP_Write1BFifo(pSSP, xf_setup);
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}
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/* Check overrun error */
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if (Chip_SSP_GetRawIntStatus(pSSP, SSP_RORRIS) == SET) {
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return ERROR;
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}
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/* Check for any data available in RX FIFO */
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SSP_Read1BFifo(pSSP, xf_setup);
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}
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}
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if (xf_setup->tx_data) {
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return xf_setup->tx_cnt;
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}
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else if (xf_setup->rx_data) {
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return xf_setup->rx_cnt;
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}
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return 0;
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}
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/* SSP Polling Write in blocking mode */
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uint32_t Chip_SSP_WriteFrames_Blocking(LPC_SSP_T *pSSP, uint8_t *buffer, uint32_t buffer_len)
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{
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uint32_t tx_cnt = 0, rx_cnt = 0;
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/* Clear all remaining frames in RX FIFO */
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while (Chip_SSP_GetStatus(pSSP, SSP_STAT_RNE)) {
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Chip_SSP_ReceiveFrame(pSSP);
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}
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/* Clear status */
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Chip_SSP_ClearIntPending(pSSP, SSP_INT_CLEAR_BITMASK);
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if (Chip_SSP_GetDataSize(pSSP) > SSP_BITS_8) {
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uint16_t *wdata16;
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wdata16 = (uint16_t *) buffer;
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while (tx_cnt < buffer_len || rx_cnt < buffer_len) {
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/* write data to buffer */
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if ((Chip_SSP_GetStatus(pSSP, SSP_STAT_TNF) == SET) && (tx_cnt < buffer_len)) {
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Chip_SSP_SendFrame(pSSP, *wdata16);
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wdata16++;
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tx_cnt += 2;
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}
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/* Check overrun error */
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if (Chip_SSP_GetRawIntStatus(pSSP, SSP_RORRIS) == SET) {
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return ERROR;
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}
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/* Check for any data available in RX FIFO */
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while (Chip_SSP_GetStatus(pSSP, SSP_STAT_RNE) == SET) {
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Chip_SSP_ReceiveFrame(pSSP); /* read dummy data */
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rx_cnt += 2;
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}
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}
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}
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else {
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uint8_t *wdata8;
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wdata8 = buffer;
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while (tx_cnt < buffer_len || rx_cnt < buffer_len) {
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/* write data to buffer */
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if ((Chip_SSP_GetStatus(pSSP, SSP_STAT_TNF) == SET) && (tx_cnt < buffer_len)) {
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Chip_SSP_SendFrame(pSSP, *wdata8);
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wdata8++;
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tx_cnt++;
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}
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/* Check overrun error */
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if (Chip_SSP_GetRawIntStatus(pSSP, SSP_RORRIS) == SET) {
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return ERROR;
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}
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/* Check for any data available in RX FIFO */
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while (Chip_SSP_GetStatus(pSSP, SSP_STAT_RNE) == SET && rx_cnt < buffer_len) {
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Chip_SSP_ReceiveFrame(pSSP); /* read dummy data */
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rx_cnt++;
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}
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}
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}
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return tx_cnt;
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}
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/* SSP Polling Read in blocking mode */
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uint32_t Chip_SSP_ReadFrames_Blocking(LPC_SSP_T *pSSP, uint8_t *buffer, uint32_t buffer_len)
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{
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uint32_t rx_cnt = 0, tx_cnt = 0;
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/* Clear all remaining frames in RX FIFO */
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while (Chip_SSP_GetStatus(pSSP, SSP_STAT_RNE)) {
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Chip_SSP_ReceiveFrame(pSSP);
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}
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/* Clear status */
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Chip_SSP_ClearIntPending(pSSP, SSP_INT_CLEAR_BITMASK);
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if (Chip_SSP_GetDataSize(pSSP) > SSP_BITS_8) {
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uint16_t *rdata16;
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rdata16 = (uint16_t *) buffer;
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while (tx_cnt < buffer_len || rx_cnt < buffer_len) {
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/* write data to buffer */
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if ((Chip_SSP_GetStatus(pSSP, SSP_STAT_TNF) == SET) && (tx_cnt < buffer_len)) {
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Chip_SSP_SendFrame(pSSP, 0xFFFF); /* just send dummy data */
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tx_cnt += 2;
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}
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/* Check overrun error */
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if (Chip_SSP_GetRawIntStatus(pSSP, SSP_RORRIS) == SET) {
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return ERROR;
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}
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/* Check for any data available in RX FIFO */
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while (Chip_SSP_GetStatus(pSSP, SSP_STAT_RNE) == SET && rx_cnt < buffer_len) {
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*rdata16 = Chip_SSP_ReceiveFrame(pSSP);
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rdata16++;
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rx_cnt += 2;
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}
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}
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}
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else {
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uint8_t *rdata8;
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rdata8 = buffer;
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while (tx_cnt < buffer_len || rx_cnt < buffer_len) {
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/* write data to buffer */
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if ((Chip_SSP_GetStatus(pSSP, SSP_STAT_TNF) == SET) && (tx_cnt < buffer_len)) {
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Chip_SSP_SendFrame(pSSP, 0xFF); /* just send dummy data */
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tx_cnt++;
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}
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/* Check overrun error */
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if (Chip_SSP_GetRawIntStatus(pSSP, SSP_RORRIS) == SET) {
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return ERROR;
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}
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/* Check for any data available in RX FIFO */
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while (Chip_SSP_GetStatus(pSSP, SSP_STAT_RNE) == SET && rx_cnt < buffer_len) {
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*rdata8 = Chip_SSP_ReceiveFrame(pSSP);
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rdata8++;
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rx_cnt++;
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}
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}
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}
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return rx_cnt;
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}
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/* Clean all data in RX FIFO of SSP */
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void Chip_SSP_Int_FlushData(LPC_SSP_T *pSSP)
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{
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if (Chip_SSP_GetStatus(pSSP, SSP_STAT_BSY)) {
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while (Chip_SSP_GetStatus(pSSP, SSP_STAT_BSY)) {}
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}
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/* Clear all remaining frames in RX FIFO */
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while (Chip_SSP_GetStatus(pSSP, SSP_STAT_RNE)) {
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Chip_SSP_ReceiveFrame(pSSP);
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}
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/* Clear status */
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Chip_SSP_ClearIntPending(pSSP, SSP_INT_CLEAR_BITMASK);
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}
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/* SSP Interrupt Read/Write with 8-bit frame width */
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Status Chip_SSP_Int_RWFrames8Bits(LPC_SSP_T *pSSP, Chip_SSP_DATA_SETUP_T *xf_setup)
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{
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/* Check overrun error in RIS register */
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if (Chip_SSP_GetRawIntStatus(pSSP, SSP_RORRIS) == SET) {
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return ERROR;
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}
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if ((xf_setup->tx_cnt != xf_setup->length) || (xf_setup->rx_cnt != xf_setup->length)) {
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/* check if RX FIFO contains data */
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SSP_Read1BFifo(pSSP, xf_setup);
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while ((Chip_SSP_GetStatus(pSSP, SSP_STAT_TNF)) && (xf_setup->tx_cnt != xf_setup->length)) {
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/* Write data to buffer */
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SSP_Write1BFifo(pSSP, xf_setup);
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/* Check overrun error in RIS register */
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if (Chip_SSP_GetRawIntStatus(pSSP, SSP_RORRIS) == SET) {
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return ERROR;
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}
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/* Check for any data available in RX FIFO */
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SSP_Read1BFifo(pSSP, xf_setup);
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}
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return SUCCESS;
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}
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return ERROR;
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}
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/* SSP Interrupt Read/Write with 16-bit frame width */
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Status Chip_SSP_Int_RWFrames16Bits(LPC_SSP_T *pSSP, Chip_SSP_DATA_SETUP_T *xf_setup)
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{
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/* Check overrun error in RIS register */
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if (Chip_SSP_GetRawIntStatus(pSSP, SSP_RORRIS) == SET) {
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return ERROR;
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}
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if ((xf_setup->tx_cnt != xf_setup->length) || (xf_setup->rx_cnt != xf_setup->length)) {
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/* check if RX FIFO contains data */
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SSP_Read2BFifo(pSSP, xf_setup);
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while ((Chip_SSP_GetStatus(pSSP, SSP_STAT_TNF)) && (xf_setup->tx_cnt != xf_setup->length)) {
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/* Write data to buffer */
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SSP_Write2BFifo(pSSP, xf_setup);
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/* Check overrun error in RIS register */
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if (Chip_SSP_GetRawIntStatus(pSSP, SSP_RORRIS) == SET) {
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return ERROR;
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}
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||||
/* Check for any data available in RX FIFO */
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SSP_Read2BFifo(pSSP, xf_setup);
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}
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||||
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||||
return SUCCESS;
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||||
}
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||||
|
||||
return ERROR;
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||||
}
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||||
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/* Set the SSP operating modes, master or slave */
|
||||
void Chip_SSP_SetMaster(LPC_SSP_T *pSSP, bool master)
|
||||
{
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||||
if (master) {
|
||||
Chip_SSP_Set_Mode(pSSP, SSP_MODE_MASTER);
|
||||
}
|
||||
else {
|
||||
Chip_SSP_Set_Mode(pSSP, SSP_MODE_SLAVE);
|
||||
}
|
||||
}
|
||||
|
||||
/* Set the clock frequency for SSP interface */
|
||||
void Chip_SSP_SetBitRate(LPC_SSP_T *pSSP, uint32_t bitRate)
|
||||
{
|
||||
uint32_t ssp_clk, cr0_div, cmp_clk, prescale;
|
||||
|
||||
ssp_clk = Chip_SSP_GetPCLKkRate(pSSP);
|
||||
|
||||
cr0_div = 0;
|
||||
cmp_clk = 0xFFFFFFFF;
|
||||
prescale = 2;
|
||||
|
||||
while (cmp_clk > bitRate) {
|
||||
cmp_clk = ssp_clk / ((cr0_div + 1) * prescale);
|
||||
if (cmp_clk > bitRate) {
|
||||
cr0_div++;
|
||||
if (cr0_div > 0xFF) {
|
||||
cr0_div = 0;
|
||||
prescale += 2;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
Chip_SSP_SetClockRate(pSSP, cr0_div, prescale);
|
||||
}
|
||||
|
||||
/* Initialize the SSP */
|
||||
void Chip_SSP_Init(LPC_SSP_T *pSSP)
|
||||
{
|
||||
Chip_Clock_EnablePeriphClock(Chip_SSP_GetClockIndex(pSSP));
|
||||
Chip_SSP_SetSSPClkDivider(pSSP, 1);
|
||||
Chip_SYSCTL_PeriphReset(Chip_SSP_GetResetIndex(pSSP));
|
||||
|
||||
Chip_SSP_Set_Mode(pSSP, SSP_MODE_MASTER);
|
||||
Chip_SSP_SetFormat(pSSP, SSP_BITS_8, SSP_FRAMEFORMAT_SPI, SSP_CLOCK_CPHA0_CPOL0);
|
||||
Chip_SSP_SetBitRate(pSSP, 100000);
|
||||
}
|
||||
|
||||
/* De-initializes the SSP peripheral */
|
||||
void Chip_SSP_DeInit(LPC_SSP_T *pSSP)
|
||||
{
|
||||
Chip_SSP_Disable(pSSP);
|
||||
|
||||
Chip_Clock_DisablePeriphClock(Chip_SSP_GetClockIndex(pSSP));
|
||||
Chip_SSP_SetSSPClkDivider(pSSP, 0);
|
||||
}
|
||||
|
||||
Reference in New Issue
Block a user