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make sure usb buffer occupies whole cache line when DCACHE is enabled for msc,cdc,hid

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HIL enable device DMA for p4
This commit is contained in:
hathach
2024-11-21 10:15:30 +07:00
parent 2571889061
commit fa523a5682
10 changed files with 105 additions and 103 deletions
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6
src/tusb_option.h
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@@ -252,11 +252,7 @@
#define CFG_TUD_DWC2_SLAVE_ENABLE 1
#endif
// DWC2 controller: use DMA for data transfer
// For processors with data cache enabled, USB endpoint buffer region
// (defined by CFG_TUSB_MEM_SECTION) must be declared as non-cacheable.
// For example, on Cortex-M7 the MPU region can be configured as normal
// non-cacheable, with RASR register value: TEX=1 C=0 B=0 S=0.
// Enable DWC2 DMA for device
#ifndef CFG_TUD_DWC2_DMA_ENABLE
#define CFG_TUD_DWC2_DMA_ENABLE 0
#endif