Merge pull request #1405 from gregdavill/ch32v307
Add WCH CH32V307 port
This commit is contained in:
Ha Thach
345
src/portable/wch/ch32v307/ch32_usbhs_reg.h
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345
src/portable/wch/ch32v307/ch32_usbhs_reg.h
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#ifndef _USB_CH32_USBHS_REG_H
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#define _USB_CH32_USBHS_REG_H
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#include <ch32v30x.h>
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/******************* GLOBAL ******************/
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// USB CONTROL
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#define USBHS_CONTROL_OFFSET 0x00
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#define USBHS_DMA_EN (1 << 0)
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#define USBHS_ALL_CLR (1 << 1)
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#define USBHS_FORCE_RST (1 << 2)
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#define USBHS_INT_BUSY_EN (1 << 3)
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#define USBHS_DEV_PU_EN (1 << 4)
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#define USBHS_SPEED_MASK (3 << 5)
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#define USBHS_FULL_SPEED (0 << 5)
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#define USBHS_HIGH_SPEED (1 << 5)
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#define USBHS_LOW_SPEED (2 << 5)
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#define USBHS_HOST_MODE (1 << 7)
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// USB_INT_EN
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#define USBHS_INT_EN_OFFSET 0x02
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#define USBHS_BUS_RST_EN (1 << 0)
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#define USBHS_DETECT_EN (1 << 0)
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#define USBHS_TRANSFER_EN (1 << 1)
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#define USBHS_SUSPEND_EN (1 << 2)
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#define USBHS_SOF_ACT_EN (1 << 3)
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#define USBHS_FIFO_OV_EN (1 << 4)
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#define USBHS_SETUP_ACT_EN (1 << 5)
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#define USBHS_ISO_ACT_EN (1 << 6)
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#define USBHS_DEV_NAK_EN (1 << 7)
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// USB DEV AD
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#define USBHS_DEV_AD_OFFSET 0x03
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// USB FRAME_NO
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#define USBHS_FRAME_NO_OFFSET 0x04
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// USB SUSPEND
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#define USBHS_SUSPEND_OFFSET 0x06
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#define USBHS_DEV_REMOTE_WAKEUP (1 << 2)
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#define USBHS_LINESTATE_MASK (2 << 4) /* Read Only */
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// RESERVED0
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// USB SPEED TYPE
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#define USBHS_SPEED_TYPE_OFFSET 0x08
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#define USBSPEED_MASK (0x03)
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// USB_MIS_ST
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#define USBHS_MIS_ST_OFFSET 0x09
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#define USBHS_SPLIT_CAN (1 << 0)
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#define USBHS_ATTACH (1 << 1)
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#define USBHS_SUSPEND (1 << 2)
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#define USBHS_BUS_RESET (1 << 3)
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#define USBHS_R_FIFO_RDY (1 << 4)
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#define USBHS_SIE_FREE (1 << 5)
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#define USBHS_SOF_ACT (1 << 6)
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#define USBHS_SOF_PRES (1 << 7)
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// INT_FLAG
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#define USBHS_INT_FLAG_OFFSET 0x0A
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#define USBHS_BUS_RST_FLAG (1 << 0)
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#define USBHS_DETECT_FLAG (1 << 0)
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#define USBHS_TRANSFER_FLAG (1 << 1)
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#define USBHS_SUSPEND_FLAG (1 << 2)
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#define USBHS_HST_SOF_FLAG (1 << 3)
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#define USBHS_FIFO_OV_FLAG (1 << 4)
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#define USBHS_SETUP_FLAG (1 << 5)
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#define USBHS_ISO_ACT_FLAG (1 << 6)
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// INT_ST
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#define USBHS_INT_ST_OFFSET 0x0B
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#define USBHS_DEV_UIS_IS_NAK (1 << 7)
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#define USBHS_DEV_UIS_TOG_OK (1 << 6)
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#define MASK_UIS_TOKEN (3 << 4)
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#define MASK_UIS_ENDP (0x0F)
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#define MASK_UIS_H_RES (0x0F)
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#define USBHS_TOGGLE_OK (0x40)
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#define USBHS_HOST_RES (0x0f)
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//USB_RX_LEN
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#define USBHS_RX_LEN_OFFSET 0x0C
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/******************* DEVICE ******************/
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//UEP_CONFIG
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#define USBHS_UEP_CONFIG_OFFSET 0x10
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#define USBHS_EP0_T_EN (1 << 0)
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#define USBHS_EP0_R_EN (1 << 16)
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#define USBHS_EP1_T_EN (1 << 1)
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#define USBHS_EP1_R_EN (1 << 17)
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#define USBHS_EP2_T_EN (1 << 2)
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#define USBHS_EP2_R_EN (1 << 18)
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#define USBHS_EP3_T_EN (1 << 3)
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#define USBHS_EP3_R_EN (1 << 19)
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#define USBHS_EP4_T_EN (1 << 4)
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#define USBHS_EP4_R_EN (1 << 20)
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#define USBHS_EP5_T_EN (1 << 5)
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#define USBHS_EP5_R_EN (1 << 21)
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#define USBHS_EP6_T_EN (1 << 6)
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#define USBHS_EP6_R_EN (1 << 22)
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#define USBHS_EP7_T_EN (1 << 7)
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#define USBHS_EP7_R_EN (1 << 23)
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#define USBHS_EP8_T_EN (1 << 8)
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#define USBHS_EP8_R_EN (1 << 24)
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#define USBHS_EP9_T_EN (1 << 9)
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#define USBHS_EP9_R_EN (1 << 25)
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#define USBHS_EP10_T_EN (1 << 10)
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#define USBHS_EP10_R_EN (1 << 26)
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#define USBHS_EP11_T_EN (1 << 11)
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#define USBHS_EP11_R_EN (1 << 27)
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#define USBHS_EP12_T_EN (1 << 12)
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#define USBHS_EP12_R_EN (1 << 28)
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#define USBHS_EP13_T_EN (1 << 13)
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#define USBHS_EP13_R_EN (1 << 29)
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#define USBHS_EP14_T_EN (1 << 14)
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#define USBHS_EP14_R_EN (1 << 30)
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#define USBHS_EP15_T_EN (1 << 15)
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#define USBHS_EP15_R_EN (1 << 31)
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//UEP_TYPE
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#define USBHS_UEP_TYPE_OFFSET 0x14
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#define USBHS_EP0_T_TYP (1 << 0)
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#define USBHS_EP0_R_TYP (1 << 16)
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#define USBHS_EP1_T_TYP (1 << 1)
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#define USBHS_EP1_R_TYP (1 << 17)
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#define USBHS_EP2_T_TYP (1 << 2)
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#define USBHS_EP2_R_TYP (1 << 18)
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#define USBHS_EP3_T_TYP (1 << 3)
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#define USBHS_EP3_R_TYP (1 << 19)
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#define USBHS_EP4_T_TYP (1 << 4)
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#define USBHS_EP4_R_TYP (1 << 20)
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#define USBHS_EP5_T_TYP (1 << 5)
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#define USBHS_EP5_R_TYP (1 << 21)
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#define USBHS_EP6_T_TYP (1 << 6)
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#define USBHS_EP6_R_TYP (1 << 22)
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#define USBHS_EP7_T_TYP (1 << 7)
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#define USBHS_EP7_R_TYP (1 << 23)
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#define USBHS_EP8_T_TYP (1 << 8)
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#define USBHS_EP8_R_TYP (1 << 24)
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#define USBHS_EP9_T_TYP (1 << 8)
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#define USBHS_EP9_R_TYP (1 << 25)
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#define USBHS_EP10_T_TYP (1 << 10)
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#define USBHS_EP10_R_TYP (1 << 26)
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#define USBHS_EP11_T_TYP (1 << 11)
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#define USBHS_EP11_R_TYP (1 << 27)
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#define USBHS_EP12_T_TYP (1 << 12)
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#define USBHS_EP12_R_TYP (1 << 28)
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#define USBHS_EP13_T_TYP (1 << 13)
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#define USBHS_EP13_R_TYP (1 << 29)
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#define USBHS_EP14_T_TYP (1 << 14)
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#define USBHS_EP14_R_TYP (1 << 30)
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#define USBHS_EP15_T_TYP (1 << 15)
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#define USBHS_EP15_R_TYP (1 << 31)
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/* BUF_MOD UEP1~15 */
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#define USBHS_BUF_MOD_OFFSET 0x18
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#define USBHS_EP0_BUF_MOD (1 << 0)
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#define USBHS_EP0_ISO_BUF_MOD (1 << 16)
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#define USBHS_EP1_BUF_MOD (1 << 1)
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#define USBHS_EP1_ISO_BUF_MOD (1 << 17)
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#define USBHS_EP2_BUF_MOD (1 << 2)
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#define USBHS_EP2_ISO_BUF_MOD (1 << 18)
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#define USBHS_EP3_BUF_MOD (1 << 3)
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#define USBHS_EP3_ISO_BUF_MOD (1 << 19)
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#define USBHS_EP4_BUF_MOD (1 << 4)
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#define USBHS_EP4_ISO_BUF_MOD (1 << 20)
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#define USBHS_EP5_BUF_MOD (1 << 5)
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#define USBHS_EP5_ISO_BUF_MOD (1 << 21)
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#define USBHS_EP6_BUF_MOD (1 << 6)
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#define USBHS_EP6_ISO_BUF_MOD (1 << 22)
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#define USBHS_EP7_BUF_MOD (1 << 7)
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#define USBHS_EP7_ISO_BUF_MOD (1 << 23)
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#define USBHS_EP8_BUF_MOD (1 << 8)
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#define USBHS_EP8_ISO_BUF_MOD (1 << 24)
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#define USBHS_EP9_BUF_MOD (1 << 9)
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#define USBHS_EP9_ISO_BUF_MOD (1 << 25)
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#define USBHS_EP10_BUF_MOD (1 << 10)
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#define USBHS_EP10_ISO_BUF_MOD (1 << 26)
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#define USBHS_EP11_BUF_MOD (1 << 11)
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#define USBHS_EP11_ISO_BUF_MOD (1 << 27)
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#define USBHS_EP12_BUF_MOD (1 << 12)
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#define USBHS_EP12_ISO_BUF_MOD (1 << 28)
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#define USBHS_EP13_BUF_MOD (1 << 13)
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#define USBHS_EP13_ISO_BUF_MOD (1 << 29)
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#define USBHS_EP14_BUF_MOD (1 << 14)
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#define USBHS_EP14_ISO_BUF_MOD (1 << 30)
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#define USBHS_EP15_BUF_MOD (1 << 15)
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#define USBHS_EP15_ISO_BUF_MOD (1 << 31)
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//USBHS_EPn_T_EN USBHS_EPn_R_EN USBHS_EPn_BUF_MOD Description: Arrange from low to high with UEPn_DMA as the starting address
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// 0 0 x The endpoint is disabled and the UEPn_*_DMA buffers are not used.
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// 1 0 0 The first address of the receive (OUT) buffer is UEPn_RX_DMA
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// 1 0 1 RB_UEPn_RX_TOG[0]=0, use buffer UEPn_RX_DMA RB_UEPn_RX_TOG[0]=1, use buffer UEPn_TX_DMA
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// 0 1 0 The first address of the transmit (IN) buffer is UEPn_TX_DMA.
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// 0 1 1 RB_UEPn_TX_TOG[0]=0, use buffer UEPn_TX_DMA RB_UEPn_TX_TOG[0]=1, use buffer UEPn_RX_DMA
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/* USB0_DMA */
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#define USBHS_UEP0_DMA_OFFSET(n) (0x1C) // endpoint 0 DMA buffer address
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/* USBX_RX_DMA */
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#define USBHS_UEPx_RX_DMA_OFFSET(n) (0x1C + 4 * (n)) // endpoint x DMA buffer address
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#define USBHS_UEPx_TX_DMA_OFFSET(n) (0x58 + 4 * (n)) // endpoint x DMA buffer address
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#define USBHS_UEPx_MAX_LEN_OFFSET(n) (0x98 + 4 * (n)) // endpoint x DMA buffer address
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#define USBHS_UEPx_T_LEN_OFFSET(n) (0xD8 + 4 * (n)) // endpoint x DMA buffer address
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#define USBHS_UEPx_TX_CTRL_OFFSET(n) (0xD8 + 4 * (n) + 2) // endpoint x DMA buffer address
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#define USBHS_UEPx_RX_CTRL_OFFSET(n) (0xD8 + 4 * (n) + 3) // endpoint x DMA buffer address
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// UEPn_T_LEN
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#define USBHS_EP_T_LEN_MASK (0x7FF)
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//UEPn_TX_CTRL
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#define USBHS_EP_T_RES_MASK (3 << 0)
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#define USBHS_EP_T_RES_ACK (0 << 0)
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#define USBHS_EP_T_RES_NYET (1 << 0)
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#define USBHS_EP_T_RES_NAK (2 << 0)
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#define USBHS_EP_T_RES_STALL (3 << 0)
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#define USBHS_EP_T_TOG_MASK (3 << 3)
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#define USBHS_EP_T_TOG_0 (0 << 3)
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#define USBHS_EP_T_TOG_1 (1 << 3)
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#define USBHS_EP_T_TOG_2 (2 << 3)
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#define USBHS_EP_T_TOG_M (3 << 3)
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#define USBHS_EP_T_AUTOTOG (1 << 5)
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//UEPn_RX_CTRL
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#define USBHS_EP_R_RES_MASK (3 << 0)
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#define USBHS_EP_R_RES_ACK (0 << 0)
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#define USBHS_EP_R_RES_NYET (1 << 0)
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#define USBHS_EP_R_RES_NAK (2 << 0)
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#define USBHS_EP_R_RES_STALL (3 << 0)
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#define USBHS_EP_R_TOG_MASK (3 << 3)
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#define USBHS_EP_R_TOG_0 (0 << 3)
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#define USBHS_EP_R_TOG_1 (1 << 3)
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#define USBHS_EP_R_TOG_2 (2 << 3)
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#define USBHS_EP_R_TOG_M (3 << 3)
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#define USBHS_EP_R_AUTOTOG (1 << 5)
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#define USBHS_TOG_MATCH (1 << 6)
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/******************* HOST ******************/
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// USB HOST_CTRL
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#define USBHS_SEND_BUS_RESET (1 << 0)
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#define USBHS_SEND_BUS_SUSPEND (1 << 1)
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#define USBHS_SEND_BUS_RESUME (1 << 2)
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#define USBHS_REMOTE_WAKE (1 << 3)
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#define USBHS_PHY_SUSPENDM (1 << 4)
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#define USBHS_UH_SOFT_FREE (1 << 6)
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#define USBHS_SEND_SOF_EN (1 << 7)
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//UH_CONFIG
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#define USBHS_HOST_TX_EN (1 << 3)
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#define USBHS_HOST_RX_EN (1 << 18)
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// HOST_EP_TYPE
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#define USBHS_ENDP_TX_ISO (1 << 3)
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#define USBHS_ENDP_RX_ISO (1 << (16 + 2))
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// R32_UH_EP_PID
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#define USBHS_HOST_MASK_TOKEN (0x0f)
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#define USBHS_HOST_MASK_ENDP (0x0f << 4)
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//R8_UH_RX_CTRL
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#define USBHS_EP_R_RES_MASK (3 << 0)
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#define USBHS_EP_R_RES_ACK (0 << 0)
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#define USBHS_EP_R_RES_NYET (1 << 0)
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#define USBHS_EP_R_RES_NAK (2 << 0)
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#define USBHS_EP_R_RES_STALL (3 << 0)
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#define USBHS_UH_R_RES_NO (1 << 2)
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#define USBHS_UH_R_TOG_1 (1 << 3)
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#define USBHS_UH_R_TOG_2 (2 << 3)
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#define USBHS_UH_R_TOG_3 (3 << 3)
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#define USBHS_UH_R_TOG_AUTO (1 << 5)
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#define USBHS_UH_R_DATA_NO (1 << 6)
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//R8_UH_TX_CTRL
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#define USBHS_UH_T_RES_MASK (3 << 0)
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#define USBHS_UH_T_RES_ACK (0 << 0)
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#define USBHS_UH_T_RES_NYET (1 << 0)
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#define USBHS_UH_T_RES_NAK (2 << 0)
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#define USBHS_UH_T_RES_STALL (3 << 0)
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#define USBHS_UH_T_RES_NO (1 << 2)
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#define USBHS_UH_T_TOG_1 (1 << 3)
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#define USBHS_UH_T_TOG_2 (2 << 3)
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#define USBHS_UH_T_TOG_3 (3 << 3)
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#define USBHS_UH_T_TOG_AUTO (1 << 5)
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#define USBHS_UH_T_DATA_NO (1 << 6)
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// 00: OUT, 01:SOF, 10:IN, 11:SETUP
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#define PID_OUT 0
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#define PID_SOF 1
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#define PID_IN 2
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#define PID_SETUP 3
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#endif
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391
src/portable/wch/ch32v307/dcd_usbhs.c
Normal file
391
src/portable/wch/ch32v307/dcd_usbhs.c
Normal file
@@ -0,0 +1,391 @@
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/*
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* The MIT License (MIT)
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*
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* Copyright (c) 2022 Greg Davill
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
|
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* of this software and associated documentation files (the "Software"), to deal
|
||||
* in the Software without restriction, including without limitation the rights
|
||||
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
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* copies of the Software, and to permit persons to whom the Software is
|
||||
* furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in
|
||||
* all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
|
||||
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
|
||||
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
|
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* THE SOFTWARE.
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*
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* This file is part of the TinyUSB stack.
|
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*/
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#include "tusb_option.h"
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#if CFG_TUD_ENABLED && (CFG_TUSB_MCU == OPT_MCU_CH32V307)
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#include "device/dcd.h"
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#include "ch32_usbhs_reg.h"
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#include "core_riscv.h"
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// Max number of bi-directional endpoints including EP0
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#define EP_MAX 16
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typedef struct {
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uint8_t *buffer;
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// tu_fifo_t * ff; // TODO support dcd_edpt_xfer_fifo API
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uint16_t total_len;
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uint16_t queued_len;
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uint16_t max_size;
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bool short_packet;
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} xfer_ctl_t;
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|
||||
#define XFER_CTL_BASE(_ep, _dir) &xfer_status[_ep][_dir]
|
||||
static xfer_ctl_t xfer_status[EP_MAX][2];
|
||||
|
||||
#define EP_TX_LEN(ep) *(volatile uint16_t *)((volatile uint16_t *)&(USBHSD->UEP0_TX_LEN) + (ep)*2)
|
||||
#define EP_TX_CTRL(ep) *(volatile uint8_t *)((volatile uint8_t *)&(USBHSD->UEP0_TX_CTRL) + (ep)*4)
|
||||
#define EP_RX_CTRL(ep) *(volatile uint8_t *)((volatile uint8_t *)&(USBHSD->UEP0_RX_CTRL) + (ep)*4)
|
||||
#define EP_RX_MAX_LEN(ep) *(volatile uint16_t *)((volatile uint16_t *)&(USBHSD->UEP0_MAX_LEN) + (ep)*2)
|
||||
|
||||
#define EP_TX_DMA_ADDR(ep) *(volatile uint32_t *)((volatile uint32_t *)&(USBHSD->UEP1_TX_DMA) + (ep - 1))
|
||||
#define EP_RX_DMA_ADDR(ep) *(volatile uint32_t *)((volatile uint32_t *)&(USBHSD->UEP1_RX_DMA) + (ep - 1))
|
||||
|
||||
/* Endpoint Buffer */
|
||||
TU_ATTR_ALIGNED(4) uint8_t EP0_DatabufHD[64]; // ep0(64)
|
||||
|
||||
volatile uint8_t USBHS_Dev_Endp0_Tog = 0x01;
|
||||
|
||||
void dcd_init(uint8_t rhport) {
|
||||
(void)rhport;
|
||||
|
||||
memset(&xfer_status, 0, sizeof(xfer_status));
|
||||
|
||||
USBHSD->HOST_CTRL = 0x00;
|
||||
USBHSD->HOST_CTRL = USBHS_PHY_SUSPENDM;
|
||||
|
||||
USBHSD->CONTROL = 0;
|
||||
|
||||
#if TUD_OPT_HIGH_SPEED
|
||||
USBHSD->CONTROL = USBHS_DMA_EN | USBHS_INT_BUSY_EN | USBHS_HIGH_SPEED;
|
||||
#else
|
||||
#error OPT_MODE_FULL_SPEED not currently supported on CH32V307
|
||||
USBHSD->CONTROL = USBHS_DMA_EN | USBHS_INT_BUSY_EN | USBHS_FULL_SPEED;
|
||||
#endif
|
||||
|
||||
USBHSD->INT_EN = 0;
|
||||
USBHSD->INT_EN = USBHS_SETUP_ACT_EN | USBHS_TRANSFER_EN | USBHS_DETECT_EN | USBHS_SUSPEND_EN;
|
||||
|
||||
/* ALL endpoint enable */
|
||||
USBHSD->ENDP_CONFIG = 0xffffffff;
|
||||
|
||||
USBHSD->ENDP_CONFIG = USBHS_EP0_T_EN | USBHS_EP0_R_EN;
|
||||
USBHSD->ENDP_TYPE = 0x00;
|
||||
USBHSD->BUF_MODE = 0x00;
|
||||
|
||||
USBHSD->UEP0_MAX_LEN = 64;
|
||||
|
||||
USBHSD->UEP0_DMA = (uint32_t)EP0_DatabufHD;
|
||||
|
||||
USBHSD->UEP0_TX_LEN = 0;
|
||||
USBHSD->UEP0_TX_CTRL = USBHS_EP_T_RES_NAK;
|
||||
USBHSD->UEP0_RX_CTRL = USBHS_EP_R_RES_ACK;
|
||||
|
||||
for (int ep = 1; ep < EP_MAX; ep++) {
|
||||
EP_TX_LEN(ep) = 0;
|
||||
EP_TX_CTRL(ep) = USBHS_EP_T_AUTOTOG | USBHS_EP_T_RES_NAK;
|
||||
EP_RX_CTRL(ep) = USBHS_EP_R_AUTOTOG | USBHS_EP_R_RES_NAK;
|
||||
|
||||
EP_RX_MAX_LEN(ep) = 512;
|
||||
}
|
||||
|
||||
USBHSD->DEV_AD = 0;
|
||||
USBHSD->CONTROL |= USBHS_DEV_PU_EN;
|
||||
}
|
||||
|
||||
void dcd_int_enable(uint8_t rhport) {
|
||||
(void)rhport;
|
||||
|
||||
NVIC_EnableIRQ(USBHS_IRQn);
|
||||
}
|
||||
|
||||
void dcd_int_disable(uint8_t rhport) {
|
||||
(void)rhport;
|
||||
|
||||
NVIC_DisableIRQ(USBHS_IRQn);
|
||||
}
|
||||
|
||||
void dcd_edpt_close_all(uint8_t rhport) {
|
||||
(void)rhport;
|
||||
}
|
||||
|
||||
void dcd_set_address(uint8_t rhport, uint8_t dev_addr) {
|
||||
(void)dev_addr;
|
||||
|
||||
// Response with zlp status
|
||||
dcd_edpt_xfer(rhport, 0x80, NULL, 0);
|
||||
}
|
||||
|
||||
void dcd_remote_wakeup(uint8_t rhport)
|
||||
{
|
||||
(void) rhport;
|
||||
}
|
||||
|
||||
void dcd_edpt0_status_complete(uint8_t rhport, tusb_control_request_t const *request) {
|
||||
(void)rhport;
|
||||
|
||||
if (request->bmRequestType_bit.recipient == TUSB_REQ_RCPT_DEVICE &&
|
||||
request->bmRequestType_bit.type == TUSB_REQ_TYPE_STANDARD &&
|
||||
request->bRequest == TUSB_REQ_SET_ADDRESS) {
|
||||
USBHSD->DEV_AD = (uint8_t)request->wValue;
|
||||
}
|
||||
|
||||
EP_TX_CTRL(0) = USBHS_EP_T_RES_NAK;
|
||||
EP_RX_CTRL(0) = USBHS_EP_R_RES_ACK;
|
||||
}
|
||||
|
||||
bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const *desc_edpt) {
|
||||
(void)rhport;
|
||||
|
||||
uint8_t const epnum = tu_edpt_number(desc_edpt->bEndpointAddress);
|
||||
uint8_t const dir = tu_edpt_dir(desc_edpt->bEndpointAddress);
|
||||
|
||||
TU_ASSERT(epnum < EP_MAX);
|
||||
|
||||
xfer_ctl_t *xfer = XFER_CTL_BASE(epnum, dir);
|
||||
xfer->max_size = tu_edpt_packet_size(desc_edpt);
|
||||
|
||||
if (epnum != 0) {
|
||||
if (tu_edpt_dir(desc_edpt->bEndpointAddress) == TUSB_DIR_OUT) {
|
||||
EP_RX_CTRL(epnum) = USBHS_EP_R_AUTOTOG | USBHS_EP_R_RES_ACK;
|
||||
} else {
|
||||
EP_TX_LEN(epnum) = 0;
|
||||
EP_TX_CTRL(epnum) = USBHS_EP_T_AUTOTOG | USBHS_EP_T_RES_NAK | USBHS_EP_T_TOG_0;
|
||||
}
|
||||
}
|
||||
|
||||
return true;
|
||||
}
|
||||
|
||||
int usbd_ep_close(const uint8_t ep) {
|
||||
(void)ep;
|
||||
|
||||
return 0;
|
||||
}
|
||||
void dcd_edpt_stall(uint8_t rhport, uint8_t ep_addr) {
|
||||
(void)rhport;
|
||||
|
||||
uint8_t const epnum = tu_edpt_number(ep_addr);
|
||||
uint8_t const dir = tu_edpt_dir(ep_addr);
|
||||
|
||||
if (epnum == 0) {
|
||||
if (dir == TUSB_DIR_OUT) {
|
||||
USBHSD->UEP0_RX_CTRL = USBHS_EP_R_RES_STALL;
|
||||
} else {
|
||||
USBHSD->UEP0_TX_LEN = 0;
|
||||
USBHSD->UEP0_TX_CTRL = USBHS_EP_T_RES_STALL;
|
||||
}
|
||||
} else {
|
||||
if (dir == TUSB_DIR_OUT) {
|
||||
EP_RX_CTRL(epnum) = (EP_RX_CTRL(epnum) & ~USBHS_EP_R_RES_MASK) | USBHS_EP_R_RES_STALL;
|
||||
|
||||
} else {
|
||||
EP_TX_CTRL(epnum) = (EP_TX_CTRL(epnum) & ~USBHS_EP_T_RES_MASK) | USBHS_EP_T_RES_STALL;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
void dcd_edpt_clear_stall(uint8_t rhport, uint8_t ep_addr) {
|
||||
(void)rhport;
|
||||
|
||||
uint8_t const epnum = tu_edpt_number(ep_addr);
|
||||
uint8_t const dir = tu_edpt_dir(ep_addr);
|
||||
|
||||
if (epnum == 0) {
|
||||
if (dir == TUSB_DIR_OUT) {
|
||||
USBHSD->UEP0_RX_CTRL = USBHS_EP_R_RES_ACK;
|
||||
} else {
|
||||
}
|
||||
} else {
|
||||
if (dir == TUSB_DIR_OUT) {
|
||||
EP_RX_CTRL(epnum) = (EP_RX_CTRL(epnum) & ~(USBHS_EP_R_RES_MASK | USBHS_EP_T_TOG_MASK)) | USBHS_EP_T_RES_ACK;
|
||||
|
||||
} else {
|
||||
EP_TX_CTRL(epnum) = (EP_TX_CTRL(epnum) & ~(USBHS_EP_T_RES_MASK | USBHS_EP_T_TOG_MASK)) | USBHS_EP_T_RES_NAK;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
bool dcd_edpt_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t *buffer, uint16_t total_bytes) {
|
||||
(void)rhport;
|
||||
uint8_t const epnum = tu_edpt_number(ep_addr);
|
||||
uint8_t const dir = tu_edpt_dir(ep_addr);
|
||||
|
||||
xfer_ctl_t *xfer = XFER_CTL_BASE(epnum, dir);
|
||||
xfer->buffer = buffer;
|
||||
// xfer->ff = NULL; // TODO support dcd_edpt_xfer_fifo API
|
||||
xfer->total_len = total_bytes;
|
||||
xfer->queued_len = 0;
|
||||
xfer->short_packet = false;
|
||||
|
||||
// uint16_t num_packets = (total_bytes / xfer->max_size);
|
||||
uint16_t short_packet_size = total_bytes % (xfer->max_size + 1);
|
||||
|
||||
// Zero-size packet is special case.
|
||||
if (short_packet_size == 0 || (total_bytes == 0)) {
|
||||
xfer->short_packet = true;
|
||||
}
|
||||
|
||||
if (tu_edpt_dir(ep_addr) == TUSB_DIR_IN) {
|
||||
if (!total_bytes) {
|
||||
xfer->short_packet = true;
|
||||
if (epnum == 0) {
|
||||
USBHSD->UEP0_TX_LEN = 0;
|
||||
USBHSD->UEP0_TX_CTRL = USBHS_EP_T_RES_ACK | (USBHS_Dev_Endp0_Tog ? USBHS_EP_T_TOG_1 : USBHS_EP_T_TOG_0);
|
||||
USBHS_Dev_Endp0_Tog ^= 1;
|
||||
} else {
|
||||
EP_TX_LEN(epnum) = 0;
|
||||
EP_TX_CTRL(epnum) = (EP_TX_CTRL(epnum) & ~(USBHS_EP_T_RES_MASK)) | USBHS_EP_T_RES_ACK;
|
||||
}
|
||||
} else {
|
||||
if (epnum == 0) {
|
||||
xfer->queued_len += short_packet_size;
|
||||
memcpy(&EP0_DatabufHD[0], buffer, short_packet_size);
|
||||
|
||||
USBHSD->UEP0_TX_LEN = short_packet_size;
|
||||
USBHSD->UEP0_TX_CTRL = USBHS_EP_T_RES_ACK | (USBHS_Dev_Endp0_Tog ? USBHS_EP_T_TOG_1 : USBHS_EP_T_TOG_0);
|
||||
USBHS_Dev_Endp0_Tog ^= 1;
|
||||
} else {
|
||||
xfer->queued_len += short_packet_size;
|
||||
|
||||
EP_TX_DMA_ADDR(epnum) = (uint32_t)buffer;
|
||||
USBHSD->ENDP_CONFIG |= (USBHS_EP0_T_EN << epnum);
|
||||
EP_TX_LEN(epnum) = short_packet_size;
|
||||
EP_TX_CTRL(epnum) = (EP_TX_CTRL(epnum) & ~(USBHS_EP_T_RES_MASK)) | USBHS_EP_T_RES_ACK;
|
||||
}
|
||||
}
|
||||
} else { /* TUSB_DIR_OUT */
|
||||
if (epnum == 0) {
|
||||
uint32_t read_count = USBHSD->RX_LEN;
|
||||
read_count = TU_MIN(read_count, total_bytes);
|
||||
|
||||
if ((total_bytes == 8)) {
|
||||
read_count = 8;
|
||||
memcpy(buffer, &EP0_DatabufHD[0], 8);
|
||||
} else {
|
||||
memcpy(buffer, &EP0_DatabufHD[0], read_count);
|
||||
}
|
||||
} else {
|
||||
EP_RX_DMA_ADDR(epnum) = (uint32_t)xfer->buffer;
|
||||
USBHSD->ENDP_CONFIG |= (USBHS_EP0_R_EN << epnum);
|
||||
}
|
||||
|
||||
// usbd_ep_read(ep_addr, buffer, total_bytes, &ret_bytes);
|
||||
}
|
||||
return true;
|
||||
}
|
||||
|
||||
|
||||
static void receive_packet(xfer_ctl_t *xfer, uint16_t xfer_size) {
|
||||
// xfer->queued_len = xfer->total_len - remaining;
|
||||
|
||||
uint16_t remaining = xfer->total_len - xfer->queued_len;
|
||||
uint16_t to_recv_size;
|
||||
|
||||
if (remaining <= xfer->max_size) {
|
||||
// Avoid buffer overflow.
|
||||
to_recv_size = (xfer_size > remaining) ? remaining : xfer_size;
|
||||
} else {
|
||||
// Room for full packet, choose recv_size based on what the microcontroller
|
||||
// claims.
|
||||
to_recv_size = (xfer_size > xfer->max_size) ? xfer->max_size : xfer_size;
|
||||
}
|
||||
|
||||
if (to_recv_size) {
|
||||
}
|
||||
|
||||
xfer->queued_len += xfer_size;
|
||||
|
||||
// Per USB spec, a short OUT packet (including length 0) is always
|
||||
// indicative of the end of a transfer (at least for ctl, bulk, int).
|
||||
xfer->short_packet = (xfer_size < xfer->max_size);
|
||||
}
|
||||
|
||||
void dcd_int_handler(uint8_t rhport) {
|
||||
(void)rhport;
|
||||
|
||||
uint32_t end_num, rx_token;
|
||||
uint8_t intflag = 0;
|
||||
|
||||
intflag = USBHSD->INT_FG;
|
||||
|
||||
if (intflag & USBHS_TRANSFER_FLAG) {
|
||||
|
||||
end_num = (USBHSD->INT_ST) & MASK_UIS_ENDP;
|
||||
rx_token = (((USBHSD->INT_ST) & MASK_UIS_TOKEN) >> 4) & 0x03;
|
||||
|
||||
uint8_t endp = end_num | (rx_token == PID_IN ? TUSB_DIR_IN_MASK : 0);
|
||||
|
||||
xfer_ctl_t *xfer = XFER_CTL_BASE(end_num, tu_edpt_dir(endp));
|
||||
|
||||
if (rx_token == PID_OUT) {
|
||||
uint16_t rx_len = USBHSD->RX_LEN;
|
||||
|
||||
receive_packet(xfer, rx_len);
|
||||
|
||||
if (xfer->short_packet || (xfer->queued_len == xfer->total_len)) {
|
||||
xfer->short_packet = false;
|
||||
|
||||
dcd_event_xfer_complete(0, endp, xfer->queued_len, XFER_RESULT_SUCCESS, true);
|
||||
}
|
||||
|
||||
if (end_num == 0) {
|
||||
USBHSD->UEP0_RX_CTRL = USBHS_EP_R_RES_ACK | USBHS_EP_R_TOG_0;
|
||||
}
|
||||
|
||||
} else if (rx_token == PID_IN) {
|
||||
if (xfer->short_packet || (xfer->queued_len == xfer->total_len)) {
|
||||
xfer->short_packet = false;
|
||||
xfer->total_len = 0;
|
||||
dcd_event_xfer_complete(0, endp, xfer->queued_len, XFER_RESULT_SUCCESS, true);
|
||||
|
||||
EP_TX_CTRL(end_num) = (EP_TX_CTRL(end_num) & ~(USBHS_EP_T_RES_MASK)) | USBHS_EP_T_RES_NAK;
|
||||
|
||||
if (end_num == 0) {
|
||||
}
|
||||
} else {
|
||||
dcd_edpt_xfer(0, endp, xfer->buffer + xfer->queued_len, xfer->total_len - xfer->queued_len);
|
||||
}
|
||||
}
|
||||
|
||||
USBHSD->INT_FG = USBHS_TRANSFER_FLAG; /* Clear flag */
|
||||
} else if (intflag & USBHS_SETUP_FLAG) {
|
||||
USBHS_Dev_Endp0_Tog = 1;
|
||||
dcd_event_setup_received(0, EP0_DatabufHD, true);
|
||||
|
||||
USBHSD->INT_FG = USBHS_SETUP_FLAG; /* Clear flag */
|
||||
} else if (intflag & USBHS_DETECT_FLAG) {
|
||||
USBHS_Dev_Endp0_Tog = 1;
|
||||
|
||||
xfer_status[0][TUSB_DIR_OUT].max_size = 64;
|
||||
xfer_status[0][TUSB_DIR_IN].max_size = 64;
|
||||
|
||||
dcd_event_bus_reset(0, TUSB_SPEED_HIGH, true);
|
||||
|
||||
USBHSD->DEV_AD = 0;
|
||||
USBHSD->UEP0_RX_CTRL = USBHS_EP_R_RES_ACK | USBHS_EP_R_TOG_0;
|
||||
|
||||
USBHSD->INT_FG = USBHS_DETECT_FLAG; /* Clear flag */
|
||||
} else if (intflag & USBHS_SUSPEND_FLAG) {
|
||||
dcd_event_t event = { .rhport = rhport, .event_id = DCD_EVENT_SUSPEND };
|
||||
dcd_event_handler(&event, true);
|
||||
|
||||
USBHSD->INT_FG = USBHS_SUSPEND_FLAG; /* Clear flag */
|
||||
}
|
||||
}
|
||||
|
||||
#endif
|
||||
Reference in New Issue
Block a user