Ha Thach
1ef820ecfe
Enhance chipidea ( #2075 )
...
* update chipidea dcd, remove manual ep_count and use DCCPARAMS to get number of endpoint instead
* add dcd dcache for chipidea
* add cmake for lpc18
* add makefile build for mcx
* use fork of mcu sdk
* fix ci build with nrf
* flash rp2040 with openocd
2023-05-23 21:45:00 +07:00
hathach
3623ba1884
fix trailing space and new line
...
temporarily disable codespell
2023-03-17 16:12:49 +07:00
hathach
ffdffc7e06
rename FREERTOS_PORT to FREERTOS_PORTABLE_SRC
...
also fix trailing spaces
2023-03-16 23:11:11 +07:00
hathach
05e0205ad0
Merge branch 'master' into renesas-ra
2023-03-08 21:05:06 +07:00
hathach
a6001fc8f2
update uart read for lpc18/43 for testing
2022-11-18 21:50:00 +07:00
hathach
2571211957
remove static port defined for device/host
2022-06-03 11:32:09 +07:00
hathach
8b9cf152a0
rhport argument in usbd_ API() is not used (always use the initialized port)
...
remove the usage of TUD_OPT_RHPORT in class driver
2022-06-02 16:51:17 +07:00
Rafael Silva
2a17a7e8f8
rework make freertos port handling
...
this allows ports to specify a freertos port outside the FreeRTOS-Kernel lib directory, which would otherwise not be possible
Signed-off-by: Rafael Silva <rafaelsilva@ajtec.pt >
2022-06-02 09:35:30 +01:00
hathach
0612433eef
add chipidea highspeed controller
...
add warning to transdimension for the rename
2021-12-01 12:14:44 +07:00
hathach
a5f516893b
more with -Wcast-qual
2021-10-17 16:36:53 +07:00
hathach
e115e08728
add nxp_lpcopen as submodule
2021-04-28 18:11:49 +07:00
hathach
253430a765
add example specific DEPS_SUBMODULES
2021-03-18 16:28:44 +07:00
hathach
ed8f117dd1
explicitly add dcd source file without vendor/family
2021-03-17 16:52:07 +07:00
hathach
590d8d4d5c
rename FAMILY_SUBMODULES to DEPS_SUBMODULES
2021-03-04 22:53:02 +07:00
hathach
e1966f8d91
mcb1800 and lpc18s37 work well with both device and host demo
2021-03-03 17:29:30 +07:00
hathach
0dc1a3d3af
add lpc18 family
2021-03-03 16:03:21 +07:00
