4 Commits

Author	SHA1	Message	Date
hathach	3eb0451879	change CFG_TUSB_MEM_DCACHE_LINE_SIZE_DEFAULT (not defined) to 1 ... use stock iar linker	2025-07-07 20:31:49 +07:00
HiFiPhile	ffab23cf0f	Revise DCache with RTT section ... Signed-off-by: HiFiPhile <admin@hifiphile.com>	2025-07-04 12:10:56 +02:00
hathach	211c2e380f	fix build with clang	2025-07-03 18:03:19 +07:00
HiFiPhile	424d743739	hw/h7rs: Update linker to put RTT in DTCM ... Signed-off-by: HiFiPhile <admin@hifiphile.com>	2025-06-13 22:49:06 +02:00