Rocky04
c3e96e667f
Change to control complete cb
2024-01-15 15:10:46 +00:00
Rocky04
1755bba509
Add DWC2 Test Mode SUpport
2024-01-15 12:47:13 +00:00
Alex Voinea
3bf6826451
Disable ULPI clock during sleep on stm32f7 when using internal phy
2024-01-10 10:27:21 +01:00
hathach
01f22a9e25
fix h7 running on fullspeed phy has issue with WFI if not disable ULPI clock
2023-11-22 22:50:10 +07:00
hathach
025ffa200c
add spec version to dwc2 info
2023-11-22 17:36:52 +07:00
HiFiPhile
8af470e06d
Fix CI
2023-11-19 16:19:11 +01:00
HiFiPhile
b5b34e73d6
Add dwc2 info of F429.
2023-11-19 16:10:16 +01:00
hathach
214a4afa6a
dwc2 flush tx,rx fifo in dcd_init()
2023-10-31 11:53:40 +07:00
hathach
db3ff4b352
usb on u5a5 hs work well with correct VBVALEXTOEN/VBVALOVAL set
2023-10-31 11:26:31 +07:00
hathach
9f0223dccd
minor clean up
2023-10-31 10:58:15 +07:00
hathach
305ef5d48a
minor space format dwc2 driver
2023-10-30 22:22:27 +07:00
hathach
a4c542a7b4
addd dwc2_info.py/md update stm32u5a5 board clock & power configure, able to get passed otg clock reset
2023-10-30 22:21:58 +07:00
hathach
27a2c8cba4
adding nulceo stm32u5a5, fix clock configure issue
...
dwc2 core stuck at reset
2023-10-18 18:43:07 +07:00
bac
1168e4e163
Added support for USB2 HS peripheral (with integrated HS PHY) on STM32U59x chips
2023-09-26 15:27:17 +01:00
Michiel van Leeuwen
75cf8e21a7
Use double-sized fifo only for IN endpoints
2023-05-04 10:02:42 +02:00
Michiel van Leeuwen
678edbe203
Check correct interrupt flag
...
Fixes #1737
2023-04-28 12:55:58 +02:00
Michiel van Leeuwen
5ade917805
dwc2: configure fifo size to be twice the max_size
...
This is needed in order to always be able to fit a packet in the fifo.
Writing to the fifo is done from an interrupts that fires when the fifo is
half-empty, so the fifo must be twice the packet size.
2023-04-28 11:26:26 +02:00
Gunar Schorcht
4c510c12b1
synopsys/dwc2: fix SOF interrupt handling
...
SOF is not a flag of the GOTGINT register but of the GINTSTS register. Therefore the flag must be written in the GINTSTS register instead of the GOTGINT register to clear the interrupt.
2023-02-27 09:54:45 +01:00
MasterPhi
9d19ed940e
dwc2: fix IAR warnings.
2023-01-11 18:50:38 +01:00
Bastien Nocera
6a2cf67289
Fix typos
2022-12-04 19:43:23 +07:00
LynnL4
4238467b2d
Add support for STM32U5 mcu
2022-10-13 17:39:42 +08:00
hathach
7a48b1f0d1
re-added code in pr 1438 to fix compile with h7 with 1 usb otg
2022-09-13 11:04:48 +07:00
hathach
8fe9022a6e
fix buid_board.py script
2022-06-29 14:06:44 +07:00
hathach
4f6e770eda
add more warning option, also fix -Wconversion with rp2040
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-Wuninitialized, -Wunused, -Wredundant-decls
2022-06-24 19:46:19 +07:00
hathach
1b08672945
more ci fix
2022-06-06 13:25:48 +07:00
hathach
f626916a57
update all dwc2 ports to support new dynamic controller support
2022-06-04 23:52:12 +07:00
hathach
31134f41a1
make dwc2 stm32 rhport support dynamic
2022-06-03 17:24:28 +07:00
Ha Thach
fd8afc7e3b
Merge pull request #1454 from Iktek/bugfix_1453
...
overwrite grstctl on edpt_disable
2022-06-01 14:36:36 +07:00
hathach
6e7cd220dc
grstctl set fifo + flush in one assign
2022-06-01 13:18:24 +07:00
Ha Thach
9352f75220
Merge pull request #1438 from Nikitarc/master
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Update dwc2_stm32.h
2022-06-01 12:23:32 +07:00
Pascal Speck
f452ab745e
overwrite grstctl on edpt_disable
2022-05-03 09:52:10 +02:00
Nikitarc
c422b9ef41
Update dwc2_stm32.h
...
Add missing #endif
2022-04-20 11:29:03 +02:00
Nikitarc
52190e7308
Update dwc2_stm32.h
...
Support STM32H7 with only 1 USB port: H72x / H73x / H7Ax / H7Bx
2022-04-19 21:53:00 +02:00
Reinhard Panhuber
9fde8f2d9e
Fix DSTS_FNSOF in dwc2.c
2022-03-16 07:53:47 +01:00
Reinhard Panhuber
26339e694f
Merge remote-tracking branch 'upstream/add-sof-isr' into add-sof-isr
2022-03-14 20:40:57 +01:00
Reinhard Panhuber
f212899b54
Add SOF callback function for feedback value determination in uac - wip!
2022-03-14 20:40:33 +01:00
Ha Thach
41ffd54fa0
Merge branch 'master' into add-sof-isr
2022-03-14 11:57:01 +07:00
hathach
606f932d92
added dcd_sof_enable() stubs for all other ports
2022-03-07 23:05:05 +07:00
QianHao
65bf5ddb1b
Modify the wrong macro definition code
2022-03-07 08:04:49 +00:00
hathach
a4ba3f2891
add TUP_USBIP_DWC2
2022-02-26 17:13:06 +07:00
hathach
11c89d43ab
more internal rename
2022-02-26 17:06:50 +07:00
hathach
bc63f59af2
mcu specific rename
2022-02-26 15:23:29 +07:00
hathach
99ad3ae2ca
rename and move dcd_attr.h to tusb_mcu_attr.h
2022-02-25 18:35:21 +07:00
hathach
d10326cb4e
rename TUSB_OPT_DEVICE_ENABLED to CFG_TUD_ENABLED
...
TUSB_OPT_DEVICE_ENABLED still usable for backward compatible
2022-02-25 18:35:21 +07:00
Scott Shawcroft
a79ffeb764
Add Raspberry Pi Zero W and Zero 2 W
...
These are different Broadcom chips. The peripherals are essentially
the same. The main differences are:
* The CPU(s)
* The interrupt controller
* The peripheral base address (but not the peripherals that we use)
2022-01-05 13:47:01 -08:00
Ha Thach
b8d66e4d19
Merge pull request #1206 from hathach/bcm-dwc2-address
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Bcm dwc2 address
2021-11-22 12:07:07 +07:00
hathach
dac7574c98
use USB_OTG_GLOBAL_BASE instead of hard code value
2021-11-22 10:52:28 +07:00
hathach
301d6b4133
clean up
2021-11-17 09:48:08 +07:00
hathach
12e96ce571
set DCFG_XCVRDLY when using external ULPI highspeed phy
2021-11-15 12:18:28 +07:00
hathach
d87a897a7b
xmc4500 ported, cdc msc example run fine
2021-11-05 13:13:21 +07:00
