hathach
|
3eb0451879
|
change CFG_TUSB_MEM_DCACHE_LINE_SIZE_DEFAULT (not defined) to 1
use stock iar linker
|
2025-07-07 20:31:49 +07:00 |
|
HiFiPhile
|
3287cfaf76
|
Use DMA enable for DCache condition
Signed-off-by: HiFiPhile <admin@hifiphile.com>
|
2025-07-05 12:50:00 +02:00 |
|
HiFiPhile
|
e84efd2771
|
Add STM32 DWC2 cache support
Signed-off-by: HiFiPhile <admin@hifiphile.com>
|
2025-06-13 15:21:04 +02:00 |
|
hathach
|
7d66a3e775
|
merge n6 and h7rs (same config)
|
2025-06-12 21:20:49 +07:00 |
|
James Sandison
|
56c9521abd
|
chore: squash previous commits from other branches
|
2025-06-04 11:21:27 +10:00 |
|
Chintalagiri Shashank
|
a780071d20
|
Add support for STM32H7RSxx
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2024-11-16 12:32:26 +05:30 |
|
hathach
|
b5a4f18879
|
get hpri triggered
|
2024-10-17 15:56:12 +07:00 |
|
hathach
|
bb2d1dd0c1
|
update/rename ghwcfg registers
|
2024-09-30 11:53:17 +07:00 |
|
Alex Voinea
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3bf6826451
|
Disable ULPI clock during sleep on stm32f7 when using internal phy
|
2024-01-10 10:27:21 +01:00 |
|
hathach
|
01f22a9e25
|
fix h7 running on fullspeed phy has issue with WFI if not disable ULPI clock
|
2023-11-22 22:50:10 +07:00 |
|
hathach
|
db3ff4b352
|
usb on u5a5 hs work well with correct VBVALEXTOEN/VBVALOVAL set
|
2023-10-31 11:26:31 +07:00 |
|
hathach
|
a4c542a7b4
|
addd dwc2_info.py/md update stm32u5a5 board clock & power configure, able to get passed otg clock reset
|
2023-10-30 22:21:58 +07:00 |
|
hathach
|
27a2c8cba4
|
adding nulceo stm32u5a5, fix clock configure issue
dwc2 core stuck at reset
|
2023-10-18 18:43:07 +07:00 |
|
bac
|
1168e4e163
|
Added support for USB2 HS peripheral (with integrated HS PHY) on STM32U59x chips
|
2023-09-26 15:27:17 +01:00 |
|
MasterPhi
|
9d19ed940e
|
dwc2: fix IAR warnings.
|
2023-01-11 18:50:38 +01:00 |
|
Bastien Nocera
|
6a2cf67289
|
Fix typos
|
2022-12-04 19:43:23 +07:00 |
|
LynnL4
|
4238467b2d
|
Add support for STM32U5 mcu
|
2022-10-13 17:39:42 +08:00 |
|
hathach
|
7a48b1f0d1
|
re-added code in pr 1438 to fix compile with h7 with 1 usb otg
|
2022-09-13 11:04:48 +07:00 |
|
hathach
|
8fe9022a6e
|
fix buid_board.py script
|
2022-06-29 14:06:44 +07:00 |
|
hathach
|
4f6e770eda
|
add more warning option, also fix -Wconversion with rp2040
-Wuninitialized, -Wunused, -Wredundant-decls
|
2022-06-24 19:46:19 +07:00 |
|
hathach
|
1b08672945
|
more ci fix
|
2022-06-06 13:25:48 +07:00 |
|
hathach
|
f626916a57
|
update all dwc2 ports to support new dynamic controller support
|
2022-06-04 23:52:12 +07:00 |
|
hathach
|
31134f41a1
|
make dwc2 stm32 rhport support dynamic
|
2022-06-03 17:24:28 +07:00 |
|
Nikitarc
|
c422b9ef41
|
Update dwc2_stm32.h
Add missing #endif
|
2022-04-20 11:29:03 +02:00 |
|
Nikitarc
|
52190e7308
|
Update dwc2_stm32.h
Support STM32H7 with only 1 USB port: H72x / H73x / H7Ax / H7Bx
|
2022-04-19 21:53:00 +02:00 |
|
hathach
|
9cd5a87c64
|
add support for EFM32GG
merge GG12 GG12 to simply OPT_MCU_EFM32GG
|
2021-10-30 20:42:55 +07:00 |
|
hathach
|
660e8b8c88
|
skip snpsid check for gd32, abstract phyfs turnaround, set max timeout calibration.
still has issue with gd32 with msc (does work with running with rtt as
log).
|
2021-10-29 16:08:19 +07:00 |
|
hathach
|
7def380058
|
support bcm2711 on pi4, enhance dcd init with utmi and ulpi hs phy
|
2021-10-28 12:52:18 +07:00 |
|
hathach
|
3755814f57
|
add epin, epout to dwc2 regs
|
2021-10-26 11:49:59 +07:00 |
|
hathach
|
8df078dc9e
|
more rename
|
2021-10-26 11:11:46 +07:00 |
|
hathach
|
7369d2441d
|
update dwc2_type
|
2021-10-26 00:55:24 +07:00 |
|
hathach
|
4ccf60954d
|
moving esp32s2 to dwc2, abstract dwc2_set_turnaround()
|
2021-10-25 15:51:41 +07:00 |
|
hathach
|
61c80840c3
|
update dwc int enable/disable
|
2021-10-25 00:40:21 +07:00 |
|
hathach
|
32742571da
|
switch gd32 and stm32f4 to use new dwc2 driver
|
2021-10-25 00:06:57 +07:00 |
|
hathach
|
06de6b725c
|
adding generalized dwc2 driver
|
2021-10-24 23:24:46 +07:00 |
|