HiFiPhile
8055bc88d8
Code refactor.
2024-03-30 10:36:29 +07:00
HiFiPhile
4116a962a6
Flush FIFO on bus reset.
2024-03-30 10:36:28 +07:00
HiFiPhile
cab1106416
dwc2: add endpoint allocation support.
2024-03-30 10:36:27 +07:00
Rocky04
d0373f4749
Opt-out for USB Test-Mode
2024-02-19 17:44:18 +00:00
Chris Desjardins
5ca9980060
Do not enable the Mode mismatch interrupt source, it is not cleared
...
If this interrupt ever hits it will result in an infinite interrupt
loop as it is never cleared.
2024-02-15 16:34:31 +01:00
HiFiPhile
d692d77834
Merge branch 'master' into src/portable/synopsys/dwc2/fix_sof_int_handling
2024-02-01 11:12:20 +01:00
Rocky04
78a1d4c482
Merge branch 'master' into test-mode-support
2024-01-15 16:27:22 +01:00
Rocky04
c3e96e667f
Change to control complete cb
2024-01-15 15:10:46 +00:00
Rocky04
1755bba509
Add DWC2 Test Mode SUpport
2024-01-15 12:47:13 +00:00
hathach
214a4afa6a
dwc2 flush tx,rx fifo in dcd_init()
2023-10-31 11:53:40 +07:00
hathach
db3ff4b352
usb on u5a5 hs work well with correct VBVALEXTOEN/VBVALOVAL set
2023-10-31 11:26:31 +07:00
hathach
305ef5d48a
minor space format dwc2 driver
2023-10-30 22:22:27 +07:00
Michiel van Leeuwen
75cf8e21a7
Use double-sized fifo only for IN endpoints
2023-05-04 10:02:42 +02:00
Michiel van Leeuwen
678edbe203
Check correct interrupt flag
...
Fixes #1737
2023-04-28 12:55:58 +02:00
Michiel van Leeuwen
5ade917805
dwc2: configure fifo size to be twice the max_size
...
This is needed in order to always be able to fit a packet in the fifo.
Writing to the fifo is done from an interrupts that fires when the fifo is
half-empty, so the fifo must be twice the packet size.
2023-04-28 11:26:26 +02:00
Gunar Schorcht
4c510c12b1
synopsys/dwc2: fix SOF interrupt handling
...
SOF is not a flag of the GOTGINT register but of the GINTSTS register. Therefore the flag must be written in the GINTSTS register instead of the GOTGINT register to clear the interrupt.
2023-02-27 09:54:45 +01:00
MasterPhi
9d19ed940e
dwc2: fix IAR warnings.
2023-01-11 18:50:38 +01:00
Bastien Nocera
6a2cf67289
Fix typos
2022-12-04 19:43:23 +07:00
hathach
f626916a57
update all dwc2 ports to support new dynamic controller support
2022-06-04 23:52:12 +07:00
hathach
31134f41a1
make dwc2 stm32 rhport support dynamic
2022-06-03 17:24:28 +07:00
Ha Thach
fd8afc7e3b
Merge pull request #1454 from Iktek/bugfix_1453
...
overwrite grstctl on edpt_disable
2022-06-01 14:36:36 +07:00
hathach
6e7cd220dc
grstctl set fifo + flush in one assign
2022-06-01 13:18:24 +07:00
Pascal Speck
f452ab745e
overwrite grstctl on edpt_disable
2022-05-03 09:52:10 +02:00
Reinhard Panhuber
9fde8f2d9e
Fix DSTS_FNSOF in dwc2.c
2022-03-16 07:53:47 +01:00
Reinhard Panhuber
f212899b54
Add SOF callback function for feedback value determination in uac - wip!
2022-03-14 20:40:33 +01:00
hathach
606f932d92
added dcd_sof_enable() stubs for all other ports
2022-03-07 23:05:05 +07:00
hathach
a4ba3f2891
add TUP_USBIP_DWC2
2022-02-26 17:13:06 +07:00
hathach
11c89d43ab
more internal rename
2022-02-26 17:06:50 +07:00
hathach
bc63f59af2
mcu specific rename
2022-02-26 15:23:29 +07:00
hathach
99ad3ae2ca
rename and move dcd_attr.h to tusb_mcu_attr.h
2022-02-25 18:35:21 +07:00
hathach
d10326cb4e
rename TUSB_OPT_DEVICE_ENABLED to CFG_TUD_ENABLED
...
TUSB_OPT_DEVICE_ENABLED still usable for backward compatible
2022-02-25 18:35:21 +07:00
Scott Shawcroft
a79ffeb764
Add Raspberry Pi Zero W and Zero 2 W
...
These are different Broadcom chips. The peripherals are essentially
the same. The main differences are:
* The CPU(s)
* The interrupt controller
* The peripheral base address (but not the peripherals that we use)
2022-01-05 13:47:01 -08:00
hathach
301d6b4133
clean up
2021-11-17 09:48:08 +07:00
hathach
12e96ce571
set DCFG_XCVRDLY when using external ULPI highspeed phy
2021-11-15 12:18:28 +07:00
hathach
d87a897a7b
xmc4500 ported, cdc msc example run fine
2021-11-05 13:13:21 +07:00
hathach
b51d038b65
fix issue with bcm2711 caching issue by ading ISB() after dwc2_dcd_int_enable90
...
also add hwcfg_list for reference
2021-11-04 12:30:11 +07:00
hathach
7e68894726
grouping stm32L4 family in bsp
2021-11-02 16:10:40 +07:00
hathach
b809429873
minor clean up
2021-11-02 14:51:15 +07:00
hathach
aa682d7301
add fix for stm32l4 (version 3.10a) which generate transfer complete when setup recieved and control out data complete
2021-11-02 13:52:30 +07:00
hathach
215e0595ab
change F207 to use new dwc2
2021-10-31 00:09:40 +07:00
hathach
9cd5a87c64
add support for EFM32GG
...
merge GG12 GG12 to simply OPT_MCU_EFM32GG
2021-10-30 20:42:55 +07:00
hathach
660e8b8c88
skip snpsid check for gd32, abstract phyfs turnaround, set max timeout calibration.
...
still has issue with gd32 with msc (does work with running with rtt as
log).
2021-10-29 16:08:19 +07:00
hathach
6c67fc4125
correctly init hs phy for bcm
2021-10-29 00:53:30 +07:00
hathach
7def380058
support bcm2711 on pi4, enhance dcd init with utmi and ulpi hs phy
2021-10-28 12:52:18 +07:00
hathach
9f1cd1a753
add synopsys id check, rename GCCFG_* to STM32_GCCFG-*
2021-10-26 23:10:26 +07:00
hathach
bb5dab5c2e
add hw config struct
2021-10-26 22:48:01 +07:00
hathach
68fa9d4064
enhance fifo read/write
2021-10-26 13:56:56 +07:00
hathach
5d05f8758f
more clean up
2021-10-26 13:36:43 +07:00
hathach
4ebfd00d67
clean up
2021-10-26 13:33:40 +07:00
hathach
de413183d4
use dwc2->epin
2021-10-26 13:07:00 +07:00
