hathach
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d039d54a89
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channge DWC2_CHANNEL_COUNT/DWC2_EP_COUNT to inline function
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2025-04-14 23:45:20 +07:00 |
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HiFiPhile
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084c0802c3
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dwc2: refactor bitfields.
Signed-off-by: HiFiPhile <admin@hifiphile.com>
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2025-04-09 19:34:56 +02:00 |
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hathach
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d502a0c481
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fix correct DWC2_EP_COUNT
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2024-12-11 15:02:02 +07:00 |
|
Roman Leonov
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239443c197
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fix(dcd_dwc2): Correct usage of dwc2_controller
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2024-11-28 13:11:54 +01:00 |
|
Roman Leonov
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741fdaaee7
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fix(dcd_dwc2): Reset allocated_epin_count on bus reset and close all ep
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2024-11-28 13:01:07 +01:00 |
|
hathach
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ae7cdcd070
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fix typo
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2024-11-27 12:18:54 +07:00 |
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hathach
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be25aa31f6
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hcd dwc2 add dcache support, usbh correctly use cache line size with TUH_EPBUF_DEF
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2024-11-26 10:20:38 +07:00 |
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hathach
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833eb7d22d
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change dcd_dcache_*() API return type from void to bool
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2024-11-25 19:11:19 +07:00 |
|
hathach
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85e54b0fc3
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use TUD_EPBUF_DEF to declare buffer memory for midi
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2024-11-21 19:36:15 +07:00 |
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hathach
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fa523a5682
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make sure usb buffer occupies whole cache line when DCACHE is enabled for msc,cdc,hid
HIL enable device DMA for p4
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2024-11-21 10:22:09 +07:00 |
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hathach
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c61b55b191
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dcd wrap data to dcd_data_t, add padding for setup_packet to match cache line size
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2024-11-20 22:04:55 +07:00 |
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hathach
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b3b8bd88cb
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add CFG_TUD_MEM_DCACHE_ENABLE, CFG_TUD_MEM_DCACHE_LINE_SIZE option
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2024-11-20 21:30:29 +07:00 |
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hathach
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4da5de707b
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have p4 dma somewhat working but having issue with buffer that does not occupy the whole cache line
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2024-11-20 20:38:20 +07:00 |
|
Roman Leonov
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43a45f29cd
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feature(dcd_dwc2): Added cache synchronization
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2024-11-20 20:35:00 +07:00 |
|
Roman Leonov
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b8d31a59ee
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feature(dcd_dwc2): Added cache synchronization
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2024-11-20 13:10:23 +01:00 |
|
hathach
|
3fe7e612c8
|
remove commented code
|
2024-11-18 23:38:25 +07:00 |
|
hathach
|
6d4a60d8ac
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clean up
|
2024-11-18 23:07:05 +07:00 |
|
hathach
|
d37707d6dd
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move handle ep slave/dma wihtin compiler macro
|
2024-11-18 23:02:17 +07:00 |
|
hathach
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dab600bea2
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merge back and improve edpt_schedule_packets
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2024-11-18 17:51:56 +07:00 |
|
hathach
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a2ab783db7
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seperate handle_epin_dma/slave
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2024-11-18 12:39:00 +07:00 |
|
hathach
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db7670a3bc
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separate handle out dma and slave
separate edpt_schedule_packets into epout/epin xfer
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2024-11-18 11:35:46 +07:00 |
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hathach
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a68c53fb8e
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clean up, add typdef for dwc2 type for device
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2024-11-14 17:34:14 +07:00 |
|
hathach
|
daef846aa7
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rename CFG_TUD_DWC2_DMA to CFG_TUD_DWC2_DMA_ENABLE
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2024-11-14 13:26:11 +07:00 |
|
hathach
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c8d104fb47
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fix warnings
|
2024-11-08 21:55:23 +07:00 |
|
hathach
|
b7ff10f59c
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rename and add both CFG_TUH_DWC2_SLAVE_ENABLE/CFG_TUH_DWC2_DMA_ENABLE better out dma handle
|
2024-11-01 17:54:10 +07:00 |
|
hathach
|
3c1cb0e08f
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correct the fifo_available comparison (words not byte)
|
2024-10-29 22:48:58 +07:00 |
|
hathach
|
dd99da9dce
|
implement hcd_edpt_abort_xfer, hcd_device_close,
check request queue available before making usb attempt. Though there is no handling when queue is full.
device_info example work well
|
2024-10-28 17:45:44 +07:00 |
|
hathach
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79c0a249e8
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got In transfer working, able to get 1st device descriptor and set address
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2024-10-25 22:56:25 +07:00 |
|
hathach
|
07abc722b6
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hcd able to send setup packet
|
2024-10-25 19:00:45 +07:00 |
|
hathach
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063661e3a3
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more progress on dwc2 hcd, initial code for edpt xfer
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2024-10-25 00:20:34 +07:00 |
|
hathach
|
f5978876d2
|
get hprt interrupt triggered
|
2024-10-21 11:43:37 +07:00 |
|
hathach
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b5a4f18879
|
get hpri triggered
|
2024-10-17 15:56:12 +07:00 |
|
hathach
|
8d9d3d9a2a
|
move gahbcfg/gintmsk with dma to dwc2 common
|
2024-10-16 13:19:28 +07:00 |
|
hathach
|
4012e15075
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move core init code to dwc2 common. update/correct build for esppressif
|
2024-10-15 17:55:24 +07:00 |
|
hathach
|
10a3aa3cc8
|
adding hcd dwc2
|
2024-10-15 13:03:12 +07:00 |
|
hathach
|
e83e08343a
|
change dcd_init() return from void to bool
|
2024-10-14 19:42:22 +07:00 |
|
hathach
|
1f18be93db
|
change the tusb_rhport_init_t struct, exclude the rhport to make API more consistent
|
2024-10-14 18:27:52 +07:00 |
|
hathach
|
d997f0071e
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change dcd_init() to take rhport struct
|
2024-10-11 15:31:49 +07:00 |
|
hathach
|
1406ad84e3
|
remove debug code
|
2024-10-10 11:05:32 +07:00 |
|
hathach
|
98e94a5d6d
|
enhance dwc2
|
2024-10-10 00:08:46 +07:00 |
|
hathach
|
599bb0c822
|
improving dwc2, merging diep and doep if possible
|
2024-10-10 00:08:45 +07:00 |
|
hathach
|
b2a98eadab
|
add stm32f769disco to hil pool
|
2024-10-10 00:08:45 +07:00 |
|
hathach
|
87f1993304
|
esp32p4 use port0 as fs, port1 as highspeed
|
2024-09-30 11:53:19 +07:00 |
|
hathach
|
67e5577b42
|
added p4, seems to work well and enumerated
|
2024-09-30 11:53:18 +07:00 |
|
hathach
|
bb2d1dd0c1
|
update/rename ghwcfg registers
|
2024-09-30 11:53:17 +07:00 |
|
hathach
|
6a15e7875c
|
more rename
|
2024-09-24 18:12:01 +07:00 |
|
hathach
|
a1244381b3
|
add CFG_TUD_DWC2_DMA, make it compile time option
|
2024-09-24 17:55:15 +07:00 |
|
hathach
|
86b4608365
|
update dfifo allocation scheme to use top pointer, update document and explanation for EPInfo address and GDFIFO.
some function rename
update h743 linker to use SRAM1 since USB DMA cannot access DTCM ram
update xmc4500 to use uuid for testing
|
2024-09-24 17:38:31 +07:00 |
|
HiFiPhile
|
7867464694
|
Merge branch 'master' into dwc2_dma
|
2024-09-08 17:15:28 +02:00 |
|
hathach
|
0bb7b992d8
|
dwc2: for esp32 force disconnect/connect using USB_WRAP otg pad override (DM=DP=0) in addition to dwc2's dctrl
|
2024-09-04 20:56:04 +07:00 |
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