144 lines
8.3 KiB
C
144 lines
8.3 KiB
C
/*
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* Copyright 2022 NXP
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* All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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/***********************************************************************************************************************
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* This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
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* will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
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**********************************************************************************************************************/
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/* clang-format off */
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/*
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* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
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!!GlobalInfo
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product: Pins v12.0
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processor: MCXN947
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package_id: MCXN947VDF
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mcu_data: ksdk2_0
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processor_version: 0.12.3
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* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
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*/
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/* clang-format on */
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#include "fsl_common.h"
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#include "fsl_port.h"
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#include "pin_mux.h"
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/* FUNCTION ************************************************************************************************************
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*
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* Function Name : BOARD_InitBootPins
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* Description : Calls initialization functions.
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*
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* END ****************************************************************************************************************/
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void BOARD_InitBootPins(void)
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{
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BOARD_InitPins();
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}
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/* clang-format off */
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/*
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* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
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BOARD_InitPins:
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- options: {callFromInitBoot: 'true', coreID: cm33_core0, enableClock: 'true'}
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- pin_list:
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- {pin_num: A1, peripheral: LPFlexcomm4, signal: LPFLEXCOMM_P0, pin_signal: PIO1_8/WUU0_IN10/LPTMR1_ALT3/TRACE_DATA0/FC4_P0/FC5_P4/CT_INP8/SCT0_OUT2/FLEXIO0_D16/PLU_OUT0/ENET0_TXD2/I3C1_SDA/TSI0_CH17/ADC1_A8,
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slew_rate: fast, open_drain: disable, drive_strength: low, pull_select: down, pull_enable: disable, passive_filter: disable, pull_value: low, input_buffer: enable,
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invert_input: normal}
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- {pin_num: B1, peripheral: LPFlexcomm4, signal: LPFLEXCOMM_P1, pin_signal: PIO1_9/TRACE_DATA1/FC4_P1/FC5_P5/CT_INP9/SCT0_OUT3/FLEXIO0_D17/PLU_OUT1/ENET0_TXD3/I3C1_SCL/TSI0_CH18/ADC1_A9,
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slew_rate: fast, open_drain: disable, drive_strength: low, pull_select: down, pull_enable: disable, passive_filter: disable, input_buffer: enable, invert_input: normal}
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- {pin_num: B7, peripheral: GPIO0, signal: 'GPIO, 23', pin_signal: PIO0_23/WUU0_IN5/EWM0_OUT_b/FC1_P3/CT_INP3/FLEXIO0_D7/ADC0_A15/CMP2_IN2, direction: INPUT, slew_rate: fast,
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open_drain: disable, drive_strength: low, pull_select: down, pull_enable: disable, input_buffer: enable, invert_input: normal}
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* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
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*/
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/* clang-format on */
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/* FUNCTION ************************************************************************************************************
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*
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* Function Name : BOARD_InitPins
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* Description : Configures pin routing and optionally pin electrical features.
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*
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* END ****************************************************************************************************************/
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void BOARD_InitPins(void)
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{
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/* Enables the clock for PORT0: Enables clock */
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CLOCK_EnableClock(kCLOCK_Port0);
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/* Enables the clock for PORT1: Enables clock */
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CLOCK_EnableClock(kCLOCK_Port1);
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const port_pin_config_t port1_8_pinA1_config = {/* Internal pull-up/down resistor is disabled */
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kPORT_PullDisable,
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/* Low internal pull resistor value is selected. */
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kPORT_LowPullResistor,
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/* Fast slew rate is configured */
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kPORT_FastSlewRate,
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/* Passive input filter is disabled */
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kPORT_PassiveFilterDisable,
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/* Open drain output is disabled */
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kPORT_OpenDrainDisable,
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/* Low drive strength is configured */
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kPORT_LowDriveStrength,
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/* Pin is configured as FC4_P0 */
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kPORT_MuxAlt2,
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/* Digital input enabled */
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kPORT_InputBufferEnable,
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/* Digital input is not inverted */
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kPORT_InputNormal,
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/* Pin Control Register fields [15:0] are not locked */
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kPORT_UnlockRegister};
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/* PORT1_8 (pin A1) is configured as FC4_P0 */
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PORT_SetPinConfig(PORT1, 8U, &port1_8_pinA1_config);
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const port_pin_config_t port1_9_pinB1_config = {/* Internal pull-up/down resistor is disabled */
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kPORT_PullDisable,
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/* Low internal pull resistor value is selected. */
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kPORT_LowPullResistor,
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/* Fast slew rate is configured */
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kPORT_FastSlewRate,
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/* Passive input filter is disabled */
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kPORT_PassiveFilterDisable,
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/* Open drain output is disabled */
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kPORT_OpenDrainDisable,
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/* Low drive strength is configured */
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kPORT_LowDriveStrength,
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/* Pin is configured as FC4_P1 */
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kPORT_MuxAlt2,
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/* Digital input enabled */
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kPORT_InputBufferEnable,
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/* Digital input is not inverted */
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kPORT_InputNormal,
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/* Pin Control Register fields [15:0] are not locked */
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kPORT_UnlockRegister};
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/* PORT1_9 (pin B1) is configured as FC4_P1 */
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PORT_SetPinConfig(PORT1, 9U, &port1_9_pinB1_config);
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const port_pin_config_t SW2 = {/* Internal pull-up/down resistor is disabled */
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kPORT_PullDisable,
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/* Low internal pull resistor value is selected. */
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kPORT_LowPullResistor,
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/* Fast slew rate is configured */
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kPORT_FastSlewRate,
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/* Passive input filter is disabled */
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kPORT_PassiveFilterDisable,
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/* Open drain output is disabled */
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kPORT_OpenDrainDisable,
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/* Low drive strength is configured */
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kPORT_LowDriveStrength,
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/* Pin is configured as PIO0_23 */
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kPORT_MuxAlt0,
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/* Digital input enabled */
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kPORT_InputBufferEnable,
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/* Digital input is not inverted */
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kPORT_InputNormal,
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/* Pin Control Register fields [15:0] are not locked */
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kPORT_UnlockRegister};
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/* PORT0_23 (pin B7) is configured as PIO0_23 */
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PORT_SetPinConfig(PORT0, 23U, &SW2);
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}
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/***********************************************************************************************************************
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* EOF
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**********************************************************************************************************************/
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