964 lines
35 KiB
C
964 lines
35 KiB
C
/**********************************************************************
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* $Id$ lpc17xx_emac.c 2010-05-21
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*//**
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* @file lpc17xx_emac.c
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* @brief Contains all functions support for Ethernet MAC firmware
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* library on LPC17xx
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* @version 2.0
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* @date 21. May. 2010
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* @author NXP MCU SW Application Team
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*
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* Copyright(C) 2010, NXP Semiconductor
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* All rights reserved.
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*
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***********************************************************************
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* Software that is described herein is for illustrative purposes only
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* which provides customers with programming information regarding the
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* products. This software is supplied "AS IS" without any warranties.
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* NXP Semiconductors assumes no responsibility or liability for the
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* use of the software, conveys no license or title under any patent,
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* copyright, or mask work right to the product. NXP Semiconductors
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* reserves the right to make changes in the software without
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* notification. NXP Semiconductors also make no representation or
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* warranty that such application will be suitable for the specified
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* use without further testing or modification.
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* Permission to use, copy, modify, and distribute this software and its
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* documentation is hereby granted, under NXP Semiconductors'
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* relevant copyright in the software, without fee, provided that it
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* is used in conjunction with NXP Semiconductors microcontrollers. This
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* copyright, permission, and disclaimer notice must appear in all copies of
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* this code.
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**********************************************************************/
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/* Peripheral group ----------------------------------------------------------- */
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/** @addtogroup EMAC
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* @{
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*/
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/* Includes ------------------------------------------------------------------- */
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#include "lpc17xx_emac.h"
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#include "lpc17xx_clkpwr.h"
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/* If this source file built with example, the LPC17xx FW library configuration
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* file in each example directory ("lpc17xx_libcfg.h") must be included,
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* otherwise the default FW library configuration file must be included instead
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*/
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#ifdef __BUILD_WITH_EXAMPLE__
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#include "lpc17xx_libcfg.h"
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#else
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#include "lpc17xx_libcfg_default.h"
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#endif /* __BUILD_WITH_EXAMPLE__ */
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#ifdef _EMAC
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/* Private Variables ---------------------------------------------------------- */
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/** @defgroup EMAC_Private_Variables EMAC Private Variables
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* @{
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*/
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/* MII Mgmt Configuration register - Clock divider setting */
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const uint8_t EMAC_clkdiv[] = { 4, 6, 8, 10, 14, 20, 28, 36, 40, 44, 48, 52, 56, 60, 64};
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/* EMAC local DMA Descriptors */
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/** Rx Descriptor data array */
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static RX_Desc Rx_Desc[EMAC_NUM_RX_FRAG];
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/** Rx Status data array - Must be 8-Byte aligned */
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#if defined ( __CC_ARM )
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static __align(8) RX_Stat Rx_Stat[EMAC_NUM_RX_FRAG];
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#elif defined ( __ICCARM__ )
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#pragma data_alignment=8
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static RX_Stat Rx_Stat[EMAC_NUM_RX_FRAG];
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#elif defined ( __GNUC__ )
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static __attribute__ ((aligned (8))) RX_Stat Rx_Stat[EMAC_NUM_RX_FRAG];
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#endif
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/** Tx Descriptor data array */
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static TX_Desc Tx_Desc[EMAC_NUM_TX_FRAG];
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/** Tx Status data array */
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static TX_Stat Tx_Stat[EMAC_NUM_TX_FRAG];
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/* EMAC local DMA buffers */
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/** Rx buffer data */
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static uint32_t rx_buf[EMAC_NUM_RX_FRAG][EMAC_ETH_MAX_FLEN>>2];
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/** Tx buffer data */
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static uint32_t tx_buf[EMAC_NUM_TX_FRAG][EMAC_ETH_MAX_FLEN>>2];
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/**
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* @}
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*/
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/* Private Functions ---------------------------------------------------------- */
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static void rx_descr_init (void);
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static void tx_descr_init (void);
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static int32_t write_PHY (uint32_t PhyReg, uint16_t Value);
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static int32_t read_PHY (uint32_t PhyReg);
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static void setEmacAddr(uint8_t abStationAddr[]);
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static int32_t emac_CRCCalc(uint8_t frame_no_fcs[], int32_t frame_len);
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/*--------------------------- rx_descr_init ---------------------------------*/
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/*********************************************************************//**
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* @brief Initializes RX Descriptor
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* @param[in] None
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* @return None
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***********************************************************************/
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static void rx_descr_init (void)
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{
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/* Initialize Receive Descriptor and Status array. */
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uint32_t i;
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for (i = 0; i < EMAC_NUM_RX_FRAG; i++) {
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Rx_Desc[i].Packet = (uint32_t)&rx_buf[i];
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Rx_Desc[i].Ctrl = EMAC_RCTRL_INT | (EMAC_ETH_MAX_FLEN - 1);
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Rx_Stat[i].Info = 0;
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Rx_Stat[i].HashCRC = 0;
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}
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/* Set EMAC Receive Descriptor Registers. */
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LPC_EMAC->RxDescriptor = (uint32_t)&Rx_Desc[0];
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LPC_EMAC->RxStatus = (uint32_t)&Rx_Stat[0];
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LPC_EMAC->RxDescriptorNumber = EMAC_NUM_RX_FRAG - 1;
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/* Rx Descriptors Point to 0 */
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LPC_EMAC->RxConsumeIndex = 0;
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}
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/*--------------------------- tx_descr_init ---- ----------------------------*/
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/*********************************************************************//**
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* @brief Initializes TX Descriptor
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* @param[in] None
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* @return None
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***********************************************************************/
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static void tx_descr_init (void) {
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/* Initialize Transmit Descriptor and Status array. */
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uint32_t i;
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for (i = 0; i < EMAC_NUM_TX_FRAG; i++) {
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Tx_Desc[i].Packet = (uint32_t)&tx_buf[i];
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Tx_Desc[i].Ctrl = 0;
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Tx_Stat[i].Info = 0;
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}
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/* Set EMAC Transmit Descriptor Registers. */
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LPC_EMAC->TxDescriptor = (uint32_t)&Tx_Desc[0];
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LPC_EMAC->TxStatus = (uint32_t)&Tx_Stat[0];
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LPC_EMAC->TxDescriptorNumber = EMAC_NUM_TX_FRAG - 1;
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/* Tx Descriptors Point to 0 */
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LPC_EMAC->TxProduceIndex = 0;
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}
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/*--------------------------- write_PHY -------------------------------------*/
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/*********************************************************************//**
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* @brief Write value to PHY device
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* @param[in] PhyReg: PHY Register address
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* @param[in] Value: Value to write
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* @return 0 - if success
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* 1 - if fail
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***********************************************************************/
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static int32_t write_PHY (uint32_t PhyReg, uint16_t Value)
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{
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/* Write a data 'Value' to PHY register 'PhyReg'. */
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uint32_t tout;
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LPC_EMAC->MADR = EMAC_DEF_ADR | PhyReg;
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LPC_EMAC->MWTD = Value;
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/* Wait until operation completed */
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tout = 0;
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for (tout = 0; tout < EMAC_MII_WR_TOUT; tout++) {
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if ((LPC_EMAC->MIND & EMAC_MIND_BUSY) == 0) {
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return (0);
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}
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}
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// Time out!
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return (-1);
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}
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/*--------------------------- read_PHY --------------------------------------*/
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/*********************************************************************//**
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* @brief Read value from PHY device
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* @param[in] PhyReg: PHY Register address
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* @return 0 - if success
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* 1 - if fail
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***********************************************************************/
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static int32_t read_PHY (uint32_t PhyReg)
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{
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/* Read a PHY register 'PhyReg'. */
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uint32_t tout;
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LPC_EMAC->MADR = EMAC_DEF_ADR | PhyReg;
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LPC_EMAC->MCMD = EMAC_MCMD_READ;
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/* Wait until operation completed */
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tout = 0;
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for (tout = 0; tout < EMAC_MII_RD_TOUT; tout++) {
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if ((LPC_EMAC->MIND & EMAC_MIND_BUSY) == 0) {
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LPC_EMAC->MCMD = 0;
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return (LPC_EMAC->MRDD);
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}
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}
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// Time out!
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return (-1);
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}
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/*********************************************************************//**
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* @brief Set Station MAC address for EMAC module
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* @param[in] abStationAddr Pointer to Station address that contains 6-bytes
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* of MAC address (should be in order from MAC Address 1 to MAC Address 6)
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* @return None
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**********************************************************************/
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static void setEmacAddr(uint8_t abStationAddr[])
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{
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/* Set the Ethernet MAC Address registers */
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LPC_EMAC->SA0 = ((uint32_t)abStationAddr[5] << 8) | (uint32_t)abStationAddr[4];
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LPC_EMAC->SA1 = ((uint32_t)abStationAddr[3] << 8) | (uint32_t)abStationAddr[2];
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LPC_EMAC->SA2 = ((uint32_t)abStationAddr[1] << 8) | (uint32_t)abStationAddr[0];
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}
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/*********************************************************************//**
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* @brief Calculates CRC code for number of bytes in the frame
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* @param[in] frame_no_fcs Pointer to the first byte of the frame
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* @param[in] frame_len length of the frame without the FCS
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* @return the CRC as a 32 bit integer
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**********************************************************************/
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static int32_t emac_CRCCalc(uint8_t frame_no_fcs[], int32_t frame_len)
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{
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int i; // iterator
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int j; // another iterator
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char byte; // current byte
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int crc; // CRC result
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int q0, q1, q2, q3; // temporary variables
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crc = 0xFFFFFFFF;
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for (i = 0; i < frame_len; i++) {
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byte = *frame_no_fcs++;
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for (j = 0; j < 2; j++) {
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if (((crc >> 28) ^ (byte >> 3)) & 0x00000001) {
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q3 = 0x04C11DB7;
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} else {
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q3 = 0x00000000;
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}
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if (((crc >> 29) ^ (byte >> 2)) & 0x00000001) {
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q2 = 0x09823B6E;
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} else {
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q2 = 0x00000000;
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}
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if (((crc >> 30) ^ (byte >> 1)) & 0x00000001) {
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q1 = 0x130476DC;
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} else {
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q1 = 0x00000000;
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}
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if (((crc >> 31) ^ (byte >> 0)) & 0x00000001) {
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q0 = 0x2608EDB8;
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} else {
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q0 = 0x00000000;
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}
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crc = (crc << 4) ^ q3 ^ q2 ^ q1 ^ q0;
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byte >>= 4;
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}
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}
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return crc;
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}
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/* End of Private Functions --------------------------------------------------- */
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/* Public Functions ----------------------------------------------------------- */
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/** @addtogroup EMAC_Public_Functions
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* @{
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*/
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/*********************************************************************//**
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* @brief Initializes the EMAC peripheral according to the specified
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* parameters in the EMAC_ConfigStruct.
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* @param[in] EMAC_ConfigStruct Pointer to a EMAC_CFG_Type structure
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* that contains the configuration information for the
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* specified EMAC peripheral.
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* @return None
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*
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* Note: This function will initialize EMAC module according to procedure below:
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* - Remove the soft reset condition from the MAC
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* - Configure the PHY via the MIIM interface of the MAC
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* - Select RMII mode
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* - Configure the transmit and receive DMA engines, including the descriptor arrays
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* - Configure the host registers (MAC1,MAC2 etc.) in the MAC
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* - Enable the receive and transmit data paths
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* In default state after initializing, only Rx Done and Tx Done interrupt are enabled,
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* all remain interrupts are disabled
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* (Ref. from LPC17xx UM)
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**********************************************************************/
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Status EMAC_Init(EMAC_CFG_Type *EMAC_ConfigStruct)
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{
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/* Initialize the EMAC Ethernet controller. */
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int32_t regv,tout, tmp;
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/* Set up clock and power for Ethernet module */
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CLKPWR_ConfigPPWR (CLKPWR_PCONP_PCENET, ENABLE);
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/* Reset all EMAC internal modules */
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LPC_EMAC->MAC1 = EMAC_MAC1_RES_TX | EMAC_MAC1_RES_MCS_TX | EMAC_MAC1_RES_RX |
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EMAC_MAC1_RES_MCS_RX | EMAC_MAC1_SIM_RES | EMAC_MAC1_SOFT_RES;
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LPC_EMAC->Command = EMAC_CR_REG_RES | EMAC_CR_TX_RES | EMAC_CR_RX_RES | EMAC_CR_PASS_RUNT_FRM;
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/* A short delay after reset. */
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for (tout = 100; tout; tout--);
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/* Initialize MAC control registers. */
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LPC_EMAC->MAC1 = EMAC_MAC1_PASS_ALL;
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LPC_EMAC->MAC2 = EMAC_MAC2_CRC_EN | EMAC_MAC2_PAD_EN;
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LPC_EMAC->MAXF = EMAC_ETH_MAX_FLEN;
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/*
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* Find the clock that close to desired target clock
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*/
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tmp = SystemCoreClock / EMAC_MCFG_MII_MAXCLK;
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for (tout = 0; tout < sizeof (EMAC_clkdiv); tout++){
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if (EMAC_clkdiv[tout] >= tmp) break;
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}
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tout++;
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// Write to MAC configuration register and reset
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LPC_EMAC->MCFG = EMAC_MCFG_CLK_SEL(tout) | EMAC_MCFG_RES_MII;
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// release reset
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LPC_EMAC->MCFG &= ~(EMAC_MCFG_RES_MII);
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LPC_EMAC->CLRT = EMAC_CLRT_DEF;
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LPC_EMAC->IPGR = EMAC_IPGR_P2_DEF;
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/* Enable Reduced MII interface. */
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LPC_EMAC->Command = EMAC_CR_RMII | EMAC_CR_PASS_RUNT_FRM;
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/* Reset Reduced MII Logic. */
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// LPC_EMAC->SUPP = EMAC_SUPP_RES_RMII;
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for (tout = 100; tout; tout--);
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LPC_EMAC->SUPP = 0;
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/* Put the DP83848C in reset mode */
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write_PHY (EMAC_PHY_REG_BMCR, EMAC_PHY_BMCR_RESET);
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/* Wait for hardware reset to end. */
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for (tout = EMAC_PHY_RESP_TOUT; tout>=0; tout--) {
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regv = read_PHY (EMAC_PHY_REG_BMCR);
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if (!(regv & (EMAC_PHY_BMCR_RESET | EMAC_PHY_BMCR_POWERDOWN))) {
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/* Reset complete, device not Power Down. */
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break;
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}
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if (tout == 0){
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// Time out, return ERROR
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return (ERROR);
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}
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}
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// Set PHY mode
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if (EMAC_SetPHYMode(EMAC_ConfigStruct->Mode) < 0){
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return (ERROR);
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}
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// Set EMAC address
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setEmacAddr(EMAC_ConfigStruct->pbEMAC_Addr);
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/* Initialize Tx and Rx DMA Descriptors */
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rx_descr_init ();
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tx_descr_init ();
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// Set Receive Filter register: enable broadcast and multicast
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LPC_EMAC->RxFilterCtrl = EMAC_RFC_MCAST_EN | EMAC_RFC_BCAST_EN | EMAC_RFC_PERFECT_EN;
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/* Enable Rx Done and Tx Done interrupt for EMAC */
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LPC_EMAC->IntEnable = EMAC_INT_RX_DONE | EMAC_INT_TX_DONE;
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/* Reset all interrupts */
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LPC_EMAC->IntClear = 0xFFFF;
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/* Enable receive and transmit mode of MAC Ethernet core */
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LPC_EMAC->Command |= (EMAC_CR_RX_EN | EMAC_CR_TX_EN);
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LPC_EMAC->MAC1 |= EMAC_MAC1_REC_EN;
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return SUCCESS;
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}
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/*********************************************************************//**
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* @brief De-initializes the EMAC peripheral registers to their
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* default reset values.
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* @param[in] None
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* @return None
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**********************************************************************/
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void EMAC_DeInit(void)
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{
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// Disable all interrupt
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LPC_EMAC->IntEnable = 0x00;
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// Clear all pending interrupt
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LPC_EMAC->IntClear = (0xFF) | (EMAC_INT_SOFT_INT | EMAC_INT_WAKEUP);
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/* TurnOff clock and power for Ethernet module */
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CLKPWR_ConfigPPWR (CLKPWR_PCONP_PCENET, DISABLE);
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}
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/*********************************************************************//**
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* @brief Check specified PHY status in EMAC peripheral
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* @param[in] ulPHYState Specified PHY Status Type, should be:
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* - EMAC_PHY_STAT_LINK: Link Status
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* - EMAC_PHY_STAT_SPEED: Speed Status
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* - EMAC_PHY_STAT_DUP: Duplex Status
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* @return Status of specified PHY status (0 or 1).
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* (-1) if error.
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*
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* Note:
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* For EMAC_PHY_STAT_LINK, return value:
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* - 0: Link Down
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* - 1: Link Up
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* For EMAC_PHY_STAT_SPEED, return value:
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* - 0: 10Mbps
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* - 1: 100Mbps
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* For EMAC_PHY_STAT_DUP, return value:
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* - 0: Half-Duplex
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* - 1: Full-Duplex
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**********************************************************************/
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int32_t EMAC_CheckPHYStatus(uint32_t ulPHYState)
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{
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int32_t regv, tmp;
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#ifdef MCB_LPC_1768
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regv = read_PHY (EMAC_PHY_REG_STS);
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switch(ulPHYState){
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case EMAC_PHY_STAT_LINK:
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tmp = (regv & EMAC_PHY_SR_LINK) ? 1 : 0;
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break;
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case EMAC_PHY_STAT_SPEED:
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tmp = (regv & EMAC_PHY_SR_SPEED) ? 0 : 1;
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break;
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case EMAC_PHY_STAT_DUP:
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tmp = (regv & EMAC_PHY_SR_FULL_DUP) ? 1 : 0;
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break;
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#elif defined(IAR_LPC_1768)
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/* Use IAR_LPC_1768 board:
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* FSZ8721BL doesn't have Status Register
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* so we read Basic Mode Status Register (0x01h) instead
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*/
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regv = read_PHY (EMAC_PHY_REG_BMSR);
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switch(ulPHYState){
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case EMAC_PHY_STAT_LINK:
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tmp = (regv & EMAC_PHY_BMSR_LINK_STATUS) ? 1 : 0;
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break;
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case EMAC_PHY_STAT_SPEED:
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tmp = (regv & EMAC_PHY_SR_100_SPEED) ? 1 : 0;
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break;
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case EMAC_PHY_STAT_DUP:
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tmp = (regv & EMAC_PHY_SR_FULL_DUP) ? 1 : 0;
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break;
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#endif
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default:
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tmp = -1;
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break;
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}
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return (tmp);
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}
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/*********************************************************************//**
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* @brief Set specified PHY mode in EMAC peripheral
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* @param[in] ulPHYMode Specified PHY mode, should be:
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* - EMAC_MODE_AUTO
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* - EMAC_MODE_10M_FULL
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* - EMAC_MODE_10M_HALF
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* - EMAC_MODE_100M_FULL
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* - EMAC_MODE_100M_HALF
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* @return Return (0) if no error, otherwise return (-1)
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**********************************************************************/
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int32_t EMAC_SetPHYMode(uint32_t ulPHYMode)
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{
|
|
int32_t id1, id2, tout;
|
|
|
|
/* Check if this is a DP83848C PHY. */
|
|
id1 = read_PHY (EMAC_PHY_REG_IDR1);
|
|
id2 = read_PHY (EMAC_PHY_REG_IDR2);
|
|
|
|
#ifdef MCB_LPC_1768
|
|
if (((id1 << 16) | (id2 & 0xFFF0)) == EMAC_DP83848C_ID) {
|
|
switch(ulPHYMode){
|
|
case EMAC_MODE_AUTO:
|
|
write_PHY (EMAC_PHY_REG_BMCR, EMAC_PHY_AUTO_NEG);
|
|
#elif defined(IAR_LPC_1768) /* Use IAR LPC1768 KickStart board */
|
|
if (((id1 << 16) | id2) == EMAC_KSZ8721BL_ID) {
|
|
/* Configure the PHY device */
|
|
switch(ulPHYMode){
|
|
case EMAC_MODE_AUTO:
|
|
/* Use auto-negotiation about the link speed. */
|
|
write_PHY (EMAC_PHY_REG_BMCR, EMAC_PHY_AUTO_NEG);
|
|
// write_PHY (EMAC_PHY_REG_BMCR, EMAC_PHY_BMCR_AN);
|
|
#endif
|
|
/* Wait to complete Auto_Negotiation */
|
|
for (tout = EMAC_PHY_RESP_TOUT; tout>=0; tout--) {
|
|
|
|
}
|
|
break;
|
|
case EMAC_MODE_10M_FULL:
|
|
/* Connect at 10MBit full-duplex */
|
|
write_PHY (EMAC_PHY_REG_BMCR, EMAC_PHY_FULLD_10M);
|
|
break;
|
|
case EMAC_MODE_10M_HALF:
|
|
/* Connect at 10MBit half-duplex */
|
|
write_PHY (EMAC_PHY_REG_BMCR, EMAC_PHY_HALFD_10M);
|
|
break;
|
|
case EMAC_MODE_100M_FULL:
|
|
/* Connect at 100MBit full-duplex */
|
|
write_PHY (EMAC_PHY_REG_BMCR, EMAC_PHY_FULLD_100M);
|
|
break;
|
|
case EMAC_MODE_100M_HALF:
|
|
/* Connect at 100MBit half-duplex */
|
|
write_PHY (EMAC_PHY_REG_BMCR, EMAC_PHY_HALFD_100M);
|
|
break;
|
|
default:
|
|
// un-supported
|
|
return (-1);
|
|
}
|
|
}
|
|
// It's not correct module ID
|
|
else {
|
|
return (-1);
|
|
}
|
|
|
|
// Update EMAC configuration with current PHY status
|
|
if (EMAC_UpdatePHYStatus() < 0){
|
|
return (-1);
|
|
}
|
|
|
|
// Complete
|
|
return (0);
|
|
}
|
|
|
|
|
|
/*********************************************************************//**
|
|
* @brief Auto-Configures value for the EMAC configuration register to
|
|
* match with current PHY mode
|
|
* @param[in] None
|
|
* @return Return (0) if no error, otherwise return (-1)
|
|
*
|
|
* Note: The EMAC configuration will be auto-configured:
|
|
* - Speed mode.
|
|
* - Half/Full duplex mode
|
|
**********************************************************************/
|
|
int32_t EMAC_UpdatePHYStatus(void)
|
|
{
|
|
int32_t regv, tout;
|
|
|
|
/* Check the link status. */
|
|
#ifdef MCB_LPC_1768
|
|
for (tout = EMAC_PHY_RESP_TOUT; tout>=0; tout--) {
|
|
regv = read_PHY (EMAC_PHY_REG_STS);
|
|
if (regv & EMAC_PHY_SR_LINK) {
|
|
/* Link is on. */
|
|
break;
|
|
}
|
|
if (tout == 0){
|
|
// time out
|
|
return (-1);
|
|
}
|
|
}
|
|
/* Configure Full/Half Duplex mode. */
|
|
if (regv & EMAC_PHY_SR_DUP) {
|
|
/* Full duplex is enabled. */
|
|
LPC_EMAC->MAC2 |= EMAC_MAC2_FULL_DUP;
|
|
LPC_EMAC->Command |= EMAC_CR_FULL_DUP;
|
|
LPC_EMAC->IPGT = EMAC_IPGT_FULL_DUP;
|
|
} else {
|
|
/* Half duplex mode. */
|
|
LPC_EMAC->IPGT = EMAC_IPGT_HALF_DUP;
|
|
}
|
|
if (regv & EMAC_PHY_SR_SPEED) {
|
|
/* 10MBit mode. */
|
|
LPC_EMAC->SUPP = 0;
|
|
} else {
|
|
/* 100MBit mode. */
|
|
LPC_EMAC->SUPP = EMAC_SUPP_SPEED;
|
|
}
|
|
#elif defined(IAR_LPC_1768)
|
|
for (tout = EMAC_PHY_RESP_TOUT; tout>=0; tout--) {
|
|
regv = read_PHY (EMAC_PHY_REG_BMSR);
|
|
if (regv & EMAC_PHY_BMSR_LINK_STATUS) {
|
|
/* Link is on. */
|
|
break;
|
|
}
|
|
if (tout == 0){
|
|
// time out
|
|
return (-1);
|
|
}
|
|
}
|
|
|
|
/* Configure Full/Half Duplex mode. */
|
|
if (regv & EMAC_PHY_SR_FULL_DUP) {
|
|
/* Full duplex is enabled. */
|
|
LPC_EMAC->MAC2 |= EMAC_MAC2_FULL_DUP;
|
|
LPC_EMAC->Command |= EMAC_CR_FULL_DUP;
|
|
LPC_EMAC->IPGT = EMAC_IPGT_FULL_DUP;
|
|
} else {
|
|
/* Half duplex mode. */
|
|
LPC_EMAC->IPGT = EMAC_IPGT_HALF_DUP;
|
|
}
|
|
|
|
/* Configure 100MBit/10MBit mode. */
|
|
if (!(regv & EMAC_PHY_SR_100_SPEED)) {
|
|
/* 10MBit mode. */
|
|
LPC_EMAC->SUPP = 0;
|
|
} else {
|
|
/* 100MBit mode. */
|
|
LPC_EMAC->SUPP = EMAC_SUPP_SPEED;
|
|
}
|
|
#endif
|
|
// Complete
|
|
return (0);
|
|
}
|
|
|
|
|
|
/*********************************************************************//**
|
|
* @brief Enable/Disable hash filter functionality for specified destination
|
|
* MAC address in EMAC module
|
|
* @param[in] dstMAC_addr Pointer to the first MAC destination address, should
|
|
* be 6-bytes length, in order LSB to the MSB
|
|
* @param[in] NewState New State of this command, should be:
|
|
* - ENABLE.
|
|
* - DISABLE.
|
|
* @return None
|
|
*
|
|
* Note:
|
|
* The standard Ethernet cyclic redundancy check (CRC) function is calculated from
|
|
* the 6 byte destination address in the Ethernet frame (this CRC is calculated
|
|
* anyway as part of calculating the CRC of the whole frame), then bits [28:23] out of
|
|
* the 32 bits CRC result are taken to form the hash. The 6 bit hash is used to access
|
|
* the hash table: it is used as an index in the 64 bit HashFilter register that has been
|
|
* programmed with accept values. If the selected accept value is 1, the frame is
|
|
* accepted.
|
|
**********************************************************************/
|
|
void EMAC_SetHashFilter(uint8_t dstMAC_addr[], FunctionalState NewState)
|
|
{
|
|
uint32_t *pReg;
|
|
uint32_t tmp;
|
|
int32_t crc;
|
|
|
|
// Calculate the CRC from the destination MAC address
|
|
crc = emac_CRCCalc(dstMAC_addr, 6);
|
|
// Extract the value from CRC to get index value for hash filter table
|
|
crc = (crc >> 23) & 0x3F;
|
|
|
|
pReg = (crc > 31) ? ((uint32_t *)&LPC_EMAC->HashFilterH) \
|
|
: ((uint32_t *)&LPC_EMAC->HashFilterL);
|
|
tmp = (crc > 31) ? (crc - 32) : crc;
|
|
if (NewState == ENABLE) {
|
|
(*pReg) |= (1UL << tmp);
|
|
} else {
|
|
(*pReg) &= ~(1UL << tmp);
|
|
}
|
|
// Enable Rx Filter
|
|
LPC_EMAC->Command &= ~EMAC_CR_PASS_RX_FILT;
|
|
}
|
|
|
|
/*********************************************************************//**
|
|
* @brief Enable/Disable Filter mode for each specified type EMAC peripheral
|
|
* @param[in] ulFilterMode Filter mode, should be:
|
|
* - EMAC_RFC_UCAST_EN: all frames of unicast types
|
|
* will be accepted
|
|
* - EMAC_RFC_BCAST_EN: broadcast frame will be
|
|
* accepted
|
|
* - EMAC_RFC_MCAST_EN: all frames of multicast
|
|
* types will be accepted
|
|
* - EMAC_RFC_UCAST_HASH_EN: The imperfect hash
|
|
* filter will be applied to unicast addresses
|
|
* - EMAC_RFC_MCAST_HASH_EN: The imperfect hash
|
|
* filter will be applied to multicast addresses
|
|
* - EMAC_RFC_PERFECT_EN: the destination address
|
|
* will be compared with the 6 byte station address
|
|
* programmed in the station address by the filter
|
|
* - EMAC_RFC_MAGP_WOL_EN: the result of the magic
|
|
* packet filter will generate a WoL interrupt when
|
|
* there is a match
|
|
* - EMAC_RFC_PFILT_WOL_EN: the result of the perfect address
|
|
* matching filter and the imperfect hash filter will
|
|
* generate a WoL interrupt when there is a match
|
|
* @param[in] NewState New State of this command, should be:
|
|
* - ENABLE
|
|
* - DISABLE
|
|
* @return None
|
|
**********************************************************************/
|
|
void EMAC_SetFilterMode(uint32_t ulFilterMode, FunctionalState NewState)
|
|
{
|
|
if (NewState == ENABLE){
|
|
LPC_EMAC->RxFilterCtrl |= ulFilterMode;
|
|
} else {
|
|
LPC_EMAC->RxFilterCtrl &= ~ulFilterMode;
|
|
}
|
|
}
|
|
|
|
/*********************************************************************//**
|
|
* @brief Get status of Wake On LAN Filter for each specified
|
|
* type in EMAC peripheral, clear this status if it is set
|
|
* @param[in] ulWoLMode WoL Filter mode, should be:
|
|
* - EMAC_WOL_UCAST: unicast frames caused WoL
|
|
* - EMAC_WOL_UCAST: broadcast frame caused WoL
|
|
* - EMAC_WOL_MCAST: multicast frame caused WoL
|
|
* - EMAC_WOL_UCAST_HASH: unicast frame that passes the
|
|
* imperfect hash filter caused WoL
|
|
* - EMAC_WOL_MCAST_HASH: multicast frame that passes the
|
|
* imperfect hash filter caused WoL
|
|
* - EMAC_WOL_PERFECT:perfect address matching filter
|
|
* caused WoL
|
|
* - EMAC_WOL_RX_FILTER: the receive filter caused WoL
|
|
* - EMAC_WOL_MAG_PACKET: the magic packet filter caused WoL
|
|
* @return SET/RESET
|
|
**********************************************************************/
|
|
FlagStatus EMAC_GetWoLStatus(uint32_t ulWoLMode)
|
|
{
|
|
if (LPC_EMAC->RxFilterWoLStatus & ulWoLMode) {
|
|
LPC_EMAC->RxFilterWoLClear = ulWoLMode;
|
|
return SET;
|
|
} else {
|
|
return RESET;
|
|
}
|
|
}
|
|
|
|
|
|
/*********************************************************************//**
|
|
* @brief Write data to Tx packet data buffer at current index due to
|
|
* TxProduceIndex
|
|
* @param[in] pDataStruct Pointer to a EMAC_PACKETBUF_Type structure
|
|
* data that contain specified information about
|
|
* Packet data buffer.
|
|
* @return None
|
|
**********************************************************************/
|
|
void EMAC_WritePacketBuffer(EMAC_PACKETBUF_Type *pDataStruct)
|
|
{
|
|
uint32_t idx,len;
|
|
uint32_t *sp,*dp;
|
|
|
|
idx = LPC_EMAC->TxProduceIndex;
|
|
sp = (uint32_t *)pDataStruct->pbDataBuf;
|
|
dp = (uint32_t *)Tx_Desc[idx].Packet;
|
|
/* Copy frame data to EMAC packet buffers. */
|
|
for (len = (pDataStruct->ulDataLen + 3) >> 2; len; len--) {
|
|
*dp++ = *sp++;
|
|
}
|
|
Tx_Desc[idx].Ctrl = (pDataStruct->ulDataLen - 1) | (EMAC_TCTRL_INT | EMAC_TCTRL_LAST);
|
|
}
|
|
|
|
/*********************************************************************//**
|
|
* @brief Read data from Rx packet data buffer at current index due
|
|
* to RxConsumeIndex
|
|
* @param[in] pDataStruct Pointer to a EMAC_PACKETBUF_Type structure
|
|
* data that contain specified information about
|
|
* Packet data buffer.
|
|
* @return None
|
|
**********************************************************************/
|
|
void EMAC_ReadPacketBuffer(EMAC_PACKETBUF_Type *pDataStruct)
|
|
{
|
|
uint32_t idx, len;
|
|
uint32_t *dp, *sp;
|
|
|
|
idx = LPC_EMAC->RxConsumeIndex;
|
|
dp = (uint32_t *)pDataStruct->pbDataBuf;
|
|
sp = (uint32_t *)Rx_Desc[idx].Packet;
|
|
|
|
if (pDataStruct->pbDataBuf != NULL) {
|
|
for (len = (pDataStruct->ulDataLen + 3) >> 2; len; len--) {
|
|
*dp++ = *sp++;
|
|
}
|
|
}
|
|
}
|
|
|
|
/*********************************************************************//**
|
|
* @brief Enable/Disable interrupt for each type in EMAC
|
|
* @param[in] ulIntType Interrupt Type, should be:
|
|
* - EMAC_INT_RX_OVERRUN: Receive Overrun
|
|
* - EMAC_INT_RX_ERR: Receive Error
|
|
* - EMAC_INT_RX_FIN: Receive Descriptor Finish
|
|
* - EMAC_INT_RX_DONE: Receive Done
|
|
* - EMAC_INT_TX_UNDERRUN: Transmit Under-run
|
|
* - EMAC_INT_TX_ERR: Transmit Error
|
|
* - EMAC_INT_TX_FIN: Transmit descriptor finish
|
|
* - EMAC_INT_TX_DONE: Transmit Done
|
|
* - EMAC_INT_SOFT_INT: Software interrupt
|
|
* - EMAC_INT_WAKEUP: Wakeup interrupt
|
|
* @param[in] NewState New State of this function, should be:
|
|
* - ENABLE.
|
|
* - DISABLE.
|
|
* @return None
|
|
**********************************************************************/
|
|
void EMAC_IntCmd(uint32_t ulIntType, FunctionalState NewState)
|
|
{
|
|
if (NewState == ENABLE) {
|
|
LPC_EMAC->IntEnable |= ulIntType;
|
|
} else {
|
|
LPC_EMAC->IntEnable &= ~(ulIntType);
|
|
}
|
|
}
|
|
|
|
/*********************************************************************//**
|
|
* @brief Check whether if specified interrupt flag is set or not
|
|
* for each interrupt type in EMAC and clear interrupt pending
|
|
* if it is set.
|
|
* @param[in] ulIntType Interrupt Type, should be:
|
|
* - EMAC_INT_RX_OVERRUN: Receive Overrun
|
|
* - EMAC_INT_RX_ERR: Receive Error
|
|
* - EMAC_INT_RX_FIN: Receive Descriptor Finish
|
|
* - EMAC_INT_RX_DONE: Receive Done
|
|
* - EMAC_INT_TX_UNDERRUN: Transmit Under-run
|
|
* - EMAC_INT_TX_ERR: Transmit Error
|
|
* - EMAC_INT_TX_FIN: Transmit descriptor finish
|
|
* - EMAC_INT_TX_DONE: Transmit Done
|
|
* - EMAC_INT_SOFT_INT: Software interrupt
|
|
* - EMAC_INT_WAKEUP: Wakeup interrupt
|
|
* @return New state of specified interrupt (SET or RESET)
|
|
**********************************************************************/
|
|
IntStatus EMAC_IntGetStatus(uint32_t ulIntType)
|
|
{
|
|
if (LPC_EMAC->IntStatus & ulIntType) {
|
|
LPC_EMAC->IntClear = ulIntType;
|
|
return SET;
|
|
} else {
|
|
return RESET;
|
|
}
|
|
}
|
|
|
|
|
|
/*********************************************************************//**
|
|
* @brief Check whether if the current RxConsumeIndex is not equal to the
|
|
* current RxProduceIndex.
|
|
* @param[in] None
|
|
* @return TRUE if they're not equal, otherwise return FALSE
|
|
*
|
|
* Note: In case the RxConsumeIndex is not equal to the RxProduceIndex,
|
|
* it means there're available data has been received. They should be read
|
|
* out and released the Receive Data Buffer by updating the RxConsumeIndex value.
|
|
**********************************************************************/
|
|
Bool EMAC_CheckReceiveIndex(void)
|
|
{
|
|
if (LPC_EMAC->RxConsumeIndex != LPC_EMAC->RxProduceIndex) {
|
|
return TRUE;
|
|
} else {
|
|
return FALSE;
|
|
}
|
|
}
|
|
|
|
|
|
/*********************************************************************//**
|
|
* @brief Check whether if the current TxProduceIndex is not equal to the
|
|
* current RxProduceIndex - 1.
|
|
* @param[in] None
|
|
* @return TRUE if they're not equal, otherwise return FALSE
|
|
*
|
|
* Note: In case the RxConsumeIndex is equal to the RxProduceIndex - 1,
|
|
* it means the transmit buffer is available and data can be written to transmit
|
|
* buffer to be sent.
|
|
**********************************************************************/
|
|
Bool EMAC_CheckTransmitIndex(void)
|
|
{
|
|
uint32_t tmp = LPC_EMAC->TxConsumeIndex;
|
|
if (LPC_EMAC->TxProduceIndex == ( tmp - 1 ))
|
|
{
|
|
return FALSE;
|
|
}
|
|
else if( ( tmp == 0 ) && ( LPC_EMAC->TxProduceIndex == ( EMAC_NUM_TX_FRAG - 1 ) ) )
|
|
{
|
|
return FALSE;
|
|
}
|
|
else
|
|
{
|
|
return TRUE;
|
|
}
|
|
}
|
|
|
|
|
|
|
|
/*********************************************************************//**
|
|
* @brief Get current status value of receive data (due to RxConsumeIndex)
|
|
* @param[in] ulRxStatType Received Status type, should be one of following:
|
|
* - EMAC_RINFO_CTRL_FRAME: Control Frame
|
|
* - EMAC_RINFO_VLAN: VLAN Frame
|
|
* - EMAC_RINFO_FAIL_FILT: RX Filter Failed
|
|
* - EMAC_RINFO_MCAST: Multicast Frame
|
|
* - EMAC_RINFO_BCAST: Broadcast Frame
|
|
* - EMAC_RINFO_CRC_ERR: CRC Error in Frame
|
|
* - EMAC_RINFO_SYM_ERR: Symbol Error from PHY
|
|
* - EMAC_RINFO_LEN_ERR: Length Error
|
|
* - EMAC_RINFO_RANGE_ERR: Range error(exceeded max size)
|
|
* - EMAC_RINFO_ALIGN_ERR: Alignment error
|
|
* - EMAC_RINFO_OVERRUN: Receive overrun
|
|
* - EMAC_RINFO_NO_DESCR: No new Descriptor available
|
|
* - EMAC_RINFO_LAST_FLAG: last Fragment in Frame
|
|
* - EMAC_RINFO_ERR: Error Occurred (OR of all error)
|
|
* @return Current value of receive data (due to RxConsumeIndex)
|
|
**********************************************************************/
|
|
FlagStatus EMAC_CheckReceiveDataStatus(uint32_t ulRxStatType)
|
|
{
|
|
uint32_t idx;
|
|
idx = LPC_EMAC->RxConsumeIndex;
|
|
return (((Rx_Stat[idx].Info) & ulRxStatType) ? SET : RESET);
|
|
}
|
|
|
|
|
|
/*********************************************************************//**
|
|
* @brief Get size of current Received data in received buffer (due to
|
|
* RxConsumeIndex)
|
|
* @param[in] None
|
|
* @return Size of received data
|
|
**********************************************************************/
|
|
uint32_t EMAC_GetReceiveDataSize(void)
|
|
{
|
|
uint32_t idx;
|
|
idx =LPC_EMAC->RxConsumeIndex;
|
|
return ((Rx_Stat[idx].Info) & EMAC_RINFO_SIZE);
|
|
}
|
|
|
|
/*********************************************************************//**
|
|
* @brief Increase the RxConsumeIndex (after reading the Receive buffer
|
|
* to release the Receive buffer) and wrap-around the index if
|
|
* it reaches the maximum Receive Number
|
|
* @param[in] None
|
|
* @return None
|
|
**********************************************************************/
|
|
void EMAC_UpdateRxConsumeIndex(void)
|
|
{
|
|
// Get current Rx consume index
|
|
uint32_t idx = LPC_EMAC->RxConsumeIndex;
|
|
|
|
/* Release frame from EMAC buffer */
|
|
if (++idx == EMAC_NUM_RX_FRAG) idx = 0;
|
|
LPC_EMAC->RxConsumeIndex = idx;
|
|
}
|
|
|
|
/*********************************************************************//**
|
|
* @brief Increase the TxProduceIndex (after writting to the Transmit buffer
|
|
* to enable the Transmit buffer) and wrap-around the index if
|
|
* it reaches the maximum Transmit Number
|
|
* @param[in] None
|
|
* @return None
|
|
**********************************************************************/
|
|
void EMAC_UpdateTxProduceIndex(void)
|
|
{
|
|
// Get current Tx produce index
|
|
uint32_t idx = LPC_EMAC->TxProduceIndex;
|
|
|
|
/* Start frame transmission */
|
|
if (++idx == EMAC_NUM_TX_FRAG) idx = 0;
|
|
LPC_EMAC->TxProduceIndex = idx;
|
|
}
|
|
|
|
|
|
/**
|
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* @}
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*/
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#endif /* _EMAC */
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/**
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* @}
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*/
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/* --------------------------------- End Of File ------------------------------ */
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