302 lines
9.1 KiB
C
302 lines
9.1 KiB
C
/**********************************************************************
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* $Id$ lpc_phy_lan8720.c 2011-11-20
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*//**
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* @file lpc_phy_lan8720.c
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* @brief LAN8720 PHY status and control.
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* @version 1.0
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* @date 20 Nov. 2011
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* @author NXP MCU SW Application Team
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*
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* Copyright(C) 2011, NXP Semiconductor
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* All rights reserved.
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*
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***********************************************************************
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* Software that is described herein is for illustrative purposes only
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* which provides customers with programming information regarding the
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* products. This software is supplied "AS IS" without any warranties.
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* NXP Semiconductors assumes no responsibility or liability for the
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* use of the software, conveys no license or title under any patent,
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* copyright, or mask work right to the product. NXP Semiconductors
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* reserves the right to make changes in the software without
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* notification. NXP Semiconductors also make no representation or
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* warranty that such application will be suitable for the specified
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* use without further testing or modification.
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**********************************************************************/
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#include "lwip/opt.h"
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#include "lwip/err.h"
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#include "lwip/tcpip.h"
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#include "lwip/snmp.h"
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#include "boards/board.h"
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#include "arch/lpc_arch.h" // FIXME Ethernet
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#include "lpc_phy.h"
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/** @defgroup lan8720_phy PHY status and control for the LAN8720.
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* @ingroup lwip_phy
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*
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* Various functions for controlling and monitoring the status of the
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* LAN8720 PHY. In polled (standalone) systems, the PHY state must be
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* monitored as part of the application. In a threaded (RTOS) system,
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* the PHY state is monitored by the PHY handler thread. The MAC
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* driver will not transmit unless the PHY link is active.
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* @{
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*/
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/** \brief LAN8720 PHY register offsets */
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#define LAN8_BCR_REG 0x0 /**< Basic Control Register */
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#define LAN8_BSR_REG 0x1 /**< Basic Status Reg */
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#define LAN8_PHYID1_REG 0x2 /**< PHY ID 1 Reg */
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#define LAN8_PHYID2_REG 0x3 /**< PHY ID 2 Reg */
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#define LAN8_PHYSPLCTL_REG 0x1F /**< PHY special control/status Reg */
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/* LAN8720 BCR register definitions */
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#define LAN8_RESET (1 << 15) /**< 1= S/W Reset */
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#define LAN8_LOOPBACK (1 << 14) /**< 1=loopback Enabled */
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#define LAN8_SPEED_SELECT (1 << 13) /**< 1=Select 100MBps */
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#define LAN8_AUTONEG (1 << 12) /**< 1=Enable auto-negotiation */
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#define LAN8_POWER_DOWN (1 << 11) /**< 1=Power down PHY */
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#define LAN8_ISOLATE (1 << 10) /**< 1=Isolate PHY */
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#define LAN8_RESTART_AUTONEG (1 << 9) /**< 1=Restart auto-negoatiation */
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#define LAN8_DUPLEX_MODE (1 << 8) /**< 1=Full duplex mode */
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/* LAN8720 BSR register definitions */
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#define LAN8_100BASE_T4 (1 << 15) /**< T4 mode */
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#define LAN8_100BASE_TX_FD (1 << 14) /**< 100MBps full duplex */
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#define LAN8_100BASE_TX_HD (1 << 13) /**< 100MBps half duplex */
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#define LAN8_10BASE_T_FD (1 << 12) /**< 100Bps full duplex */
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#define LAN8_10BASE_T_HD (1 << 11) /**< 10MBps half duplex */
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#define LAN8_AUTONEG_COMP (1 << 5) /**< Auto-negotation complete */
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#define LAN8_RMT_FAULT (1 << 4) /**< Fault */
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#define LAN8_AUTONEG_ABILITY (1 << 3) /**< Auto-negotation supported */
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#define LAN8_LINK_STATUS (1 << 2) /**< 1=Link active */
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#define LAN8_JABBER_DETECT (1 << 1) /**< Jabber detect */
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#define LAN8_EXTEND_CAPAB (1 << 0) /**< Supports extended capabilities */
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/* LAN8720 PHYSPLCTL status definitions */
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#define LAN8_SPEEDMASK (7 << 2) /**< Speed and duplex mask */
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#define LAN8_SPEED100F (6 << 2) /**< 100BT full duplex */
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#define LAN8_SPEED10F (5 << 2) /**< 10BT full duplex */
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#define LAN8_SPEED100H (2 << 2) /**< 100BT half duplex */
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#define LAN8_SPEED10H (1 << 2) /**< 10BT half duplex */
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/* LAN8720 PHY ID 1/2 register definitions */
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#define LAN8_PHYID1_OUI 0x0007 /**< Expected PHY ID1 */
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#define LAN8_PHYID2_OUI 0xC0F0 /**< Expected PHY ID2, except last 4 bits */
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/**
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* @brief PHY status structure used to indicate current status of PHY.
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*/
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typedef struct {
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u32_t phy_speed_100mbs:2; /**< 10/100 MBS connection speed flag. */
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u32_t phy_full_duplex:2; /**< Half/full duplex connection speed flag. */
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u32_t phy_link_active:2; /**< Phy link active flag. */
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} PHY_STATUS_TYPE;
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/** \brief PHY update flags */
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static PHY_STATUS_TYPE physts;
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/** \brief Last PHY update flags, used for determing if something has changed */
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static PHY_STATUS_TYPE olddphysts;
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/** \brief PHY update counter for state machine */
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static s32_t phyustate;
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/** \brief Update PHY status from passed value
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*
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* This function updates the current PHY status based on the
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* passed PHY status word. The PHY status indicate if the link
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* is active, the connection speed, and duplex.
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*
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* \param[in] netif NETIF structure
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* \param[in] linksts Status word with link state
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* \param[in] sdsts Status word with speed and duplex states
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* \return 1 if the status has changed, otherwise 0
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*/
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static s32_t lpc_update_phy_sts(struct netif *netif, u32_t linksts, u32_t sdsts)
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{
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s32_t changed = 0;
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/* Update link active status */
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if (linksts & LAN8_LINK_STATUS)
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physts.phy_link_active = 1;
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else
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physts.phy_link_active = 0;
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switch (sdsts & LAN8_SPEEDMASK) {
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case LAN8_SPEED100F:
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default:
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physts.phy_speed_100mbs = 1;
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physts.phy_full_duplex = 1;
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break;
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case LAN8_SPEED10F:
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physts.phy_speed_100mbs = 0;
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physts.phy_full_duplex = 1;
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break;
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case LAN8_SPEED100H:
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physts.phy_speed_100mbs = 1;
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physts.phy_full_duplex = 0;
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break;
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case LAN8_SPEED10H:
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physts.phy_speed_100mbs = 0;
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physts.phy_full_duplex = 0;
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break;
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}
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if (physts.phy_speed_100mbs != olddphysts.phy_speed_100mbs) {
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changed = 1;
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if (physts.phy_speed_100mbs) {
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/* 100MBit mode. */
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lpc_emac_set_speed(1);
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NETIF_INIT_SNMP(netif, snmp_ifType_ethernet_csmacd, 100000000);
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}
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else {
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/* 10MBit mode. */
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lpc_emac_set_speed(0);
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NETIF_INIT_SNMP(netif, snmp_ifType_ethernet_csmacd, 10000000);
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}
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olddphysts.phy_speed_100mbs = physts.phy_speed_100mbs;
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}
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if (physts.phy_full_duplex != olddphysts.phy_full_duplex) {
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changed = 1;
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if (physts.phy_full_duplex)
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lpc_emac_set_duplex(1);
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else
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lpc_emac_set_duplex(0);
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olddphysts.phy_full_duplex = physts.phy_full_duplex;
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}
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if (physts.phy_link_active != olddphysts.phy_link_active) {
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changed = 1;
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#if NO_SYS == 1
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if (physts.phy_link_active)
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netif_set_link_up(netif);
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else
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netif_set_link_down(netif);
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#else
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if (physts.phy_link_active)
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tcpip_callback_with_block((tcpip_callback_fn) netif_set_link_up,
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(void*) netif, 1);
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else
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tcpip_callback_with_block((tcpip_callback_fn) netif_set_link_down,
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(void*) netif, 1);
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#endif
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olddphysts.phy_link_active = physts.phy_link_active;
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}
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return changed;
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}
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/** \brief Initialize the LAN8720 PHY.
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*
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* This function initializes the LAN8720 PHY. It will block until
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* complete. This function is called as part of the EMAC driver
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* initialization. Configuration of the PHY at startup is
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* controlled by setting up configuration defines in
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* lpc_emac_config.h.
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*
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* \param[in] netif NETIF structure
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* \param[in] rmii If set, configures the PHY for RMII mode
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* \return ERR_OK if the setup was successful, otherwise ERR_TIMEOUT
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*/
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err_t lpc_phy_init(struct netif *netif, int rmii)
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{
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u32_t tmp, tmp1;
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s32_t i;
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physts.phy_speed_100mbs = olddphysts.phy_speed_100mbs = 2;
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physts.phy_full_duplex = olddphysts.phy_full_duplex = 2;
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physts.phy_link_active = olddphysts.phy_link_active = 2;
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phyustate = 0;
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/* Only first read and write are checked for failure */
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/* Put the LAN8720 in reset mode and wait for completion */
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if (lpc_mii_write(LAN8_BCR_REG, LAN8_RESET) != 0)
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return ERR_TIMEOUT;
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i = 400;
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while (i > 0) {
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msDelay(1); /* 1 ms */
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if (lpc_mii_read(LAN8_BCR_REG, &tmp) != 0)
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return ERR_TIMEOUT;
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if (!(tmp & (LAN8_RESET | LAN8_POWER_DOWN)))
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i = -1;
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else
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i--;
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}
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/* Timeout? */
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if (i == 0)
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return ERR_TIMEOUT;
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/* Setup link based on configuration options */
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#if PHY_USE_AUTONEG==1
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tmp = LAN8_AUTONEG;
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#else
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tmp = 0;
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#endif
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#if PHY_USE_100MBS==1
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tmp |= LAN8_SPEED_SELECT;
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#endif
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#if PHY_USE_FULL_DUPLEX==1
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tmp |= LAN8_DUPLEX_MODE;
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#endif
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lpc_mii_write(LAN8_BCR_REG, tmp);
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/* The link is not set active at this point, but will be detected
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later */
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return ERR_OK;
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}
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/* Phy status update state machine */
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s32_t lpc_phy_sts_sm(struct netif *netif)
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{
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static u32_t sts;
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s32_t changed = 0;
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switch (phyustate) {
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default:
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case 0:
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/* Read BMSR to clear faults */
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lpc_mii_read_noblock(LAN8_BSR_REG);
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phyustate = 1;
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break;
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case 1:
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/* Wait for read status state */
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if (!lpc_mii_is_busy()) {
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/* Get PHY status with link state */
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sts = lpc_mii_read_data();
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lpc_mii_read_noblock(LAN8_PHYSPLCTL_REG);
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phyustate = 2;
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}
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break;
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case 2:
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/* Wait for read status state */
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if (!lpc_mii_is_busy()) {
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/* Update PHY status */
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changed = lpc_update_phy_sts(netif, sts, lpc_mii_read_data());
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phyustate = 0;
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}
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break;
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}
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return changed;
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}
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/**
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* @}
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*/
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/* --------------------------------- End Of File ------------------------------ */
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