40 lines
1.0 KiB
C
40 lines
1.0 KiB
C
#ifndef __F1C100S_RESET_H__
|
|
#define __F1C100S_RESET_H__
|
|
|
|
#ifdef __cplusplus
|
|
extern "C" {
|
|
#endif
|
|
|
|
#define F1C100S_RESET_DMA (6)
|
|
#define F1C100S_RESET_SD0 (8)
|
|
#define F1C100S_RESET_SD1 (9)
|
|
#define F1C100S_RESET_SDRAM (14)
|
|
#define F1C100S_RESET_SPI0 (20)
|
|
#define F1C100S_RESET_SPI1 (21)
|
|
#define F1C100S_RESET_USB_OTG (24)
|
|
#define F1C100S_RESET_VE (32)
|
|
#define F1C100S_RESET_LCD (36)
|
|
#define F1C100S_RESET_DEINTERLACE (37)
|
|
#define F1C100S_RESET_CSI (40)
|
|
#define F1C100S_RESET_TVD (41)
|
|
#define F1C100S_RESET_TVE (42)
|
|
#define F1C100S_RESET_DEBE (44)
|
|
#define F1C100S_RESET_DEFE (46)
|
|
#define F1C100S_RESET_ADDA (64)
|
|
#define F1C100S_RESET_SPDIF (65)
|
|
#define F1C100S_RESET_CIR (66)
|
|
#define F1C100S_RESET_RSB (67)
|
|
#define F1C100S_RESET_DAUDIO (76)
|
|
#define F1C100S_RESET_I2C0 (80)
|
|
#define F1C100S_RESET_I2C1 (81)
|
|
#define F1C100S_RESET_I2C2 (82)
|
|
#define F1C100S_RESET_UART0 (84)
|
|
#define F1C100S_RESET_UART1 (85)
|
|
#define F1C100S_RESET_UART2 (86)
|
|
|
|
#ifdef __cplusplus
|
|
}
|
|
#endif
|
|
|
|
#endif /* __F1C100S_RESET_H__ */
|