62 lines
1.9 KiB
C
62 lines
1.9 KiB
C
/*
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* Licensed to the Apache Software Foundation (ASF) under one
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* or more contributor license agreements. See the NOTICE file
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* distributed with this work for additional information
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* regarding copyright ownership. The ASF licenses this file
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* to you under the Apache License, Version 2.0 (the
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* "License"); you may not use this file except in compliance
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* with the License. You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing,
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* software distributed under the License is distributed on an
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* "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
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* KIND, either express or implied. See the License for the
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* specific language governing permissions and limitations
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* under the License.
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*/
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#include "mcu/mcu.h"
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#include <mcu/da1469x_clock.h>
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extern uint8_t __StackLimit;
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uint32_t SystemCoreClock = 32000000;
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void
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SystemInit(void)
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{
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/* Enable FPU when using hard-float */
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#if (__FPU_USED == 1)
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SCB->CPACR |= (3UL << 20) | (3UL << 22);
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__DSB();
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__ISB();
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#endif
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/* Freeze watchdog */
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GPREG->SET_FREEZE_REG |= GPREG_SET_FREEZE_REG_FRZ_SYS_WDOG_Msk;
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/* Initialize power domains (disable radio only) */
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CRG_TOP->PMU_CTRL_REG = CRG_TOP_PMU_CTRL_REG_RADIO_SLEEP_Msk;
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CRG_TOP->P0_SET_PAD_LATCH_REG = CRG_TOP_P0_PAD_LATCH_REG_P0_LATCH_EN_Msk;
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CRG_TOP->P1_SET_PAD_LATCH_REG = CRG_TOP_P1_PAD_LATCH_REG_P1_LATCH_EN_Msk;
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/* Reset clock dividers to 0 */
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CRG_TOP->CLK_AMBA_REG &= ~(CRG_TOP_CLK_AMBA_REG_HCLK_DIV_Msk | CRG_TOP_CLK_AMBA_REG_PCLK_DIV_Msk);
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/* PD_TIM is already started in SystemInit */
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da1469x_clock_sys_xtal32m_init();
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da1469x_clock_sys_xtal32m_enable();
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da1469x_clock_sys_pll_enable();
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da1469x_clock_pll_wait_to_lock();
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/* Switch to XTAL32M and disable RC32M */
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da1469x_clock_sys_xtal32m_switch_safe();
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da1469x_clock_sys_rc32m_disable();
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}
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void _init(void)
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{
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}
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