452 lines
17 KiB
C
452 lines
17 KiB
C
/**********************************************************************
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* $Id$ lpc43xx_ssp.h 2011-06-02
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*//**
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* @file lpc43xx_ssp.h
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* @brief Contains all macro definitions and function prototypes
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* support for SSP firmware library on lpc43xx
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* @version 1.0
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* @date 02. June. 2011
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* @author NXP MCU SW Application Team
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*
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* Copyright(C) 2011, NXP Semiconductor
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* All rights reserved.
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*
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***********************************************************************
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* Software that is described herein is for illustrative purposes only
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* which provides customers with programming information regarding the
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* products. This software is supplied "AS IS" without any warranties.
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* NXP Semiconductors assumes no responsibility or liability for the
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* use of the software, conveys no license or title under any patent,
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* copyright, or mask work right to the product. NXP Semiconductors
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* reserves the right to make changes in the software without
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* notification. NXP Semiconductors also make no representation or
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* warranty that such application will be suitable for the specified
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* use without further testing or modification.
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* Permission to use, copy, modify, and distribute this software and its
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* documentation is hereby granted, under NXP Semiconductors<72>
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* relevant copyright in the software, without fee, provided that it
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* is used in conjunction with NXP Semiconductors microcontrollers. This
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* copyright, permission, and disclaimer notice must appear in all copies of
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* this code.
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**********************************************************************/
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/* Peripheral group ----------------------------------------------------------- */
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/** @defgroup SSP SSP (Synchronous Serial Port)
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* @ingroup LPC4300CMSIS_FwLib_Drivers
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* @{
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*/
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#ifndef lpc43xx_SSP_H_
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#define lpc43xx_SSP_H_
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/* Includes ------------------------------------------------------------------- */
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#include "LPC43xx.h"
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#include "lpc_types.h"
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#ifdef __cplusplus
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extern "C"
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{
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#endif
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/* Public Macros -------------------------------------------------------------- */
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/** @defgroup SSP_Private_Macros SSP Private Macros
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* @{
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*/
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/*********************************************************************//**
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* SSP configuration parameter defines
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**********************************************************************/
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/** Clock phase control bit */
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#define SSP_CPHA_FIRST ((uint32_t)(0))
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#define SSP_CPHA_SECOND SSP_CR0_CPHA_SECOND
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/** Clock polarity control bit */
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/* There's no bug here!!!
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* - If bit[6] in SSPnCR0 is 0: SSP controller maintains the bus clock low between frames.
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* That means the active clock is in HI state.
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* - If bit[6] in SSPnCR0 is 1 (SSP_CR0_CPOL_HI): SSP controller maintains the bus clock
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* high between frames. That means the active clock is in LO state.
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*/
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#define SSP_CPOL_HI ((uint32_t)(0))
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#define SSP_CPOL_LO SSP_CR0_CPOL_HI
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/** SSP master mode enable */
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#define SSP_SLAVE_MODE SSP_CR1_SLAVE_EN
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#define SSP_MASTER_MODE ((uint32_t)(0))
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/** SSP data bit number defines */
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#define SSP_DATABIT_4 SSP_CR0_DSS(4) /*!< Databit number = 4 */
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#define SSP_DATABIT_5 SSP_CR0_DSS(5) /*!< Databit number = 5 */
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#define SSP_DATABIT_6 SSP_CR0_DSS(6) /*!< Databit number = 6 */
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#define SSP_DATABIT_7 SSP_CR0_DSS(7) /*!< Databit number = 7 */
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#define SSP_DATABIT_8 SSP_CR0_DSS(8) /*!< Databit number = 8 */
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#define SSP_DATABIT_9 SSP_CR0_DSS(9) /*!< Databit number = 9 */
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#define SSP_DATABIT_10 SSP_CR0_DSS(10) /*!< Databit number = 10 */
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#define SSP_DATABIT_11 SSP_CR0_DSS(11) /*!< Databit number = 11 */
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#define SSP_DATABIT_12 SSP_CR0_DSS(12) /*!< Databit number = 12 */
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#define SSP_DATABIT_13 SSP_CR0_DSS(13) /*!< Databit number = 13 */
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#define SSP_DATABIT_14 SSP_CR0_DSS(14) /*!< Databit number = 14 */
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#define SSP_DATABIT_15 SSP_CR0_DSS(15) /*!< Databit number = 15 */
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#define SSP_DATABIT_16 SSP_CR0_DSS(16) /*!< Databit number = 16 */
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/** SSP Frame Format definition */
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/** Motorola SPI mode */
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#define SSP_FRAME_SPI SSP_CR0_FRF_SPI
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/** TI synchronous serial mode */
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#define SSP_FRAME_TI SSP_CR0_FRF_TI
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/** National Micro-wire mode */
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#define SSP_FRAME_MICROWIRE SSP_CR0_FRF_MICROWIRE
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/*********************************************************************//**
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* SSP Status defines
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**********************************************************************/
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/** SSP status TX FIFO Empty bit */
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#define SSP_STAT_TXFIFO_EMPTY SSP_SR_TFE
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/** SSP status TX FIFO not full bit */
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#define SSP_STAT_TXFIFO_NOTFULL SSP_SR_TNF
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/** SSP status RX FIFO not empty bit */
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#define SSP_STAT_RXFIFO_NOTEMPTY SSP_SR_RNE
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/** SSP status RX FIFO full bit */
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#define SSP_STAT_RXFIFO_FULL SSP_SR_RFF
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/** SSP status SSP Busy bit */
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#define SSP_STAT_BUSY SSP_SR_BSY
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/*********************************************************************//**
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* SSP Interrupt Configuration defines
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**********************************************************************/
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/** Receive Overrun */
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#define SSP_INTCFG_ROR SSP_IMSC_ROR
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/** Receive TimeOut */
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#define SSP_INTCFG_RT SSP_IMSC_RT
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/** Rx FIFO is at least half full */
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#define SSP_INTCFG_RX SSP_IMSC_RX
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/** Tx FIFO is at least half empty */
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#define SSP_INTCFG_TX SSP_IMSC_TX
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/*********************************************************************//**
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* SSP Configured Interrupt Status defines
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**********************************************************************/
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/** Receive Overrun */
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#define SSP_INTSTAT_ROR SSP_MIS_ROR
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/** Receive TimeOut */
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#define SSP_INTSTAT_RT SSP_MIS_RT
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/** Rx FIFO is at least half full */
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#define SSP_INTSTAT_RX SSP_MIS_RX
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/** Tx FIFO is at least half empty */
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#define SSP_INTSTAT_TX SSP_MIS_TX
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/*********************************************************************//**
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* SSP Raw Interrupt Status defines
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**********************************************************************/
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/** Receive Overrun */
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#define SSP_INTSTAT_RAW_ROR SSP_RIS_ROR
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/** Receive TimeOut */
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#define SSP_INTSTAT_RAW_RT SSP_RIS_RT
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/** Rx FIFO is at least half full */
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#define SSP_INTSTAT_RAW_RX SSP_RIS_RX
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/** Tx FIFO is at least half empty */
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#define SSP_INTSTAT_RAW_TX SSP_RIS_TX
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/*********************************************************************//**
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* SSP Interrupt Clear defines
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**********************************************************************/
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/** Writing a 1 to this bit clears the "frame was received when
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* RxFIFO was full" interrupt */
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#define SSP_INTCLR_ROR SSP_ICR_ROR
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/** Writing a 1 to this bit clears the "Rx FIFO was not empty and
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* has not been read for a timeout period" interrupt */
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#define SSP_INTCLR_RT SSP_ICR_RT
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/*********************************************************************//**
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* SSP DMA defines
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**********************************************************************/
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/** SSP bit for enabling RX DMA */
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#define SSP_DMA_TX SSP_DMA_RXDMA_EN
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/** SSP bit for enabling TX DMA */
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#define SSP_DMA_RX SSP_DMA_TXDMA_EN
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/* SSP Status Implementation definitions */
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#define SSP_STAT_DONE (1UL<<8) /**< Done */
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#define SSP_STAT_ERROR (1UL<<9) /**< Error */
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/* --------------------- BIT DEFINITIONS -------------------------------------- */
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/*********************************************************************//**
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* Macro defines for CR0 register
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**********************************************************************/
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/** SSP data size select, must be 4 bits to 16 bits */
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#define SSP_CR0_DSS(n) ((uint32_t)((n-1)&0xF))
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/** SSP control 0 Motorola SPI mode */
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#define SSP_CR0_FRF_SPI ((uint32_t)(0<<4))
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/** SSP control 0 TI synchronous serial mode */
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#define SSP_CR0_FRF_TI ((uint32_t)(1<<4))
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/** SSP control 0 National Micro-wire mode */
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#define SSP_CR0_FRF_MICROWIRE ((uint32_t)(2<<4))
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/** SPI clock polarity bit (used in SPI mode only), (1) = maintains the
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bus clock high between frames, (0) = low */
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#define SSP_CR0_CPOL_HI ((uint32_t)(1<<6))
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/** SPI clock out phase bit (used in SPI mode only), (1) = captures data
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on the second clock transition of the frame, (0) = first */
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#define SSP_CR0_CPHA_SECOND ((uint32_t)(1<<7))
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/** SSP serial clock rate value load macro, divider rate is
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PERIPH_CLK / (cpsr * (SCR + 1)) */
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#define SSP_CR0_SCR(n) ((uint32_t)((n&0xFF)<<8))
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/** SSP CR0 bit mask */
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#define SSP_CR0_BITMASK ((uint32_t)(0xFFFF))
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/*********************************************************************//**
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* Macro defines for CR1 register
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**********************************************************************/
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/** SSP control 1 loopback mode enable bit */
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#define SSP_CR1_LBM_EN ((uint32_t)(1<<0))
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/** SSP control 1 enable bit */
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#define SSP_CR1_SSP_EN ((uint32_t)(1<<1))
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/** SSP control 1 slave enable */
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#define SSP_CR1_SLAVE_EN ((uint32_t)(1<<2))
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/** SSP control 1 slave out disable bit, disables transmit line in slave
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mode */
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#define SSP_CR1_SO_DISABLE ((uint32_t)(1<<3))
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/** SSP CR1 bit mask */
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#define SSP_CR1_BITMASK ((uint32_t)(0x0F))
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/*********************************************************************//**
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* Macro defines for DR register
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**********************************************************************/
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/** SSP data bit mask */
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#define SSP_DR_BITMASK(n) ((n)&0xFFFF)
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/*********************************************************************//**
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* Macro defines for SR register
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**********************************************************************/
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/** SSP status TX FIFO Empty bit */
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#define SSP_SR_TFE ((uint32_t)(1<<0))
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/** SSP status TX FIFO not full bit */
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#define SSP_SR_TNF ((uint32_t)(1<<1))
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/** SSP status RX FIFO not empty bit */
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#define SSP_SR_RNE ((uint32_t)(1<<2))
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/** SSP status RX FIFO full bit */
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#define SSP_SR_RFF ((uint32_t)(1<<3))
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/** SSP status SSP Busy bit */
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#define SSP_SR_BSY ((uint32_t)(1<<4))
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/** SSP SR bit mask */
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#define SSP_SR_BITMASK ((uint32_t)(0x1F))
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/*********************************************************************//**
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* Macro defines for CPSR register
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**********************************************************************/
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/** SSP clock prescaler */
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#define SSP_CPSR_CPDVSR(n) ((uint32_t)(n&0xFF))
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/** SSP CPSR bit mask */
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#define SSP_CPSR_BITMASK ((uint32_t)(0xFF))
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/*********************************************************************//**
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* Macro define for (IMSC) Interrupt Mask Set/Clear registers
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**********************************************************************/
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/** Receive Overrun */
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#define SSP_IMSC_ROR ((uint32_t)(1<<0))
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/** Receive TimeOut */
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#define SSP_IMSC_RT ((uint32_t)(1<<1))
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/** Rx FIFO is at least half full */
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#define SSP_IMSC_RX ((uint32_t)(1<<2))
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/** Tx FIFO is at least half empty */
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#define SSP_IMSC_TX ((uint32_t)(1<<3))
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/** IMSC bit mask */
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#define SSP_IMSC_BITMASK ((uint32_t)(0x0F))
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/*********************************************************************//**
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* Macro define for (RIS) Raw Interrupt Status registers
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**********************************************************************/
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/** Receive Overrun */
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#define SSP_RIS_ROR ((uint32_t)(1<<0))
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/** Receive TimeOut */
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#define SSP_RIS_RT ((uint32_t)(1<<1))
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/** Rx FIFO is at least half full */
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#define SSP_RIS_RX ((uint32_t)(1<<2))
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/** Tx FIFO is at least half empty */
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#define SSP_RIS_TX ((uint32_t)(1<<3))
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/** RIS bit mask */
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#define SSP_RIS_BITMASK ((uint32_t)(0x0F))
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/*********************************************************************//**
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* Macro define for (MIS) Masked Interrupt Status registers
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**********************************************************************/
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/** Receive Overrun */
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#define SSP_MIS_ROR ((uint32_t)(1<<0))
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/** Receive TimeOut */
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#define SSP_MIS_RT ((uint32_t)(1<<1))
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/** Rx FIFO is at least half full */
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#define SSP_MIS_RX ((uint32_t)(1<<2))
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/** Tx FIFO is at least half empty */
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#define SSP_MIS_TX ((uint32_t)(1<<3))
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/** MIS bit mask */
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#define SSP_MIS_BITMASK ((uint32_t)(0x0F))
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/*********************************************************************//**
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* Macro define for (ICR) Interrupt Clear registers
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**********************************************************************/
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/** Writing a 1 to this bit clears the "frame was received when
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* RxFIFO was full" interrupt */
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#define SSP_ICR_ROR ((uint32_t)(1<<0))
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/** Writing a 1 to this bit clears the "Rx FIFO was not empty and
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* has not been read for a timeout period" interrupt */
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#define SSP_ICR_RT ((uint32_t)(1<<1))
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/** ICR bit mask */
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#define SSP_ICR_BITMASK ((uint32_t)(0x03))
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/*********************************************************************//**
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* Macro defines for DMACR register
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**********************************************************************/
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/** SSP bit for enabling RX DMA */
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#define SSP_DMA_RXDMA_EN ((uint32_t)(1<<0))
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/** SSP bit for enabling TX DMA */
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#define SSP_DMA_TXDMA_EN ((uint32_t)(1<<1))
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/** DMACR bit mask */
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#define SSP_DMA_BITMASK ((uint32_t)(0x03))
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/* ---------------- CHECK PARAMETER DEFINITIONS ---------------------------- */
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/** Macro to determine if it is valid SSP port number */
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#define PARAM_SSPx(n) ((((uint32_t *)n)==((uint32_t *)LPC_SSP0)) \
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|| (((uint32_t *)n)==((uint32_t *)LPC_SSP1)))
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/** Macro check clock phase control mode */
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#define PARAM_SSP_CPHA(n) ((n==SSP_CPHA_FIRST) || (n==SSP_CPHA_SECOND))
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/** Macro check clock polarity mode */
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#define PARAM_SSP_CPOL(n) ((n==SSP_CPOL_HI) || (n==SSP_CPOL_LO))
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/* Macro check master/slave mode */
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#define PARAM_SSP_MODE(n) ((n==SSP_SLAVE_MODE) || (n==SSP_MASTER_MODE))
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/* Macro check databit value */
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#define PARAM_SSP_DATABIT(n) ((n==SSP_DATABIT_4) || (n==SSP_DATABIT_5) \
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|| (n==SSP_DATABIT_6) || (n==SSP_DATABIT_16) \
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|| (n==SSP_DATABIT_7) || (n==SSP_DATABIT_8) \
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|| (n==SSP_DATABIT_9) || (n==SSP_DATABIT_10) \
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|| (n==SSP_DATABIT_11) || (n==SSP_DATABIT_12) \
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|| (n==SSP_DATABIT_13) || (n==SSP_DATABIT_14) \
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|| (n==SSP_DATABIT_15))
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/* Macro check frame type */
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#define PARAM_SSP_FRAME(n) ((n==SSP_FRAME_SPI) || (n==SSP_FRAME_TI)\
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|| (n==SSP_FRAME_MICROWIRE))
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/* Macro check SSP status */
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#define PARAM_SSP_STAT(n) ((n==SSP_STAT_TXFIFO_EMPTY) || (n==SSP_STAT_TXFIFO_NOTFULL) \
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|| (n==SSP_STAT_RXFIFO_NOTEMPTY) || (n==SSP_STAT_RXFIFO_FULL) \
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|| (n==SSP_STAT_BUSY))
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/* Macro check interrupt configuration */
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#define PARAM_SSP_INTCFG(n) ((n==SSP_INTCFG_ROR) || (n==SSP_INTCFG_RT) \
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|| (n==SSP_INTCFG_RX) || (n==SSP_INTCFG_TX))
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/* Macro check interrupt status value */
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#define PARAM_SSP_INTSTAT(n) ((n==SSP_INTSTAT_ROR) || (n==SSP_INTSTAT_RT) \
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|| (n==SSP_INTSTAT_RX) || (n==SSP_INTSTAT_TX))
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/* Macro check interrupt status raw value */
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#define PARAM_SSP_INTSTAT_RAW(n) ((n==SSP_INTSTAT_RAW_ROR) || (n==SSP_INTSTAT_RAW_RT) \
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|| (n==SSP_INTSTAT_RAW_RX) || (n==SSP_INTSTAT_RAW_TX))
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/* Macro check interrupt clear mode */
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#define PARAM_SSP_INTCLR(n) ((n==SSP_INTCLR_ROR) || (n==SSP_INTCLR_RT))
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/* Macro check DMA mode */
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#define PARAM_SSP_DMA(n) ((n==SSP_DMA_TX) || (n==SSP_DMA_RX))
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/**
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* @}
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*/
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/* Public Types --------------------------------------------------------------- */
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/** @defgroup SSP_Public_Types SSP Public Types
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* @{
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*/
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/** @brief SSP configuration structure */
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typedef struct {
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uint32_t Databit; /** Databit number, should be SSP_DATABIT_x,
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where x is in range from 4 - 16 */
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uint32_t CPHA; /** Clock phase, should be:
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- SSP_CPHA_FIRST: first clock edge
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- SSP_CPHA_SECOND: second clock edge */
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uint32_t CPOL; /** Clock polarity, should be:
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- SSP_CPOL_HI: high level
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- SSP_CPOL_LO: low level */
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uint32_t Mode; /** SSP mode, should be:
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- SSP_MASTER_MODE: Master mode
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- SSP_SLAVE_MODE: Slave mode */
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uint32_t FrameFormat; /** Frame Format:
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- SSP_FRAME_SPI: Motorola SPI frame format
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- SSP_FRAME_TI: TI frame format
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- SSP_FRAME_MICROWIRE: National Microwire frame format */
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uint32_t ClockRate; /** Clock rate,in Hz */
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} SSP_CFG_Type;
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/**
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* @brief SSP Transfer Type definitions
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*/
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typedef enum {
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SSP_TRANSFER_POLLING = 0, /**< Polling transfer */
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SSP_TRANSFER_INTERRUPT /**< Interrupt transfer */
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} SSP_TRANSFER_Type;
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/**
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* @brief SPI Data configuration structure definitions
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*/
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typedef struct {
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void *tx_data; /**< Pointer to transmit data */
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uint32_t tx_cnt; /**< Transmit counter */
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void *rx_data; /**< Pointer to transmit data */
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uint32_t rx_cnt; /**< Receive counter */
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uint32_t length; /**< Length of transfer data */
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uint32_t status; /**< Current status of SSP activity */
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} SSP_DATA_SETUP_Type;
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/**
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* @}
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*/
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/* Public Functions ----------------------------------------------------------- */
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/** @defgroup SSP_Public_Functions SSP Public Functions
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* @{
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*/
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void SSP_Init(LPC_SSPn_Type *SSPx, SSP_CFG_Type *SSP_ConfigStruct);
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void SSP_DeInit(LPC_SSPn_Type* SSPx);
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void SSP_ConfigStructInit(SSP_CFG_Type *SSP_InitStruct);
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void SSP_Cmd(LPC_SSPn_Type* SSPx, FunctionalState NewState);
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void SSP_LoopBackCmd(LPC_SSPn_Type* SSPx, FunctionalState NewState);
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void SSP_SlaveOutputCmd(LPC_SSPn_Type* SSPx, FunctionalState NewState);
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void SSP_SendData(LPC_SSPn_Type* SSPx, uint16_t Data);
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uint16_t SSP_ReceiveData(LPC_SSPn_Type* SSPx);
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int32_t SSP_ReadWrite (LPC_SSPn_Type *SSPx, SSP_DATA_SETUP_Type *dataCfg, \
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SSP_TRANSFER_Type xfType);
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FlagStatus SSP_GetStatus(LPC_SSPn_Type* SSPx, uint32_t FlagType);
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uint8_t SSP_GetDataSize(LPC_SSPn_Type* SSPx);
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void SSP_IntConfig(LPC_SSPn_Type *SSPx, uint32_t IntType, FunctionalState NewState);
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IntStatus SSP_GetRawIntStatus(LPC_SSPn_Type *SSPx, uint32_t RawIntType);
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IntStatus SSP_GetIntStatus (LPC_SSPn_Type *SSPx, uint32_t IntType);
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void SSP_ClearIntPending(LPC_SSPn_Type *SSPx, uint32_t IntType);
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void SSP_DMACmd(LPC_SSPn_Type *SSPx, uint32_t DMAMode, FunctionalState NewState);
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||
|
||
/**
|
||
* @}
|
||
*/
|
||
|
||
#ifdef __cplusplus
|
||
}
|
||
#endif
|
||
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#endif /* lpc43xx_SSP_H_ */
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||
|
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/**
|
||
* @}
|
||
*/
|
||
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