567 lines
20 KiB
C
567 lines
20 KiB
C
/*
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* @brief LPC11U6X System Control registers and control functions
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*
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* @note
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* Copyright(C) NXP Semiconductors, 2013
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* All rights reserved.
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*
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* @par
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* Software that is described herein is for illustrative purposes only
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* which provides customers with programming information regarding the
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* LPC products. This software is supplied "AS IS" without any warranties of
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* any kind, and NXP Semiconductors and its licensor disclaim any and
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* all warranties, express or implied, including all implied warranties of
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* merchantability, fitness for a particular purpose and non-infringement of
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* intellectual property rights. NXP Semiconductors assumes no responsibility
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* or liability for the use of the software, conveys no license or rights under any
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* patent, copyright, mask work right, or any other intellectual property rights in
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* or to any products. NXP Semiconductors reserves the right to make changes
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* in the software without notification. NXP Semiconductors also makes no
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* representation or warranty that such application will be suitable for the
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* specified use without further testing or modification.
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*
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* @par
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* Permission to use, copy, modify, and distribute this software and its
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* documentation is hereby granted, under NXP Semiconductors' and its
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* licensor's relevant copyrights in the software, without fee, provided that it
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* is used in conjunction with NXP Semiconductors microcontrollers. This
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* copyright, permission, and disclaimer notice must appear in all copies of
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* this code.
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*/
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#ifndef __SYSCTL_11U6X_H_
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#define __SYSCTL_11U6X_H_
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#ifdef __cplusplus
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extern "C" {
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#endif
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/** @defgroup SYSCTL_11U6X CHIP: LPC11u6x System Control block driver
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* @ingroup CHIP_11U6X_Drivers
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* @{
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*/
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/**
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* @brief LPC11U6X System Control block structure
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*/
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typedef struct { /*!< SYSCTL Structure */
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__IO uint32_t SYSMEMREMAP; /*!< System Memory remap register */
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__IO uint32_t PRESETCTRL; /*!< Peripheral reset Control register */
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__IO uint32_t SYSPLLCTRL; /*!< System PLL control register */
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__I uint32_t SYSPLLSTAT; /*!< System PLL status register */
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__IO uint32_t USBPLLCTRL; /*!< USB PLL control register */
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__I uint32_t USBPLLSTAT; /*!< USB PLL status register */
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__I uint32_t RESERVED1[1];
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__IO uint32_t RTCOSCCTRL; /*!< RTC Oscillator control register */
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__IO uint32_t SYSOSCCTRL; /*!< System Oscillator control register */
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__IO uint32_t WDTOSCCTRL; /*!< Watchdog Oscillator control register */
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__I uint32_t RESERVED2[2];
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__IO uint32_t SYSRSTSTAT; /*!< System Reset Status register */
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__I uint32_t RESERVED3[3];
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__IO uint32_t SYSPLLCLKSEL; /*!< System PLL clock source select register */
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__IO uint32_t SYSPLLCLKUEN; /*!< System PLL clock source update enable register*/
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__IO uint32_t USBPLLCLKSEL; /*!< USB PLL clock source select register */
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__IO uint32_t USBPLLCLKUEN; /*!< USB PLL clock source update enable register */
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__I uint32_t RESERVED4[8];
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__IO uint32_t MAINCLKSEL; /*!< Main clock source select register */
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__IO uint32_t MAINCLKUEN; /*!< Main clock source update enable register */
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__IO uint32_t SYSAHBCLKDIV; /*!< System Clock divider register */
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__I uint32_t RESERVED5;
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__IO uint32_t SYSAHBCLKCTRL; /*!< System clock control register */
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__I uint32_t RESERVED6[4];
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__IO uint32_t SSP0CLKDIV; /*!< SSP0 clock divider register */
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__IO uint32_t USART0CLKDIV; /*!< UART clock divider register */
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__IO uint32_t SSP1CLKDIV; /*!< SSP1 clock divider register */
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__IO uint32_t FRGCLKDIV; /*!< FRG clock divider (USARTS 1 - 4) register */
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__I uint32_t RESERVED7[7];
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__IO uint32_t USBCLKSEL; /*!< USB clock source select register */
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__IO uint32_t USBCLKUEN; /*!< USB clock source update enable register */
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__IO uint32_t USBCLKDIV; /*!< USB clock source divider register */
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__I uint32_t RESERVED8[5];
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__IO uint32_t CLKOUTSEL; /*!< Clock out source select register */
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__IO uint32_t CLKOUTUEN; /*!< Clock out source update enable register */
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__IO uint32_t CLKOUTDIV; /*!< Clock out divider register */
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__I uint32_t RESERVED9;
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__IO uint32_t UARTFRGDIV; /*!< USART fractional generator divider (USARTS 1 - 4) register */
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__IO uint32_t UARTFRGMULT; /*!< USART fractional generator multiplier (USARTS 1 - 4) register */
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__I uint32_t RESERVED10;
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__IO uint32_t EXTTRACECMD; /*!< External trace buffer command register */
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__I uint32_t PIOPORCAP[3]; /*!< POR captured PIO status registers */
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__I uint32_t RESERVED11[10];
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__IO uint32_t IOCONCLKDIV[7]; /*!< IOCON block for programmable glitch filter divider registers */
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__IO uint32_t BODCTRL; /*!< Brown Out Detect register */
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__IO uint32_t SYSTCKCAL; /*!< System tick counter calibration register */
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__I uint32_t RESERVED12[6];
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__IO uint32_t IRQLATENCY; /*!< IRQ delay register */
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__IO uint32_t NMISRC; /*!< NMI source control register */
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__IO uint32_t PINTSEL[8]; /*!< GPIO pin interrupt select register 0-7 */
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__IO uint32_t USBCLKCTRL; /*!< USB clock control register */
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__I uint32_t USBCLKST; /*!< USB clock status register */
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__I uint32_t RESERVED13[25];
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__IO uint32_t STARTERP0; /*!< Start logic 0 interrupt wake-up enable register */
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__I uint32_t RESERVED14[3];
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__IO uint32_t STARTERP1; /*!< Start logic 1 interrupt wake-up enable register */
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__I uint32_t RESERVED15[6];
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__IO uint32_t PDSLEEPCFG; /*!< Power down states in deep sleep mode register */
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__IO uint32_t PDWAKECFG; /*!< Power down states in wake up from deep sleep register */
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__IO uint32_t PDRUNCFG; /*!< Power configuration register*/
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__I uint32_t RESERVED16[110];
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__I uint32_t DEVICEID; /*!< Device ID register */
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} LPC_SYSCTL_T;
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/**
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* System memory remap modes used to remap interrupt vectors
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*/
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typedef enum CHIP_SYSCTL_BOOT_MODE_REMAP {
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REMAP_BOOT_LOADER_MODE, /*!< Interrupt vectors are re-mapped to Boot ROM */
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REMAP_USER_RAM_MODE, /*!< Interrupt vectors are re-mapped to Static RAM */
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REMAP_USER_FLASH_MODE /*!< Interrupt vectors are not re-mapped and reside in Flash */
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} CHIP_SYSCTL_BOOT_MODE_REMAP_T;
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/**
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* @brief Re-map interrupt vectors
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* @param remap : system memory map value
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* @return Nothing
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*/
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STATIC INLINE void Chip_SYSCTL_Map(CHIP_SYSCTL_BOOT_MODE_REMAP_T remap)
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{
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LPC_SYSCTL->SYSMEMREMAP = (uint32_t) remap;
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}
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/**
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* Peripheral reset identifiers, not available on all devices
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*/
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typedef enum {
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RESET_SSP0, /*!< SSP0 reset control */
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RESET_I2C0, /*!< I2C0 reset control */
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RESET_SSP1, /*!< SSP1 reset control */
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RESET_I2C1, /*!< I2C1 reset control */
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RESET_FRG, /*!< FRG reset control */
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RESET_USART1, /*!< USART1 reset control */
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RESET_USART2, /*!< USART1 reset control */
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RESET_USART3, /*!< USART1 reset control */
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RESET_USART4, /*!< USART1 reset control */
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RESET_SCT0, /*!< SCT0 reset control */
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RESET_SCT1 /*!< SCT1 reset control */
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} CHIP_SYSCTL_PERIPH_RESET_T;
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/**
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* @brief Assert reset for a peripheral
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* @param periph : Peripheral to assert reset for
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* @return Nothing
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* @note The peripheral will stay in reset until reset is de-asserted. Call
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* Chip_SYSCTL_DeassertPeriphReset() to de-assert the reset.
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*/
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STATIC INLINE void Chip_SYSCTL_AssertPeriphReset(CHIP_SYSCTL_PERIPH_RESET_T periph)
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{
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LPC_SYSCTL->PRESETCTRL &= ~(1 << (uint32_t) periph);
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}
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/**
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* @brief De-assert reset for a peripheral
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* @param periph : Peripheral to de-assert reset for
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* @return Nothing
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*/
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STATIC INLINE void Chip_SYSCTL_DeassertPeriphReset(CHIP_SYSCTL_PERIPH_RESET_T periph)
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{
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LPC_SYSCTL->PRESETCTRL |= (1 << (uint32_t) periph);
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}
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/**
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* @brief Resets a peripheral
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* @param periph : Peripheral to reset
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* @return Nothing
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*/
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STATIC INLINE void Chip_SYSCTL_PeriphReset(CHIP_SYSCTL_PERIPH_RESET_T periph)
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{
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Chip_SYSCTL_AssertPeriphReset(periph);
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Chip_SYSCTL_DeassertPeriphReset(periph);
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}
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/**
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* System reset status
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*/
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#define SYSCTL_RST_POR (1 << 0) /*!< POR reset status */
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#define SYSCTL_RST_EXTRST (1 << 1) /*!< External reset status */
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#define SYSCTL_RST_WDT (1 << 2) /*!< Watchdog reset status */
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#define SYSCTL_RST_BOD (1 << 3) /*!< Brown-out detect reset status */
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#define SYSCTL_RST_SYSRST (1 << 4) /*!< software system reset status */
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/**
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* @brief Get system reset status
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* @return An Or'ed value of SYSCTL_RST_*
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* @note This function returns the detected reset source(s).
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*/
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STATIC INLINE uint32_t Chip_SYSCTL_GetSystemRSTStatus(void)
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{
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return LPC_SYSCTL->SYSRSTSTAT;
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}
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/**
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* @brief Clear system reset status
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* @param reset : An Or'ed value of SYSCTL_RST_* status to clear
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* @return Nothing
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* @note This function returns the detected reset source(s).
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*/
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STATIC INLINE void Chip_SYSCTL_ClearSystemRSTStatus(uint32_t reset)
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{
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LPC_SYSCTL->SYSRSTSTAT = reset;
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}
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/**
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* @brief Read POR captured PIO status
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* @param index : POR register index, 0 or 1
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* @return captured POR PIO status
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*/
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STATIC INLINE uint32_t Chip_SYSCTL_GetPORPIOStatus(int index)
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{
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return LPC_SYSCTL->PIOPORCAP[index];
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}
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/**
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* Brown-out detector reset level
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*/
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typedef enum CHIP_SYSCTL_BODRSTLVL {
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// FIXME - will update with correct voltages
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SYSCTL_BODRSTLVL_LEVEL0, /*!< Brown-out reset at TBD volts */
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SYSCTL_BODRSTLVL_LEVEL1, /*!< Brown-out reset at TBD volts */
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SYSCTL_BODRSTLVL_LEVEL2, /*!< Brown-out reset at TBD volts */
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SYSCTL_BODRSTLVL_LEVEL3, /*!< Brown-out reset at TBD volts */
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} CHIP_SYSCTL_BODRSTLVL_T;
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/**
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* Brown-out detector interrupt level
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*/
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typedef enum CHIP_SYSCTL_BODRINTVAL {
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// FIXME - will update with correct voltages
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SYSCTL_BODINTVAL_RESERVED1,
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SYSCTL_BODINTVAL_RESERVED2,
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SYSCTL_BODINTVAL_2_LEVEL2, /*!< Brown-out interrupt at TBD volts */
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SYSCTL_BODINTVAL_2_LEVEL3, /*!< Brown-out interrupt at TBD volts */
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} CHIP_SYSCTL_BODRINTVAL_T;
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/**
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* @brief Set brown-out detection interrupt and reset levels
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* @param rstlvl : Brown-out detector reset level
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* @param intlvl : Brown-out interrupt level
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* @return Nothing
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* @note Brown-out detection reset will be disabled upon exiting this function.
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* Use Chip_SYSCTL_EnableBODReset() to re-enable.
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*/
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STATIC INLINE void Chip_SYSCTL_SetBODLevels(CHIP_SYSCTL_BODRSTLVL_T rstlvl,
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CHIP_SYSCTL_BODRINTVAL_T intlvl)
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{
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LPC_SYSCTL->BODCTRL = ((uint32_t) rstlvl) | (((uint32_t) intlvl) << 2);
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}
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/**
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* @brief Enable brown-out detection reset
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* @return Nothing
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*/
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STATIC INLINE void Chip_SYSCTL_EnableBODReset(void)
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{
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LPC_SYSCTL->BODCTRL |= (1 << 4);
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}
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/**
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* @brief Disable brown-out detection reset
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* @return Nothing
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*/
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STATIC INLINE void Chip_SYSCTL_DisableBODReset(void)
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{
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LPC_SYSCTL->BODCTRL &= ~(1 << 4);
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}
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/**
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* @brief Set System tick timer calibration value
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* @param sysCalVal : System tick timer calibration value
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* @return Nothing
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*/
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STATIC INLINE void Chip_SYSCTL_SetSYSTCKCAL(uint32_t sysCalVal)
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{
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LPC_SYSCTL->SYSTCKCAL = sysCalVal;
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}
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/**
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* @brief Set System IRQ latency
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* @param latency : Latency in clock ticks
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* @return Nothing
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* @note Sets the IRQ latency, a value between 0 and 255 clocks. Lower
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* values allow better latency.
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*/
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STATIC INLINE void Chip_SYSCTL_SetIRQLatency(uint32_t latency)
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{
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LPC_SYSCTL->IRQLATENCY = latency;
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}
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/**
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* @brief Get System IRQ latency
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* @return Latency in clock ticks
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*/
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STATIC INLINE uint32_t Chip_SYSCTL_GetIRQLatency(void)
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{
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return LPC_SYSCTL->IRQLATENCY;
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}
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/**
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* Non-Maskable Interrupt Enable/Disable value
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*/
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#define SYSCTL_NMISRC_ENABLE ((uint32_t) 1 << 31) /*!< Enable the Non-Maskable Interrupt (NMI) source */
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/**
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* @brief Set source for non-maskable interrupt (NMI)
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* @param intsrc : IRQ number to assign to the NMI
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* @return Nothing
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* @note The NMI source will be disabled upon exiting this function. use the
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* Chip_SYSCTL_EnableNMISource() function to enable the NMI source.
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*/
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STATIC INLINE void Chip_SYSCTL_SetNMISource(uint32_t intsrc)
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{
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LPC_SYSCTL->NMISRC = 0; /* Disable first */
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LPC_SYSCTL->NMISRC = intsrc;
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}
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/**
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* @brief Enable interrupt used for NMI source
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* @return Nothing
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*/
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STATIC INLINE void Chip_SYSCTL_EnableNMISource(void)
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{
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LPC_SYSCTL->NMISRC |= SYSCTL_NMISRC_ENABLE;
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}
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/**
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* @brief Disable interrupt used for NMI source
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* @return Nothing
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*/
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STATIC INLINE void Chip_SYSCTL_DisableNMISource(void)
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{
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LPC_SYSCTL->NMISRC &= ~(SYSCTL_NMISRC_ENABLE);
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}
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/**
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* @brief Setup a GPIO pin source for a pin interrupt (0-7)
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* @param intno : IRQ number
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* @param port : port number 0, 1, or 2)
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* @param pin : pin number (0-23 for Port 0, 0-31 for Port 1, 0-7 for port 2)
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* @return Nothing
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*/
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void Chip_SYSCTL_SetPinInterrupt(uint32_t intno, uint8_t port, uint8_t pin);
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/**
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* @brief Setup USB clock control
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* @param ap_clk : USB need_clock signal control (0 or 1)
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* @param pol_clk : USB need_clock polarity for triggering the USB wake-up interrupt (0 or 1)
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* @return Nothing
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* @note See the USBCLKCTRL register in the user manual for these settings.
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*/
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STATIC INLINE void Chip_SYSCTL_SetUSBCLKCTRL(uint32_t ap_clk, uint32_t pol_clk)
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{
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LPC_SYSCTL->USBCLKCTRL = ap_clk | (pol_clk << 1);
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}
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/**
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* @brief Use the internal pull-up resistor for the the USB_DP/DM pull-up/pull-down resistors
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* @return Nothing
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* @note See the USBCLKCTRL register in the user manual for more information.
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*/
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STATIC INLINE void Chip_SYSCTL_UseIntPullup(void)
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{
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LPC_SYSCTL->USBCLKCTRL |= (1 << 2);
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}
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/**
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* @brief Use the external pull-up resistor for the the USB_DP/DM pull-up/pull-down resistors
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* @return Nothing
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* @note See the USBCLKCTRL register in the user manual for more information.
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*/
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STATIC INLINE void Chip_SYSCTL_UseExtPullup(void)
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{
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LPC_SYSCTL->USBCLKCTRL &= ~(1 << 2);
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}
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/**
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* @brief Returns the status of the USB need_clock signal
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* @return true if USB need_clock status is high, otherwise false
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*/
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STATIC INLINE bool Chip_SYSCTL_GetUSBCLKStatus(void)
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{
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return (bool) ((LPC_SYSCTL->USBCLKST & 0x1) != 0);
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}
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/**
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* @brief Enable PIO start logic for a PININT pin
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* @param pin : PIO pin number
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* @return Nothing
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* @note Different devices support different pins, see the user manual for supported pins.
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*/
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STATIC INLINE void Chip_SYSCTL_EnableStartPin(uint32_t pin)
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{
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LPC_SYSCTL->STARTERP0 |= (1 << pin);
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}
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/**
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* @brief Disable PIO start logic for a PININT pin
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* @param pin : PIO pin number
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* @return Nothing
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* @note Different devices support different pins, see the user manual for supported pins.
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*/
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STATIC INLINE void Chip_SYSCTL_DisableStartPin(uint32_t pin)
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{
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LPC_SYSCTL->STARTERP0 &= ~(1 << pin);
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}
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/**
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* Peripheral interrupt wakeup events
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*/
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#define SYSCTL_WAKEUP_BOD_WDT_INT (1 << 13) /*!< Shared Brown Out Detect (BOD) and WDT interrupt wake-up */
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#define SYSCTL_WAKEUP_RTCINT (1 << 12) /*!< RTC interrupt wake-up */
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#define SYSCTL_WAKEUP_USB_WAKEUP (1 << 19) /*!< USB need_clock signal wake-up */
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#define SYSCTL_WAKEUP_GPIOINT0 (1 << 20) /*!< GPIO GROUP0 interrupt wake-up */
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#define SYSCTL_WAKEUP_GPIOINT1 (1 << 21) /*!< GPIO GROUP1 interrupt wake-up */
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#define SYSCTL_WAKEUP_USART1_4 (1 << 23) /*!< Combined USART1 and USART4 wake-up */
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#define SYSCTL_WAKEUP_USART2_3 (1 << 24) /*!< Combined USART2 and USART3 interrupt wake-up */
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/**
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* @brief Enables a peripheral's wakeup logic
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* @param periphmask : OR'ed values of SYSCTL_WAKEUP_* for wakeup
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* @return Nothing
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*/
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STATIC INLINE void Chip_SYSCTL_EnablePeriphWakeup(uint32_t periphmask)
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{
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LPC_SYSCTL->STARTERP1 |= periphmask;
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}
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/**
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* @brief Disables a peripheral's wakeup logic
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* @param periphmask : OR'ed values of SYSCTL_WAKEUP_* for wakeup
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* @return Nothing
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*/
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STATIC INLINE void Chip_SYSCTL_DisablePeriphWakeup(uint32_t periphmask)
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{
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LPC_SYSCTL->STARTERP1 &= ~periphmask;
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}
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/**
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* Deep sleep setup values
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*/
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#define SYSCTL_DEEPSLP_BOD_PD (1 << 3) /*!< BOD power-down control in Deep-sleep mode, powered down */
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#define SYSCTL_DEEPSLP_WDTOSC_PD (1 << 6) /*!< Watchdog oscillator power control in Deep-sleep, powered down */
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/**
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* @brief Setup deep sleep behaviour for power down
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* @param sleepmask : OR'ed values of SYSCTL_DEEPSLP_* values (high to powerdown on deepsleep)
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* @return Nothing
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* @note This must be setup prior to using deep sleep. See the user manual
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* (PDSLEEPCFG register) for more info on setting this up. This function selects
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* which peripherals are powered down on deep sleep.
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* This function should only be called once with all options for power-down
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* in that call.
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*/
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void Chip_SYSCTL_SetDeepSleepPD(uint32_t sleepmask);
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/**
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* @brief Returns current deep sleep mask
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* @return OR'ed values of SYSCTL_DEEPSLP_* values
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* @note A high bit indicates the peripheral will power down on deep sleep.
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*/
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STATIC INLINE uint32_t Chip_SYSCTL_GetDeepSleepPD(void)
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{
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return LPC_SYSCTL->PDSLEEPCFG;
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}
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/**
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* Deep sleep to wakeup setup values
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*/
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#define SYSCTL_SLPWAKE_IRCOUT_PD (1 << 0) /*!< IRC oscillator output wake-up configuration */
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#define SYSCTL_SLPWAKE_IRC_PD (1 << 1) /*!< IRC oscillator power-down wake-up configuration */
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#define SYSCTL_SLPWAKE_FLASH_PD (1 << 2) /*!< Flash wake-up configuration */
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#define SYSCTL_SLPWAKE_BOD_PD (1 << 3) /*!< BOD wake-up configuration */
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#define SYSCTL_SLPWAKE_ADC_PD (1 << 4) /*!< ADC wake-up configuration */
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#define SYSCTL_SLPWAKE_SYSOSC_PD (1 << 5) /*!< System oscillator wake-up configuration */
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#define SYSCTL_SLPWAKE_WDTOSC_PD (1 << 6) /*!< Watchdog oscillator wake-up configuration */
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#define SYSCTL_SLPWAKE_SYSPLL_PD (1 << 7) /*!< System PLL wake-up configuration */
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#define SYSCTL_SLPWAKE_USBPLL_PD (1 << 8) /*!< USB PLL wake-up configuration */
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#define SYSCTL_SLPWAKE_USBPAD_PD (1 << 10) /*!< USB transceiver wake-up configuration */
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#define SYSCTL_SLPWAKE_TS_PD (1 << 13) /*!< Temperature sensor wake-up configuration */
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/**
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* @brief Setup wakeup behaviour from deep sleep
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* @param wakeupmask : OR'ed values of SYSCTL_SLPWAKE_* values (high is powered down)
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* @return Nothing
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* @note This must be setup prior to using deep sleep. See the user manual
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* (PDWAKECFG register) for more info on setting this up. This function selects
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* which peripherals are powered up on exit from deep sleep.
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* This function should only be called once with all options for wakeup
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* in that call.
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*/
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void Chip_SYSCTL_SetWakeup(uint32_t wakeupmask);
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/**
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* @brief Return current wakeup mask
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* @return OR'ed values of SYSCTL_SLPWAKE_* values
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* @note A high state indicates the peripehral will powerup on wakeup.
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*/
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STATIC INLINE uint32_t Chip_SYSCTL_GetWakeup(void)
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{
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return LPC_SYSCTL->PDWAKECFG;
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}
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/**
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* Power down configuration values
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*/
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#define SYSCTL_POWERDOWN_IRCOUT_PD (1 << 0) /*!< IRC oscillator output power down */
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#define SYSCTL_POWERDOWN_IRC_PD (1 << 1) /*!< IRC oscillator power-down */
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#define SYSCTL_POWERDOWN_FLASH_PD (1 << 2) /*!< Flash power down */
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#define SYSCTL_POWERDOWN_BOD_PD (1 << 3) /*!< BOD power down */
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#define SYSCTL_POWERDOWN_ADC_PD (1 << 4) /*!< ADC power down */
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#define SYSCTL_POWERDOWN_SYSOSC_PD (1 << 5) /*!< System oscillator power down */
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#define SYSCTL_POWERDOWN_WDTOSC_PD (1 << 6) /*!< Watchdog oscillator power down */
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#define SYSCTL_POWERDOWN_SYSPLL_PD (1 << 7) /*!< System PLL power down */
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#define SYSCTL_POWERDOWN_USBPLL_PD (1 << 8) /*!< USB PLL power-down */
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#define SYSCTL_POWERDOWN_USBPAD_PD (1 << 10) /*!< USB transceiver power-down */
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#define SYSCTL_POWERDOWN_TS_PD (1 << 13) /*!< Temperature Sensor power-down */
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/**
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* @brief Power down one or more blocks or peripherals
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* @param powerdownmask : OR'ed values of SYSCTL_POWERDOWN_* values
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* @return Nothing
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*/
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void Chip_SYSCTL_PowerDown(uint32_t powerdownmask);
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/**
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* @brief Power up one or more blocks or peripherals
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* @param powerupmask : OR'ed values of SYSCTL_POWERDOWN_* values
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* @return Nothing
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*/
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void Chip_SYSCTL_PowerUp(uint32_t powerupmask);
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/**
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* @brief Get power status
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* @return OR'ed values of SYSCTL_POWERDOWN_* values
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* @note A high state indicates the peripheral is powered down.
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*/
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STATIC INLINE uint32_t Chip_SYSCTL_GetPowerStates(void)
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{
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return LPC_SYSCTL->PDRUNCFG;
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}
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/**
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* @brief Return the device ID
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* @return the device ID
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*/
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STATIC INLINE uint32_t Chip_SYSCTL_GetDeviceID(void)
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{
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return LPC_SYSCTL->DEVICEID;
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}
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/**
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* @}
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*/
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#ifdef __cplusplus
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}
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#endif
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#endif /*!< __SYSCTL_11U6X_H_ */
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