93 lines
3.1 KiB
C
93 lines
3.1 KiB
C
/**
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**************************************************************************
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* @file at32f415_clock.c
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* @brief system clock config program
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**************************************************************************
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* Copyright notice & Disclaimer
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*
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* The software Board Support Package (BSP) that is made available to
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* download from Artery official website is the copyrighted work of Artery.
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* Artery authorizes customers to use, copy, and distribute the BSP
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* software and its related documentation for the purpose of design and
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* development in conjunction with Artery microcontrollers. Use of the
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* software is governed by this copyright notice and the following disclaimer.
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*
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* THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
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* GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
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* TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
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* STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
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* INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
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*
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**************************************************************************
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*/
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/* includes ------------------------------------------------------------------*/
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#include "at32f415_clock.h"
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/**
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* @brief system clock config program
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* @note the system clock is configured as follow:
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* system clock (sclk) = hick8m / 2 * pll_mult
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* system clock source = pll (hick)
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* - hick = HICK_VALUE
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* - sclk = 144000000
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* - ahbdiv = 1
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* - ahbclk = 144000000
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* - apb2div = 2
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* - apb2clk = 72000000
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* - apb1div = 2
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* - apb1clk = 72000000
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* - pll_mult = 36
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* - flash_wtcyc = 4 cycle
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* @param none
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* @retval none
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*/
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void system_clock_config(void)
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{
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/* config flash psr register */
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flash_psr_set(FLASH_WAIT_CYCLE_4);
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/* reset crm */
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crm_reset();
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crm_clock_source_enable(CRM_CLOCK_SOURCE_HICK, TRUE);
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/* config pll clock resource */
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crm_pll_config(CRM_PLL_SOURCE_HICK, CRM_PLL_MULT_36);
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/* enable pll */
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crm_clock_source_enable(CRM_CLOCK_SOURCE_PLL, TRUE);
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/* wait till pll is ready */
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while(crm_flag_get(CRM_PLL_STABLE_FLAG) != SET)
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{
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}
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/* config ahbclk */
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crm_ahb_div_set(CRM_AHB_DIV_1);
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/* config apb2clk, the maximum frequency of APB1/APB2 clock is 75 MHz */
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crm_apb2_div_set(CRM_APB2_DIV_2);
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/* config apb1clk, the maximum frequency of APB1/APB2 clock is 75 MHz */
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crm_apb1_div_set(CRM_APB1_DIV_2);
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/* enable auto step mode */
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crm_auto_step_mode_enable(TRUE);
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/* select pll as system clock source */
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crm_sysclk_switch(CRM_SCLK_PLL);
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/* wait till pll is used as system clock source */
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while(crm_sysclk_switch_status_get() != CRM_SCLK_PLL)
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{
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}
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/* disable auto step mode */
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crm_auto_step_mode_enable(FALSE);
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/* update system_core_clock global variable */
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system_core_clock_update();
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}
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