478 lines
14 KiB
C
478 lines
14 KiB
C
/*
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* The MIT License (MIT)
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*
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* Copyright (c) 2020 SE TEAM
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*
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* This file is part of the TinyUSB stack.
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*/
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#include "tusb_option.h"
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#if TUSB_OPT_DEVICE_ENABLED && ( CFG_TUSB_MCU == OPT_MCU_MM32F327X )
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#include "reg_usb_otg_fs.h"
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#include "mm32_device.h"
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#include "hal_conf.h"
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#include "device/dcd.h"
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//--------------------------------------------------------------------+
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// MACRO TYPEDEF CONSTANT ENUM DECLARATION
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//--------------------------------------------------------------------+
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enum {
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TOK_PID_OUT = 0x1u,
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TOK_PID_IN = 0x9u,
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TOK_PID_SETUP = 0xDu,
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};
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typedef struct TU_ATTR_PACKED
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{
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union {
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uint32_t head;
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struct {
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union {
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struct {
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uint16_t : 2;
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uint16_t tok_pid : 4;
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uint16_t data : 1;
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uint16_t own : 1;
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uint16_t : 8;
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};
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struct {
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uint16_t : 2;
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uint16_t bdt_stall: 1;
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uint16_t dts : 1;
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uint16_t ninc : 1;
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uint16_t keep : 1;
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uint16_t : 10;
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};
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};
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uint16_t bc : 10;
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uint16_t : 6;
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};
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};
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uint8_t *addr;
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}buffer_descriptor_t;
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TU_VERIFY_STATIC( sizeof(buffer_descriptor_t) == 8, "size is not correct" );
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typedef struct TU_ATTR_PACKED
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{
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union {
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uint32_t state;
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struct {
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uint32_t max_packet_size :11;
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uint32_t : 5;
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uint32_t odd : 1;
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uint32_t :15;
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};
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};
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uint16_t length;
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uint16_t remaining;
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}endpoint_state_t;
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TU_VERIFY_STATIC( sizeof(endpoint_state_t) == 8, "size is not correct" );
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typedef struct
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{
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union {
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/* [#EP][OUT,IN][EVEN,ODD] */
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buffer_descriptor_t bdt[16][2][2];
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uint16_t bda[512];
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};
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TU_ATTR_ALIGNED(4) union {
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endpoint_state_t endpoint[16][2];
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endpoint_state_t endpoint_unified[16 * 2];
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};
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uint8_t setup_packet[8];
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uint8_t addr;
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}dcd_data_t;
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//--------------------------------------------------------------------+
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// INTERNAL OBJECT & FUNCTION DECLARATION
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//--------------------------------------------------------------------+
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// BDT(Buffer Descriptor Table) must be 256-byte aligned
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CFG_TUSB_MEM_SECTION TU_ATTR_ALIGNED(512) static dcd_data_t _dcd;
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TU_VERIFY_STATIC( sizeof(_dcd.bdt) == 512, "size is not correct" );
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static void prepare_next_setup_packet(uint8_t rhport)
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{
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const unsigned out_odd = _dcd.endpoint[0][0].odd;
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const unsigned in_odd = _dcd.endpoint[0][1].odd;
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if (_dcd.bdt[0][0][out_odd].own) {
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TU_LOG1("DCD fail to prepare the next SETUP %d %d\r\n", out_odd, in_odd);
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return;
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}
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_dcd.bdt[0][0][out_odd].data = 0;
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_dcd.bdt[0][0][out_odd ^ 1].data = 1;
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_dcd.bdt[0][1][in_odd].data = 1;
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_dcd.bdt[0][1][in_odd ^ 1].data = 0;
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dcd_edpt_xfer(rhport, tu_edpt_addr(0, TUSB_DIR_OUT),
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_dcd.setup_packet, sizeof(_dcd.setup_packet));
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}
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static void process_stall(uint8_t rhport)
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{
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if (USB_OTG_FS->EP_CTL[0] & USB_ENDPT_EPSTALL_MASK) {
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/* clear stall condition of the control pipe */
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prepare_next_setup_packet(rhport);
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USB_OTG_FS->EP_CTL[0] &= ~USB_ENDPT_EPSTALL_MASK;
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}
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}
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static void process_tokdne(uint8_t rhport)
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{
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const unsigned s = USB_OTG_FS->STAT;
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USB_OTG_FS->INT_STAT = USB_ISTAT_TOKDNE_MASK; /* fetch the next token if received */
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buffer_descriptor_t *bd = (buffer_descriptor_t *)&_dcd.bda[s];
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endpoint_state_t *ep = &_dcd.endpoint_unified[s >> 3];
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unsigned odd = (s & USB_STAT_ODD_MASK) ? 1 : 0;
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/* fetch pid before discarded by the next steps */
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const unsigned pid = bd->tok_pid;
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/* reset values for a next transfer */
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bd->bdt_stall = 0;
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bd->dts = 1;
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bd->ninc = 0;
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bd->keep = 0;
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/* update the odd variable to prepare for the next transfer */
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ep->odd = odd ^ 1;
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if (pid == TOK_PID_SETUP) {
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dcd_event_setup_received(rhport, bd->addr, true);
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USB_OTG_FS->CTL &= ~USB_CTL_TXSUSPENDTOKENBUSY_MASK;
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return;
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}
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if (s >> 4) {
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TU_LOG1("TKDNE %x\r\n", s);
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}
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const unsigned bc = bd->bc;
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const unsigned remaining = ep->remaining - bc;
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if (remaining && bc == ep->max_packet_size) {
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/* continue the transferring consecutive data */
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ep->remaining = remaining;
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const int next_remaining = remaining - ep->max_packet_size;
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if (next_remaining > 0) {
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/* prepare to the after next transfer */
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bd->addr += ep->max_packet_size * 2;
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bd->bc = next_remaining > ep->max_packet_size ? ep->max_packet_size: next_remaining;
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__DSB();
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bd->own = 1; /* the own bit must set after addr */
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}
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return;
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}
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const unsigned length = ep->length;
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dcd_event_xfer_complete(rhport,
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((s & USB_STAT_TX_MASK) << 4) | (s >> USB_STAT_ENDP_SHIFT),
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length - remaining, XFER_RESULT_SUCCESS, true);
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if (0 == (s & USB_STAT_ENDP_MASK) && 0 == length) {
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/* After completion a ZLP of control transfer,
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* it prepares for the next steup transfer. */
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if (_dcd.addr) {
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/* When the transfer was the SetAddress,
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* the device address should be updated here. */
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USB_OTG_FS->ADDR = _dcd.addr;
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_dcd.addr = 0;
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}
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prepare_next_setup_packet(rhport);
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}
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}
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static void process_bus_reset(uint8_t rhport)
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{
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USB_OTG_FS->CTL |= USB_CTL_ODDRST_MASK;
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USB_OTG_FS->ADDR = 0;
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USB_OTG_FS->INT_ENB = (USB_OTG_FS->INT_ENB & ~USB_INTEN_RESUMEEN_MASK) | USB_INTEN_SLEEPEN_MASK;
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USB_OTG_FS->EP_CTL[0] = USB_ENDPT_EPHSHK_MASK | USB_ENDPT_EPRXEN_MASK | USB_ENDPT_EPTXEN_MASK;
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for (unsigned i = 1; i < 16; ++i) {
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USB_OTG_FS->EP_CTL[i] = 0;
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}
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buffer_descriptor_t *bd = _dcd.bdt[0][0];
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for (unsigned i = 0; i < sizeof(_dcd.bdt)/sizeof(*bd); ++i, ++bd) {
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bd->head = 0;
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}
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const endpoint_state_t ep0 = {
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.max_packet_size = CFG_TUD_ENDPOINT0_SIZE,
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.odd = 0,
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.length = 0,
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.remaining = 0,
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};
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_dcd.endpoint[0][0] = ep0;
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_dcd.endpoint[0][1] = ep0;
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tu_memclr(_dcd.endpoint[1], sizeof(_dcd.endpoint) - sizeof(_dcd.endpoint[0]));
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_dcd.addr = 0;
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prepare_next_setup_packet(rhport);
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USB_OTG_FS->CTL &= ~USB_CTL_ODDRST_MASK;
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dcd_event_bus_reset(rhport, TUSB_SPEED_FULL, true);
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}
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static void process_bus_inactive(uint8_t rhport)
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{
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(void) rhport;
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const unsigned inten = USB_OTG_FS->INT_ENB;
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USB_OTG_FS->INT_ENB = (inten & ~USB_INTEN_SLEEPEN_MASK) | USB_INTEN_RESUMEEN_MASK;
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dcd_event_bus_signal(rhport, DCD_EVENT_SUSPEND, true);
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}
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static void process_bus_active(uint8_t rhport)
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{
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(void) rhport;
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const unsigned inten = USB_OTG_FS->INT_ENB;
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USB_OTG_FS->INT_ENB = (inten & ~USB_INTEN_RESUMEEN_MASK) | USB_INTEN_SLEEPEN_MASK;
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dcd_event_bus_signal(rhport, DCD_EVENT_RESUME, true);
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}
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/*------------------------------------------------------------------*/
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/* Device API
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*------------------------------------------------------------------*/
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void dcd_init(uint8_t rhport)
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{
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(void) rhport;
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tu_memclr(&_dcd, sizeof(_dcd));
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USB_OTG_FS->BDT_PAGE_01 = (uint8_t)((uintptr_t)_dcd.bdt >> 8);
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USB_OTG_FS->BDT_PAGE_02 = (uint8_t)((uintptr_t)_dcd.bdt >> 16);
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USB_OTG_FS->BDT_PAGE_03 = (uint8_t)((uintptr_t)_dcd.bdt >> 24);
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dcd_connect(rhport);
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NVIC_ClearPendingIRQ(USB_FS_IRQn);
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}
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#define USB_DEVICE_INTERRUPT_PRIORITY (3U)
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void dcd_int_enable(uint8_t rhport)
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{
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uint8_t irqNumber;
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irqNumber = USB_FS_IRQn;
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(void) rhport;
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USB_OTG_FS->INT_ENB = USB_INTEN_USBRSTEN_MASK | USB_INTEN_TOKDNEEN_MASK |
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USB_INTEN_SLEEPEN_MASK | USB_INTEN_ERROREN_MASK | USB_INTEN_STALLEN_MASK;
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NVIC_SetPriority((IRQn_Type)irqNumber, USB_DEVICE_INTERRUPT_PRIORITY);
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NVIC_EnableIRQ(USB_FS_IRQn);
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}
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void dcd_int_disable(uint8_t rhport)
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{
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(void) rhport;
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NVIC_DisableIRQ(USB_FS_IRQn);
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USB_OTG_FS->INT_ENB = 0;
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}
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void dcd_set_address(uint8_t rhport, uint8_t dev_addr)
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{
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(void) rhport;
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_dcd.addr = dev_addr & 0x7F;
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/* Response with status first before changing device address */
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dcd_edpt_xfer(rhport, tu_edpt_addr(0, TUSB_DIR_IN), NULL, 0);
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}
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extern u32 SystemCoreClock ;
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void dcd_remote_wakeup(uint8_t rhport)
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{
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(void) rhport;
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unsigned cnt = SystemCoreClock / 100;
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USB_OTG_FS->CTL |= USB_CTL_RESUME_MASK;
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while (cnt--) __NOP();
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USB_OTG_FS->CTL &= ~USB_CTL_RESUME_MASK;
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}
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void dcd_connect(uint8_t rhport)
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{
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(void) rhport;
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USB_OTG_FS->CTL |= USB_CTL_USBENSOFEN_MASK;
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}
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void dcd_disconnect(uint8_t rhport)
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{
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(void) rhport;
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USB_OTG_FS->CTL = 0;
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}
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//--------------------------------------------------------------------+
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// Endpoint API
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//--------------------------------------------------------------------+
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bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const * ep_desc)
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{
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(void) rhport;
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const unsigned ep_addr = ep_desc->bEndpointAddress;
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const unsigned epn = ep_addr & 0xFu;
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const unsigned dir = (ep_addr & TUSB_DIR_IN_MASK) ? TUSB_DIR_IN : TUSB_DIR_OUT;
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const unsigned xfer = ep_desc->bmAttributes.xfer;
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endpoint_state_t *ep = &_dcd.endpoint[epn][dir];
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const unsigned odd = ep->odd;
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buffer_descriptor_t *bd = &_dcd.bdt[epn][dir][0];
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/* No support for control transfer */
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TU_ASSERT(epn && (xfer != TUSB_XFER_CONTROL));
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ep->max_packet_size = ep_desc->wMaxPacketSize.size;
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unsigned val = USB_ENDPT_EPCTLDIS_MASK;
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val |= (xfer != TUSB_XFER_ISOCHRONOUS) ? USB_ENDPT_EPHSHK_MASK: 0;
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val |= dir ? USB_ENDPT_EPTXEN_MASK : USB_ENDPT_EPRXEN_MASK;
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USB_OTG_FS->EP_CTL[epn] |= val;
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if (xfer != TUSB_XFER_ISOCHRONOUS) {
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bd[odd].dts = 1;
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bd[odd].data = 0;
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bd[odd ^ 1].dts = 1;
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bd[odd ^ 1].data = 1;
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}
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return true;
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}
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void dcd_edpt_close_all (uint8_t rhport)
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{
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(void) rhport;
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// TODO implement dcd_edpt_close_all()
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}
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void dcd_edpt_close(uint8_t rhport, uint8_t ep_addr)
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{
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(void) rhport;
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const unsigned epn = ep_addr & 0xFu;
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const unsigned dir = (ep_addr & TUSB_DIR_IN_MASK) ? TUSB_DIR_IN : TUSB_DIR_OUT;
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endpoint_state_t *ep = &_dcd.endpoint[epn][dir];
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buffer_descriptor_t *bd = &_dcd.bdt[epn][dir][0];
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const unsigned msk = dir ? USB_ENDPT_EPTXEN_MASK : USB_ENDPT_EPRXEN_MASK;
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USB_OTG_FS->EP_CTL[epn] &= ~msk;
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ep->max_packet_size = 0;
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ep->length = 0;
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ep->remaining = 0;
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bd->head = 0;
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}
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bool dcd_edpt_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t* buffer, uint16_t total_bytes)
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{
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(void) rhport;
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NVIC_DisableIRQ(USB_FS_IRQn);
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const unsigned epn = ep_addr & 0xFu;
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const unsigned dir = (ep_addr & TUSB_DIR_IN_MASK) ? TUSB_DIR_IN : TUSB_DIR_OUT;
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endpoint_state_t *ep = &_dcd.endpoint[epn][dir];
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buffer_descriptor_t *bd = &_dcd.bdt[epn][dir][ep->odd];
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if (bd->own) {
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TU_LOG1("DCD XFER fail %x %d %lx %lx\r\n", ep_addr, total_bytes, ep->state, bd->head);
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return false; /* The last transfer has not completed */
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}
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ep->length = total_bytes;
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ep->remaining = total_bytes;
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const unsigned mps = ep->max_packet_size;
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if (total_bytes > mps) {
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buffer_descriptor_t *next = ep->odd ? bd - 1: bd + 1;
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/* When total_bytes is greater than the max packet size,
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* it prepares to the next transfer to avoid NAK in advance. */
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next->bc = total_bytes >= 2 * mps ? mps: total_bytes - mps;
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next->addr = buffer + mps;
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next->own = 1;
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}
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bd->bc = total_bytes >= mps ? mps: total_bytes;
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bd->addr = buffer;
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__DSB();
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bd->own = 1; /* the own bit must set after addr */
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NVIC_EnableIRQ(USB_FS_IRQn);
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return true;
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}
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void dcd_edpt_stall(uint8_t rhport, uint8_t ep_addr)
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{
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(void) rhport;
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const unsigned epn = ep_addr & 0xFu;
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if (0 == epn) {
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USB_OTG_FS->EP_CTL[epn] |= USB_ENDPT_EPSTALL_MASK;
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} else {
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const unsigned dir = (ep_addr & TUSB_DIR_IN_MASK) ? TUSB_DIR_IN : TUSB_DIR_OUT;
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buffer_descriptor_t *bd = _dcd.bdt[epn][dir];
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bd[0].bdt_stall = 1;
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bd[1].bdt_stall = 1;
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}
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}
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void dcd_edpt_clear_stall(uint8_t rhport, uint8_t ep_addr)
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{
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(void) rhport;
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const unsigned epn = ep_addr & 0xFu;
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const unsigned dir = (ep_addr & TUSB_DIR_IN_MASK) ? TUSB_DIR_IN : TUSB_DIR_OUT;
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const unsigned odd = _dcd.endpoint[epn][dir].odd;
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buffer_descriptor_t *bd = _dcd.bdt[epn][dir];
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bd[odd ^ 1].own = 0;
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bd[odd ^ 1].data = 1;
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bd[odd ^ 1].bdt_stall = 0;
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bd[odd].own = 0;
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bd[odd].data = 0;
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bd[odd].bdt_stall = 0;
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}
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//--------------------------------------------------------------------+
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// ISR
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//--------------------------------------------------------------------+
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void dcd_int_handler(uint8_t rhport)
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{
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(void) rhport;
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uint32_t is = USB_OTG_FS->INT_STAT;
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uint32_t msk = USB_OTG_FS->INT_ENB;
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USB_OTG_FS->INT_STAT = is & ~msk;
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is &= msk;
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if (is & USB_ISTAT_ERROR_MASK) {
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/* TODO: */
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uint32_t es = USB_OTG_FS->ERR_STAT;
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USB_OTG_FS->ERR_STAT = es;
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USB_OTG_FS->INT_STAT = is; /* discard any pending events */
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return;
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}
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if (is & USB_ISTAT_USBRST_MASK) {
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USB_OTG_FS->INT_STAT = is; /* discard any pending events */
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process_bus_reset(rhport);
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return;
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}
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if (is & USB_ISTAT_SLEEP_MASK) {
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USB_OTG_FS->INT_STAT = USB_ISTAT_SLEEP_MASK;
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|
process_bus_inactive(rhport);
|
|
return;
|
|
}
|
|
if (is & USB_ISTAT_RESUME_MASK) {
|
|
USB_OTG_FS->INT_STAT = USB_ISTAT_RESUME_MASK;
|
|
process_bus_active(rhport);
|
|
return;
|
|
}
|
|
if (is & USB_ISTAT_SOFTOK_MASK) {
|
|
USB_OTG_FS->INT_STAT = USB_ISTAT_SOFTOK_MASK;
|
|
dcd_event_bus_signal(rhport, DCD_EVENT_SOF, true);
|
|
return;
|
|
}
|
|
if (is & USB_ISTAT_STALL_MASK) {
|
|
USB_OTG_FS->INT_STAT = USB_ISTAT_STALL_MASK;
|
|
process_stall(rhport);
|
|
return;
|
|
}
|
|
if (is & USB_ISTAT_TOKDNE_MASK) {
|
|
process_tokdne(rhport);
|
|
return;
|
|
}
|
|
}
|
|
|
|
#endif
|