481 lines
16 KiB
C
481 lines
16 KiB
C
/******************************************************************
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***** *****
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***** Name: cs8900.c *****
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***** Ver.: 1.0 *****
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***** Date: 07/05/2001 *****
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***** Auth: Andreas Dannenberg *****
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***** HTWK Leipzig *****
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***** university of applied sciences *****
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***** Germany *****
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***** Func: ethernet packet-driver for use with LAN- *****
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***** controller CS8900 from Crystal/Cirrus Logic *****
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***** *****
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***** NXP: Module modified for use with NXP *****
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***** lpc43xx EMAC Ethernet controller *****
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***** *****
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******************************************************************/
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#include "../board.h"
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#if BOARD == BOARD_EA4357
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#include "emac.h"
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//#include "tcpip.h"
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#include "LPC43xx.h"
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#include "lpc43xx_scu.h"
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#include "lpc43xx_rgu.h"
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#define TIMEOUT 100000
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static unsigned short *rptr;
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static unsigned short *tptr;
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static unsigned int TxDescIndex = 0;
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static unsigned int RxDescIndex = 0;
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// Keil: function added to write PHY
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static void write_PHY (unsigned int PhyReg, unsigned short Value) {
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unsigned int tout;
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/* Write a data 'Value' to PHY register 'PhyReg'. */
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while(LPC_ETHERNET->MAC_MII_ADDR & GMII_BUSY); // Check GMII busy bit
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LPC_ETHERNET->MAC_MII_ADDR = (DP83848C_DEF_ADR<<11) | (PhyReg<<6) | GMII_WRITE;
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LPC_ETHERNET->MAC_MII_DATA = Value;
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LPC_ETHERNET->MAC_MII_ADDR |= GMII_BUSY; // Start PHY Write Cycle
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/* Wait utill operation completed */
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for (tout = 0; tout < MII_WR_TOUT; tout++) {
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if ((LPC_ETHERNET->MAC_MII_ADDR & GMII_BUSY) == 0) {
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break;
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}
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}
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if (tout == MII_WR_TOUT) // Trap the timeout
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while(1);
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}
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// Keil: function added to read PHY
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static unsigned short read_PHY (unsigned int PhyReg) {
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unsigned int tout, val;
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/* Read a PHY register 'PhyReg'. */
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while(LPC_ETHERNET->MAC_MII_ADDR & GMII_BUSY); // Check GMII busy bit
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LPC_ETHERNET->MAC_MII_ADDR = (DP83848C_DEF_ADR<<11) | (PhyReg<<6) | GMII_READ;
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LPC_ETHERNET->MAC_MII_ADDR |= GMII_BUSY; // Start PHY Read Cycle
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/* Wait until operation completed */
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for (tout = 0; tout < MII_RD_TOUT; tout++) {
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if ((LPC_ETHERNET->MAC_MII_ADDR & GMII_BUSY) == 0) {
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break;
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}
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}
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if (tout == MII_RD_TOUT) // Trap the timeout
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while(1);
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val = LPC_ETHERNET->MAC_MII_DATA;
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return (val);
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}
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// Keil: function added to initialize Rx Descriptors
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void rx_descr_init (void)
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{
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unsigned int i;
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for (i = 0; i < NUM_RX_DESC; i++) {
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RX_DESC_STAT(i) = OWN_BIT;
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RX_DESC_CTRL(i) = ETH_FRAG_SIZE;
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RX_BUFADDR(i) = RX_BUF(i);
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if (i == (NUM_RX_DESC-1)) // Last Descriptor?
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RX_DESC_CTRL(i) |= RX_END_RING;
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}
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/* Set Starting address of RX Descriptor list */
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LPC_ETHERNET->DMA_REC_DES_ADDR = RX_DESC_BASE;
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}
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// Keil: function added to initialize Tx Descriptors
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void tx_descr_init (void)
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{
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unsigned int i;
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for (i = 0; i < NUM_TX_DESC; i++) { // Take it out!!!!
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TX_DESC_STAT(i) = 0;
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TX_DESC_CTRL(i) = 0;
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TX_BUFADDR(i) = 0;
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}
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for (i = 0; i < NUM_TX_DESC; i++) {
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TX_DESC_STAT(i) = TX_LAST_SEGM | TX_FIRST_SEGM;
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TX_DESC_CTRL(i) = 0;
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TX_BUFADDR(i) = TX_BUF(i);
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if (i == (NUM_TX_DESC-1)) // Last Descriptor?
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TX_DESC_STAT(i) |= TX_END_RING;
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}
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/* Set Starting address of RX Descriptor list */
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LPC_ETHERNET->DMA_TRANS_DES_ADDR = TX_DESC_BASE;
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}
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// configure port-pins for use with LAN-controller,
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// reset it and send the configuration-sequence
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void Init_EMAC(void)
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{
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int id1, id2, tout, regv;
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unsigned phy_in_use = 0;
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/* Ethernet pins configuration */
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#if MII
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scu_pinmux(0xC ,1 , (MD_PLN | MD_EZI | MD_ZI), FUNC3); // ENET_MDC: PC_1 -> FUNC3
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scu_pinmux(0x1 ,17 , (MD_PLN | MD_EZI | MD_ZI), FUNC3); // ENET_MDIO: P1_17 -> FUNC3
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scu_pinmux(0x1 ,18 , (MD_PLN | MD_EZI | MD_ZI), FUNC3); // ENET_TXD0: P1_18 -> FUNC3
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scu_pinmux(0x1 ,20 , (MD_PLN | MD_EZI | MD_ZI), FUNC3); // ENET_TXD1: P1_20 -> FUNC3
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scu_pinmux(0x1 ,19 , (MD_PLN | MD_EZI | MD_ZI), FUNC0); // ENET_REF: P1_19 -> FUNC0 (default)
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// scu_pinmux(0xC ,4 , (MD_PLN | MD_EZI | MD_ZI), FUNC3); // ENET_TX_EN: PC_4 -> FUNC3
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scu_pinmux(0x0 ,1 , (MD_PLN | MD_EZI | MD_ZI), FUNC6); // ENET_TX_EN: P0_1 -> FUNC6
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scu_pinmux(0x1 ,15 , (MD_PLN | MD_EZI | MD_ZI), FUNC3); // ENET_RXD0: P1_15 -> FUNC3
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scu_pinmux(0x0 ,0 , (MD_PLN | MD_EZI | MD_ZI), FUNC2); // ENET_RXD1: P0_0 -> FUNC2
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// scu_pinmux(0x1 ,16 , (MD_PLN | MD_EZI | MD_ZI), FUNC3); // ENET_CRS: P1_16 -> FUNC3
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scu_pinmux(0x9 ,0 , (MD_PLN | MD_EZI | MD_ZI), FUNC5); // ENET_CRS: P9_0 -> FUNC5
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// scu_pinmux(0xC ,9 , (MD_PLN | MD_EZI | MD_ZI), FUNC3); // ENET_RX_ER: PC_9 -> FUNC3
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scu_pinmux(0x9 ,1 , (MD_PLN | MD_EZI | MD_ZI), FUNC5); // ENET_RX_ER: P9_1 -> FUNC5
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// scu_pinmux(0xC ,8 , (MD_PLN | MD_EZI | MD_ZI), FUNC3); // ENET_RXDV: PC_8 -> FUNC3
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scu_pinmux(0x1 ,16 , (MD_PLN | MD_EZI | MD_ZI), FUNC7); // ENET_RXDV: P1_16 -> FUNC7
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#else
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scu_pinmux(0xC ,1 , (MD_EHS | MD_PLN | MD_EZI | MD_ZI), FUNC3); // ENET_MDC: PC_1 -> FUNC3
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scu_pinmux(0x1 ,17 , (MD_EHS | MD_PLN | MD_EZI | MD_ZI), FUNC3); // ENET_MDIO: P1_17 -> FUNC3
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scu_pinmux(0x1 ,18 , (MD_EHS | MD_PLN | MD_EZI | MD_ZI), FUNC3); // ENET_TXD0: P1_18 -> FUNC3
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scu_pinmux(0x1 ,20 , (MD_EHS | MD_PLN | MD_EZI | MD_ZI), FUNC3); // ENET_TXD1: P1_20 -> FUNC3
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scu_pinmux(0x1 ,19 , (MD_EHS | MD_PLN | MD_EZI | MD_ZI), FUNC0); // ENET_REF: P1_19 -> FUNC0 (default)
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// scu_pinmux(0xC ,4 , (MD_EHS | MD_PLN | MD_EZI | MD_ZI), FUNC3); // ENET_TX_EN: PC_4 -> FUNC3
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scu_pinmux(0x0 ,1 , (MD_PLN | MD_EZI | MD_ZI), FUNC6); // ENET_TX_EN: P0_1 -> FUNC6
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scu_pinmux(0x1 ,15 , (MD_EHS | MD_PLN | MD_EZI | MD_ZI), FUNC3); // ENET_RXD0: P1_15 -> FUNC3
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scu_pinmux(0x0 ,0 , (MD_EHS | MD_PLN | MD_EZI | MD_ZI), FUNC2); // ENET_RXD1: P0_0 -> FUNC2
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// scu_pinmux(0x1 ,16 , (MD_EHS | MD_PLN | MD_EZI | MD_ZI), FUNC3); // ENET_CRS: P1_16 -> FUNC3
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// scu_pinmux(0x9 ,0 , (MD_PLN | MD_EZI | MD_ZI), FUNC5); // ENET_CRS: P9_0 -> FUNC5
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// scu_pinmux(0xC ,9 , (MD_EHS | MD_PLN | MD_EZI | MD_ZI), FUNC3); // ENET_RX_ER: PC_9 -> FUNC3
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// scu_pinmux(0x9 ,1 , (MD_PLN | MD_EZI | MD_ZI), FUNC5); // ENET_RX_ER: P9_1 -> FUNC5
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// scu_pinmux(0xC ,8 , (MD_EHS | MD_PLN | MD_EZI | MD_ZI), FUNC3); // ENET_RXDV: PC_8 -> FUNC3
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scu_pinmux(0x1 ,16 , (MD_PLN | MD_EZI | MD_ZI), FUNC7); // ENET_RXDV: P1_16 -> FUNC7
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#endif
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#if MII /* Select MII interface */ // check MUXING for new Eagle...
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// scu_pinmux(0xC ,6 , (MD_PLN | MD_EZI | MD_ZI), FUNC3); // ENET_RXD2: PC_6 -> FUNC3
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scu_pinmux(0x9 ,3 , (MD_PLN | MD_EZI | MD_ZI), FUNC5); // ENET_RXD2: P9_3 -> FUNC5
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// scu_pinmux(0xC ,7 , (MD_PLN | MD_EZI | MD_ZI), FUNC3); // ENET_RXD3: PC_7 -> FUNC3
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scu_pinmux(0x9 ,2 , (MD_PLN | MD_EZI | MD_ZI), FUNC5); // ENET_RXD3: P9_2 -> FUNC5
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scu_pinmux(0xC ,0 , (MD_PLN | MD_EZI | MD_ZI), FUNC3); // ENET_RXLK: PC_0 -> FUNC3
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// scu_pinmux(0xC ,2 , (MD_PLN | MD_EZI | MD_ZI), FUNC3); // ENET_TXD2: PC_2 -> FUNC3
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scu_pinmux(0x9 ,4 , (MD_PLN | MD_EZI | MD_ZI), FUNC5); // ENET_TXD2: P9_4 -> FUNC5
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// scu_pinmux(0xC ,3 , (MD_PLN | MD_EZI | MD_ZI), FUNC3); // ENET_TXD3: PC_3 -> FUNC3
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scu_pinmux(0x9 ,5 , (MD_PLN | MD_EZI | MD_ZI), FUNC5); // ENET_TXD3: P9_5 -> FUNC5
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// scu_pinmux(0xC ,5 , (MD_PLN | MD_EZI | MD_ZI), FUNC3); // ENET_TX_ER: PC_5 -> FUNC3
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scu_pinmux(0xC ,5 , (MD_PLN | MD_EZI | MD_ZI), FUNC3); // ENET_TX_ER: PC_5 -> FUNC3
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// scu_pinmux(0x0 ,1 , (MD_PLN | MD_EZI | MD_ZI), FUNC2); // ENET_COL: P0_1 -> FUNC2
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scu_pinmux(0x9 ,6 , (MD_PLN | MD_EZI | MD_ZI), FUNC5); // ENET_COL: P9_6 -> FUNC5
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#else /* Select RMII interface */
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LPC_CREG->CREG6 |= RMII_SELECT;
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#endif
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RGU_SoftReset(RGU_SIG_ETHERNET);
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while(1){ // Confirm the reset happened
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if (LPC_RGU->RESET_ACTIVE_STATUS0 & (1<<ETHERNET_RST))
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break;
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}
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LPC_ETHERNET->DMA_BUS_MODE |= DMA_SOFT_RESET; // Reset all GMAC Subsystem internal registers and logic
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while(LPC_ETHERNET->DMA_BUS_MODE & DMA_SOFT_RESET); // Wait for software reset completion
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/* Put the DP83848C in reset mode */
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write_PHY (PHY_REG_BMCR, PHY_BMCR_RESET);
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/* Wait for hardware reset to end. */
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for (tout = 0; tout < TIMEOUT; tout++) {
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regv = read_PHY (PHY_REG_BMCR);
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if (!(regv & PHY_BMCR_RESET)) {
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/* Reset complete */
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break;
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}
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}
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/* Check if this is a DP83848C PHY. */
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id1 = read_PHY (PHY_REG_IDR1);
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id2 = read_PHY (PHY_REG_IDR2);
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if (((id1 << 16) | (id2 & 0xFFF0)) == DP83848C_ID) {
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phy_in_use = DP83848C_ID;
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}
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else if (((id1 << 16) | (id2 & 0xFFF0)) == LAN8720_ID) {
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phy_in_use = LAN8720_ID;
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}
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if (phy_in_use != 0) {
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/* Configure the PHY device */
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#if !MII
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write_PHY (PHY_REG_RBR, 0x20);
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#endif
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/* Use autonegotiation about the link speed. */
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write_PHY (PHY_REG_BMCR, PHY_AUTO_NEG);
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/* Wait to complete Auto_Negotiation. */
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for (tout = 0; tout < TIMEOUT; tout++) {
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regv = read_PHY (PHY_REG_BMSR);
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if (regv & PHY_AUTO_NEG_DONE) {
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/* Autonegotiation Complete. */
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break;
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}
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}
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}
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/* Check the link status. */
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for (tout = 0; tout < TIMEOUT; tout++) {
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regv = read_PHY (PHY_REG_STS);
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if (regv & LINK_VALID_STS) {
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/* Link is on. */
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break;
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}
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}
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// Configure the EMAC with the established parameters
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switch (phy_in_use) {
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case DP83848C_ID:
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/* Configure Full/Half Duplex mode. */
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if (regv & FULL_DUP_STS) {
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/* Full duplex is enabled. */
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LPC_ETHERNET->MAC_CONFIG |= MAC_DUPMODE;
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}
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/* Configure 100MBit/10MBit mode. */
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if (~(regv & SPEED_10M_STS)) {
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/* 100MBit mode. */
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LPC_ETHERNET->MAC_CONFIG |= MAC_100MPS;
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}
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// value = ReadFromPHY (PHY_REG_STS); /* PHY Extended Status Register */
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// // Now configure for full/half duplex mode
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// if (value & 0x0004) {
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// // We are in full duplex is enabled mode
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// LPC_ETHERNET->MAC2 |= MAC2_FULL_DUP;
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// LPC_ETHERNET->Command |= CR_FULL_DUP;
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// LPC_ETHERNET->IPGT = IPGT_FULL_DUP;
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// }
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// else {
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// // Otherwise we are in half duplex mode
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// LPC_ETHERNET->IPGT = IPGT_HALF_DUP;
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// }
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// // Now configure 100MBit or 10MBit mode
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// if (value & 0x0002) {
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// // 10MBit mode
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// LPC_ETHERNET->SUPP = 0;
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// }
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// else {
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// // 100MBit mode
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// LPC_ETHERNET->SUPP = SUPP_SPEED;
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// }
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break;
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case LAN8720_ID:
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regv = read_PHY (PHY_REG_SCSR); /* PHY Extended Status Register */
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// Now configure for full/half duplex mode
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if (regv & (1<<4)) { /* bit 4: 1 = Full Duplex, 0 = Half Duplex */
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// We are in full duplex is enabled mode
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LPC_ETHERNET->MAC_CONFIG |= MAC_DUPMODE;
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}
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// Now configure 100MBit or 10MBit mode
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if (regv & (1<<3)) { /* bit 3: 1 = 100Mbps, 0 = 10Mbps */
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// 100MBit mode
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LPC_ETHERNET->MAC_CONFIG |= MAC_100MPS;
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}
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break;
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}
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/* Set the Ethernet MAC Address registers */
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LPC_ETHERNET->MAC_ADDR0_HIGH = (MYMAC_6 << 8) | MYMAC_5;
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LPC_ETHERNET->MAC_ADDR0_LOW = (MYMAC_4 << 24) | (MYMAC_3 << 16) | (MYMAC_2 << 8) | MYMAC_1;
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/* Initialize Descriptor Lists */
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rx_descr_init();
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tx_descr_init();
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/* Configure Filter */
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LPC_ETHERNET->MAC_FRAME_FILTER = MAC_PROMISCUOUS | MAC_RECEIVEALL;
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/* Enable Receiver and Transmitter */
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LPC_ETHERNET->MAC_CONFIG |= (MAC_TX_ENABLE | MAC_RX_ENABLE);
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/* Enable interrupts */
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//LPC_ETHERNET->DMA_INT_EN = DMA_INT_NOR_SUM | DMA_INT_RECEIVE | DMA_INT_TRANSMIT;
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/* Start Transmission & Receive processes */
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LPC_ETHERNET->DMA_OP_MODE |= (DMA_SS_TRANSMIT | DMA_SS_RECEIVE );
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}
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// reads a word in little-endian byte order from RX_BUFFER
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unsigned short ReadFrame_EMAC(void)
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{
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return (*rptr++);
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}
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// easyWEB internal function
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// help function to swap the byte order of a WORD
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unsigned short SwapBytes(unsigned short Data)
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{
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return (Data >> 8) | (Data << 8);
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}
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// reads a word in big-endian byte order from RX_FRAME_PORT
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// (useful to avoid permanent byte-swapping while reading
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// TCP/IP-data)
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unsigned short ReadFrameBE_EMAC(void)
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{
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unsigned short ReturnValue;
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ReturnValue = SwapBytes (*rptr++);
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return (ReturnValue);
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}
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// copies bytes from frame port to MCU-memory
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// NOTES: * an odd number of byte may only be transfered
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// if the frame is read to the end!
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// * MCU-memory MUST start at word-boundary
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void CopyFromFrame_EMAC(void *Dest, unsigned short Size)
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{
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unsigned short * piDest; // Keil: Pointer added to correct expression
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piDest = Dest; // Keil: Line added
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while (Size > 1) {
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*piDest++ = ReadFrame_EMAC();
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Size -= 2;
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}
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if (Size) { // check for leftover byte...
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*(unsigned char *)piDest = (char)ReadFrame_EMAC();// the LAN-Controller will return 0
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} // for the highbyte
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}
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// does a dummy read on frame-I/O-port
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// NOTE: only an even number of bytes is read!
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void DummyReadFrame_EMAC(unsigned short Size) // discards an EVEN number of bytes
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{ // from RX-fifo
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while (Size > 1) {
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ReadFrame_EMAC();
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Size -= 2;
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}
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}
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// Reads the length of the received ethernet frame and checks if the
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// destination address is a broadcast message or not
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// returns the frame length
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unsigned short StartReadFrame(void) {
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unsigned short RxLen;
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if ((RX_DESC_STAT(RxDescIndex) & OWN_BIT) == 0) {
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RxLen = (RX_DESC_STAT(RxDescIndex) >> 16) & 0x03FFF;
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rptr = (unsigned short *)RX_BUFADDR(RxDescIndex);
|
|
return(RxLen);
|
|
}
|
|
return 0;
|
|
|
|
}
|
|
|
|
void EndReadFrame(void) {
|
|
|
|
RX_DESC_STAT(RxDescIndex) = OWN_BIT;
|
|
RxDescIndex++;
|
|
if (RxDescIndex == NUM_RX_DESC)
|
|
RxDescIndex = 0;
|
|
}
|
|
|
|
unsigned int CheckFrameReceived(void) { // Packet received ?
|
|
|
|
if ((RX_DESC_STAT(RxDescIndex) & OWN_BIT) == 0)
|
|
return(1);
|
|
else
|
|
return(0);
|
|
}
|
|
|
|
// requests space in EMAC memory for storing an outgoing frame
|
|
|
|
void RequestSend(unsigned short FrameSize)
|
|
{
|
|
tptr = (unsigned short *)TX_BUFADDR(TxDescIndex);
|
|
TX_DESC_CTRL(TxDescIndex) = FrameSize;
|
|
}
|
|
|
|
// check if ethernet controller is ready to accept the
|
|
// frame we want to send
|
|
|
|
unsigned int Rdy4Tx(void)
|
|
{
|
|
return (1); // the ethernet controller transmits much faster
|
|
} // than the CPU can load its buffers
|
|
|
|
|
|
// writes a word in little-endian byte order to TX_BUFFER
|
|
void WriteFrame_EMAC(unsigned short Data)
|
|
{
|
|
*tptr++ = Data;
|
|
}
|
|
|
|
// copies bytes from MCU-memory to frame port
|
|
// NOTES: * an odd number of byte may only be transfered
|
|
// if the frame is written to the end!
|
|
// * MCU-memory MUST start at word-boundary
|
|
|
|
void CopyToFrame_EMAC(void *Source, unsigned int Size)
|
|
{
|
|
unsigned short * piSource;
|
|
// unsigned int idx;
|
|
|
|
piSource = Source;
|
|
Size = (Size + 1) & 0xFFFE; // round Size up to next even number
|
|
while (Size > 0) {
|
|
WriteFrame_EMAC(*piSource++);
|
|
Size -= 2;
|
|
}
|
|
TX_DESC_STAT(TxDescIndex) |= OWN_BIT;
|
|
LPC_ETHERNET->DMA_TRANS_POLL_DEMAND = 1; // Wake Up the DMA if it's in Suspended Mode
|
|
TxDescIndex++;
|
|
if (TxDescIndex == NUM_TX_DESC)
|
|
TxDescIndex = 0;
|
|
}
|
|
|
|
#endif
|
|
|