601 lines
18 KiB
C
601 lines
18 KiB
C
/********************************** (C) COPYRIGHT *******************************
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* File Name : system_ch32v10x.c
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* Author : WCH
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* Version : V1.0.0
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* Date : 2020/04/30
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* Description : CH32V10x Device Peripheral Access Layer System Source File.
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*********************************************************************************
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* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
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* Attention: This software (modified or not) and binary are used for
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* microcontroller manufactured by Nanjing Qinheng Microelectronics.
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*******************************************************************************/
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#include "ch32v10x.h"
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/*
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* Uncomment the line corresponding to the desired System clock (SYSCLK) frequency (after
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* reset the HSI is used as SYSCLK source).
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* If none of the define below is enabled, the HSI is used as System clock source.
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*/
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//#define SYSCLK_FREQ_HSE HSE_VALUE
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//#define SYSCLK_FREQ_48MHz_HSE 48000000
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//#define SYSCLK_FREQ_56MHz_HSE 56000000
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#define SYSCLK_FREQ_72MHz_HSE 72000000
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//#define SYSCLK_FREQ_HSI HSI_VALUE
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//#define SYSCLK_FREQ_48MHz_HSI 48000000
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//#define SYSCLK_FREQ_56MHz_HSI 56000000
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//#define SYSCLK_FREQ_72MHz_HSI 72000000
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/* Clock Definitions */
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#ifdef SYSCLK_FREQ_HSE
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uint32_t SystemCoreClock = SYSCLK_FREQ_HSE; /* System Clock Frequency (Core Clock) */
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#elif defined SYSCLK_FREQ_48MHz_HSE
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uint32_t SystemCoreClock = SYSCLK_FREQ_48MHz_HSE; /* System Clock Frequency (Core Clock) */
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#elif defined SYSCLK_FREQ_56MHz_HSE
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uint32_t SystemCoreClock = SYSCLK_FREQ_56MHz_HSE; /* System Clock Frequency (Core Clock) */
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#elif defined SYSCLK_FREQ_72MHz_HSE
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uint32_t SystemCoreClock = SYSCLK_FREQ_72MHz_HSE; /* System Clock Frequency (Core Clock) */
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#elif defined SYSCLK_FREQ_48MHz_HSI
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uint32_t SystemCoreClock = SYSCLK_FREQ_48MHz_HSI; /* System Clock Frequency (Core Clock) */
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#elif defined SYSCLK_FREQ_56MHz_HSI
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uint32_t SystemCoreClock = SYSCLK_FREQ_56MHz_HSI; /* System Clock Frequency (Core Clock) */
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#elif defined SYSCLK_FREQ_72MHz_HSI
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uint32_t SystemCoreClock = SYSCLK_FREQ_72MHz_HSI; /* System Clock Frequency (Core Clock) */
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#else
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uint32_t SystemCoreClock = HSI_VALUE; /* System Clock Frequency (Core Clock) */
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#endif
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__I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
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/* ch32v10x_system_private_function_proto_types */
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static void SetSysClock(void);
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#ifdef SYSCLK_FREQ_HSE
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static void SetSysClockToHSE( void );
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#elif defined SYSCLK_FREQ_48MHz_HSE
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static void SetSysClockTo48_HSE( void );
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#elif defined SYSCLK_FREQ_56MHz_HSE
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static void SetSysClockTo56_HSE( void );
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#elif defined SYSCLK_FREQ_72MHz_HSE
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static void SetSysClockTo72_HSE( void );
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#elif defined SYSCLK_FREQ_48MHz_HSI
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static void SetSysClockTo48_HSI( void );
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#elif defined SYSCLK_FREQ_56MHz_HSI
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static void SetSysClockTo56_HSI( void );
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#elif defined SYSCLK_FREQ_72MHz_HSI
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static void SetSysClockTo72_HSI( void );
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#endif
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/*********************************************************************
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* @fn SystemInit
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*
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* @brief Setup the microcontroller system Initialize the Embedded Flash Interface,
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* the PLL and update the SystemCoreClock variable.
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*
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* @return none
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*/
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void SystemInit(void)
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{
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RCC->CTLR |= (uint32_t)0x00000001;
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RCC->CFGR0 &= (uint32_t)0xF8FF0000;
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RCC->CTLR &= (uint32_t)0xFEF6FFFF;
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RCC->CTLR &= (uint32_t)0xFFFBFFFF;
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RCC->CFGR0 &= (uint32_t)0xFF80FFFF;
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RCC->INTR = 0x009F0000;
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SetSysClock();
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}
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/*********************************************************************
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* @fn SystemCoreClockUpdate
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*
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* @brief Update SystemCoreClock variable according to Clock Register Values.
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*
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* @return none
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*/
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void SystemCoreClockUpdate(void)
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{
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uint32_t tmp = 0, pllmull = 0, pllsource = 0;
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tmp = RCC->CFGR0 & RCC_SWS;
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switch(tmp)
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{
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case 0x00:
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SystemCoreClock = HSI_VALUE;
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break;
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case 0x04:
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SystemCoreClock = HSE_VALUE;
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break;
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case 0x08:
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pllmull = RCC->CFGR0 & RCC_PLLMULL;
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pllsource = RCC->CFGR0 & RCC_PLLSRC;
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pllmull = (pllmull >> 18) + 2;
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if(pllsource == 0x00)
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{
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if( EXTEN->EXTEN_CTR & EXTEN_PLL_HSI_PRE )
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{
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SystemCoreClock = ( HSI_VALUE ) * pllmull;
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}
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else
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{
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SystemCoreClock = ( HSI_VALUE >> 1 ) * pllmull;
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}
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}
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else
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{
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if((RCC->CFGR0 & RCC_PLLXTPRE) != (uint32_t)RESET)
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{
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SystemCoreClock = (HSE_VALUE >> 1) * pllmull;
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}
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else
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{
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SystemCoreClock = HSE_VALUE * pllmull;
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}
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}
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break;
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default:
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SystemCoreClock = HSI_VALUE;
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break;
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}
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tmp = AHBPrescTable[((RCC->CFGR0 & RCC_HPRE) >> 4)];
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SystemCoreClock >>= tmp;
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}
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/*********************************************************************
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* @fn SetSysClock
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*
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* @brief Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
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*
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* @return none
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*/
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static void SetSysClock(void)
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{
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//GPIO_IPD_Unused();
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#ifdef SYSCLK_FREQ_HSE
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SetSysClockToHSE();
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#elif defined SYSCLK_FREQ_48MHz_HSE
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SetSysClockTo48_HSE();
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#elif defined SYSCLK_FREQ_56MHz_HSE
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SetSysClockTo56_HSE();
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#elif defined SYSCLK_FREQ_72MHz_HSE
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SetSysClockTo72_HSE();
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#elif defined SYSCLK_FREQ_48MHz_HSI
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SetSysClockTo48_HSI();
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#elif defined SYSCLK_FREQ_56MHz_HSI
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SetSysClockTo56_HSI();
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#elif defined SYSCLK_FREQ_72MHz_HSI
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SetSysClockTo72_HSI();
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#endif
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/* If none of the define above is enabled, the HSI is used as System clock
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* source (default after reset)
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*/
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}
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#ifdef SYSCLK_FREQ_HSE
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/*********************************************************************
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* @fn SetSysClockToHSE
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*
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* @brief Sets HSE as System clock source and configure HCLK, PCLK2 and PCLK1 prescalers.
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*
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* @return none
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*/
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static void SetSysClockToHSE(void)
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{
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__IO uint32_t StartUpCounter = 0, HSEStatus = 0;
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RCC->CTLR |= ((uint32_t)RCC_HSEON);
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/* Wait till HSE is ready and if Time out is reached exit */
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do
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{
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HSEStatus = RCC->CTLR & RCC_HSERDY;
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StartUpCounter++;
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} while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
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if((RCC->CTLR & RCC_HSERDY) != RESET)
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{
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HSEStatus = (uint32_t)0x01;
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}
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else
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{
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HSEStatus = (uint32_t)0x00;
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}
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if(HSEStatus == (uint32_t)0x01)
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{
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FLASH->ACTLR |= FLASH_ACTLR_PRFTBE;
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/* Flash 0 wait state */
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FLASH->ACTLR &= (uint32_t)((uint32_t)~FLASH_ACTLR_LATENCY);
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FLASH->ACTLR |= (uint32_t)FLASH_ACTLR_LATENCY_0;
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/* HCLK = SYSCLK */
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RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1;
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/* PCLK2 = HCLK */
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RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1;
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/* PCLK1 = HCLK */
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RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV1;
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/* Select HSE as system clock source */
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RCC->CFGR0 &= (uint32_t)((uint32_t) ~(RCC_SW));
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RCC->CFGR0 |= (uint32_t)RCC_SW_HSE;
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/* Wait till HSE is used as system clock source */
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while((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x04)
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{
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}
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}
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else
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{
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/* If HSE fails to start-up, the application will have wrong clock
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* configuration. User can add here some code to deal with this error
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*/
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}
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}
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#elif defined SYSCLK_FREQ_48MHz_HSE
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/*********************************************************************
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* @fn SetSysClockTo48_HSE
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*
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* @brief Sets System clock frequency to 48MHz and configure HCLK, PCLK2 and PCLK1 prescalers.
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*
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* @return none
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*/
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static void SetSysClockTo48_HSE(void)
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{
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__IO uint32_t StartUpCounter = 0, HSEStatus = 0;
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RCC->CTLR |= ((uint32_t)RCC_HSEON);
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/* Wait till HSE is ready and if Time out is reached exit */
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do
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{
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HSEStatus = RCC->CTLR & RCC_HSERDY;
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StartUpCounter++;
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} while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
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if((RCC->CTLR & RCC_HSERDY) != RESET)
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{
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HSEStatus = (uint32_t)0x01;
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}
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else
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{
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HSEStatus = (uint32_t)0x00;
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}
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if(HSEStatus == (uint32_t)0x01)
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{
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/* Enable Prefetch Buffer */
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FLASH->ACTLR |= FLASH_ACTLR_PRFTBE;
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/* Flash 1 wait state */
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FLASH->ACTLR &= (uint32_t)((uint32_t)~FLASH_ACTLR_LATENCY);
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FLASH->ACTLR |= (uint32_t)FLASH_ACTLR_LATENCY_1;
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/* HCLK = SYSCLK */
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RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1;
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/* PCLK2 = HCLK */
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RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1;
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/* PCLK1 = HCLK */
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RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2;
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/* PLL configuration: PLLCLK = HSE * 6 = 48 MHz */
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RCC->CFGR0 &= (uint32_t)((uint32_t) ~(RCC_PLLSRC | RCC_PLLXTPRE | RCC_PLLMULL));
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RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSE | RCC_PLLMULL6);
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/* Enable PLL */
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RCC->CTLR |= RCC_PLLON;
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/* Wait till PLL is ready */
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while((RCC->CTLR & RCC_PLLRDY) == 0)
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{
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}
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/* Select PLL as system clock source */
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RCC->CFGR0 &= (uint32_t)((uint32_t) ~(RCC_SW));
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RCC->CFGR0 |= (uint32_t)RCC_SW_PLL;
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/* Wait till PLL is used as system clock source */
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while((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08)
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{
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}
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}
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else
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{
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/*
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* If HSE fails to start-up, the application will have wrong clock
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* configuration. User can add here some code to deal with this error
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*/
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}
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}
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#elif defined SYSCLK_FREQ_56MHz_HSE
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/*********************************************************************
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* @fn SetSysClockTo56_HSE
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*
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* @brief Sets System clock frequency to 56MHz and configure HCLK, PCLK2 and PCLK1 prescalers.
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*
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* @return none
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*/
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static void SetSysClockTo56_HSE(void)
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{
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__IO uint32_t StartUpCounter = 0, HSEStatus = 0;
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RCC->CTLR |= ((uint32_t)RCC_HSEON);
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/* Wait till HSE is ready and if Time out is reached exit */
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do
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{
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HSEStatus = RCC->CTLR & RCC_HSERDY;
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StartUpCounter++;
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} while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
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if((RCC->CTLR & RCC_HSERDY) != RESET)
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{
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HSEStatus = (uint32_t)0x01;
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}
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else
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{
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HSEStatus = (uint32_t)0x00;
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}
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if(HSEStatus == (uint32_t)0x01)
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{
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/* Enable Prefetch Buffer */
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FLASH->ACTLR |= FLASH_ACTLR_PRFTBE;
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/* Flash 2 wait state */
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FLASH->ACTLR &= (uint32_t)((uint32_t)~FLASH_ACTLR_LATENCY);
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FLASH->ACTLR |= (uint32_t)FLASH_ACTLR_LATENCY_2;
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/* HCLK = SYSCLK */
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RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1;
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/* PCLK2 = HCLK */
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RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1;
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/* PCLK1 = HCLK */
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RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2;
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/* PLL configuration: PLLCLK = HSE * 7 = 56 MHz */
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RCC->CFGR0 &= (uint32_t)((uint32_t) ~(RCC_PLLSRC | RCC_PLLXTPRE | RCC_PLLMULL));
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RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSE | RCC_PLLMULL7);
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/* Enable PLL */
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RCC->CTLR |= RCC_PLLON;
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/* Wait till PLL is ready */
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while((RCC->CTLR & RCC_PLLRDY) == 0)
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{
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}
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/* Select PLL as system clock source */
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RCC->CFGR0 &= (uint32_t)((uint32_t) ~(RCC_SW));
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RCC->CFGR0 |= (uint32_t)RCC_SW_PLL;
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/* Wait till PLL is used as system clock source */
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while((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08)
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{
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}
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}
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else
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{
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/*
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* If HSE fails to start-up, the application will have wrong clock
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* configuration. User can add here some code to deal with this error
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*/
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}
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}
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#elif defined SYSCLK_FREQ_72MHz_HSE
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/*********************************************************************
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* @fn SetSysClockTo72_HSE
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*
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* @brief Sets System clock frequency to 72MHz and configure HCLK, PCLK2 and PCLK1 prescalers.
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*
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* @return none
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*/
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static void SetSysClockTo72_HSE(void)
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{
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__IO uint32_t StartUpCounter = 0, HSEStatus = 0;
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RCC->CTLR |= ((uint32_t)RCC_HSEON);
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/* Wait till HSE is ready and if Time out is reached exit */
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do
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{
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HSEStatus = RCC->CTLR & RCC_HSERDY;
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StartUpCounter++;
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} while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
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if((RCC->CTLR & RCC_HSERDY) != RESET)
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{
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HSEStatus = (uint32_t)0x01;
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}
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else
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{
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HSEStatus = (uint32_t)0x00;
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}
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if(HSEStatus == (uint32_t)0x01)
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{
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/* Enable Prefetch Buffer */
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FLASH->ACTLR |= FLASH_ACTLR_PRFTBE;
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/* Flash 2 wait state */
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FLASH->ACTLR &= (uint32_t)((uint32_t)~FLASH_ACTLR_LATENCY);
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FLASH->ACTLR |= (uint32_t)FLASH_ACTLR_LATENCY_2;
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/* HCLK = SYSCLK */
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RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1;
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/* PCLK2 = HCLK */
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RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1;
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/* PCLK1 = HCLK */
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RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2;
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/* PLL configuration: PLLCLK = HSE * 9 = 72 MHz */
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RCC->CFGR0 &= (uint32_t)((uint32_t) ~(RCC_PLLSRC | RCC_PLLXTPRE |
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RCC_PLLMULL));
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RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSE | RCC_PLLMULL9);
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/* Enable PLL */
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RCC->CTLR |= RCC_PLLON;
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/* Wait till PLL is ready */
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while((RCC->CTLR & RCC_PLLRDY) == 0)
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{
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}
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/* Select PLL as system clock source */
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RCC->CFGR0 &= (uint32_t)((uint32_t) ~(RCC_SW));
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RCC->CFGR0 |= (uint32_t)RCC_SW_PLL;
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/* Wait till PLL is used as system clock source */
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while((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08)
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{
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}
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}
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else
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{
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/*
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* If HSE fails to start-up, the application will have wrong clock
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* configuration. User can add here some code to deal with this error
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*/
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}
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}
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#elif defined SYSCLK_FREQ_48MHz_HSI
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/*********************************************************************
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* @fn SetSysClockTo48_HSI
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*
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* @brief Sets System clock frequency to 48MHz and configure HCLK, PCLK2 and PCLK1 prescalers.
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*
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* @return none
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*/
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static void SetSysClockTo48_HSI(void)
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{
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EXTEN->EXTEN_CTR |= EXTEN_PLL_HSI_PRE;
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/* Enable Prefetch Buffer */
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FLASH->ACTLR |= FLASH_ACTLR_PRFTBE;
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/* Flash 1 wait state */
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FLASH->ACTLR &= (uint32_t)((uint32_t)~FLASH_ACTLR_LATENCY);
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FLASH->ACTLR |= (uint32_t)FLASH_ACTLR_LATENCY_1;
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/* HCLK = SYSCLK */
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RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1;
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/* PCLK2 = HCLK */
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RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1;
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/* PCLK1 = HCLK */
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RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2;
|
|
|
|
/* PLL configuration: PLLCLK = HSI * 6 = 48 MHz */
|
|
RCC->CFGR0 &= (uint32_t)((uint32_t) ~(RCC_PLLSRC | RCC_PLLXTPRE | RCC_PLLMULL));
|
|
RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSI_Div2 | RCC_PLLMULL6);
|
|
|
|
/* Enable PLL */
|
|
RCC->CTLR |= RCC_PLLON;
|
|
/* Wait till PLL is ready */
|
|
while((RCC->CTLR & RCC_PLLRDY) == 0)
|
|
{
|
|
}
|
|
/* Select PLL as system clock source */
|
|
RCC->CFGR0 &= (uint32_t)((uint32_t) ~(RCC_SW));
|
|
RCC->CFGR0 |= (uint32_t)RCC_SW_PLL;
|
|
/* Wait till PLL is used as system clock source */
|
|
while((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08)
|
|
{
|
|
}
|
|
}
|
|
|
|
#elif defined SYSCLK_FREQ_56MHz_HSI
|
|
|
|
/*********************************************************************
|
|
* @fn SetSysClockTo56_HSI
|
|
*
|
|
* @brief Sets System clock frequency to 56MHz and configure HCLK, PCLK2 and PCLK1 prescalers.
|
|
*
|
|
* @return none
|
|
*/
|
|
static void SetSysClockTo56_HSI(void)
|
|
{
|
|
EXTEN->EXTEN_CTR |= EXTEN_PLL_HSI_PRE;
|
|
|
|
/* Enable Prefetch Buffer */
|
|
FLASH->ACTLR |= FLASH_ACTLR_PRFTBE;
|
|
|
|
/* Flash 1 wait state */
|
|
FLASH->ACTLR &= (uint32_t)((uint32_t)~FLASH_ACTLR_LATENCY);
|
|
FLASH->ACTLR |= (uint32_t)FLASH_ACTLR_LATENCY_1;
|
|
|
|
/* HCLK = SYSCLK */
|
|
RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1;
|
|
/* PCLK2 = HCLK */
|
|
RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1;
|
|
/* PCLK1 = HCLK */
|
|
RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2;
|
|
|
|
/* PLL configuration: PLLCLK = HSI * 7 = 56 MHz */
|
|
RCC->CFGR0 &= (uint32_t)((uint32_t) ~(RCC_PLLSRC | RCC_PLLXTPRE | RCC_PLLMULL));
|
|
RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSI_Div2 | RCC_PLLMULL7);
|
|
|
|
/* Enable PLL */
|
|
RCC->CTLR |= RCC_PLLON;
|
|
/* Wait till PLL is ready */
|
|
while((RCC->CTLR & RCC_PLLRDY) == 0)
|
|
{
|
|
}
|
|
/* Select PLL as system clock source */
|
|
RCC->CFGR0 &= (uint32_t)((uint32_t) ~(RCC_SW));
|
|
RCC->CFGR0 |= (uint32_t)RCC_SW_PLL;
|
|
/* Wait till PLL is used as system clock source */
|
|
while((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08)
|
|
{
|
|
}
|
|
}
|
|
|
|
#elif defined SYSCLK_FREQ_72MHz_HSI
|
|
|
|
/*********************************************************************
|
|
* @fn SetSysClockTo72_HSI
|
|
*
|
|
* @brief Sets System clock frequency to 72MHz and configure HCLK, PCLK2 and PCLK1 prescalers.
|
|
*
|
|
* @return none
|
|
*/
|
|
static void SetSysClockTo72_HSI(void)
|
|
{
|
|
EXTEN->EXTEN_CTR |= EXTEN_PLL_HSI_PRE;
|
|
|
|
/* Enable Prefetch Buffer */
|
|
FLASH->ACTLR |= FLASH_ACTLR_PRFTBE;
|
|
|
|
/* Flash 1 wait state */
|
|
FLASH->ACTLR &= (uint32_t)((uint32_t)~FLASH_ACTLR_LATENCY);
|
|
FLASH->ACTLR |= (uint32_t)FLASH_ACTLR_LATENCY_1;
|
|
|
|
/* HCLK = SYSCLK */
|
|
RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1;
|
|
/* PCLK2 = HCLK */
|
|
RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1;
|
|
/* PCLK1 = HCLK */
|
|
RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2;
|
|
|
|
/* PLL configuration: PLLCLK = HSI * 9 = 72 MHz */
|
|
RCC->CFGR0 &= (uint32_t)((uint32_t) ~(RCC_PLLSRC | RCC_PLLXTPRE | RCC_PLLMULL));
|
|
RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSI_Div2 | RCC_PLLMULL9);
|
|
|
|
/* Enable PLL */
|
|
RCC->CTLR |= RCC_PLLON;
|
|
/* Wait till PLL is ready */
|
|
while((RCC->CTLR & RCC_PLLRDY) == 0)
|
|
{
|
|
}
|
|
/* Select PLL as system clock source */
|
|
RCC->CFGR0 &= (uint32_t)((uint32_t) ~(RCC_SW));
|
|
RCC->CFGR0 |= (uint32_t)RCC_SW_PLL;
|
|
/* Wait till PLL is used as system clock source */
|
|
while((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08)
|
|
{
|
|
}
|
|
}
|
|
|
|
#endif
|